Slides for Lecture 23

Transcription

1 Slides for Lecture 23 ENEL 353: Digital Circuits Fall 213 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 1 November, 213

2 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 2/15 Previous Lecture Completion of discussion of glitches. Introduction to sequential logic. The SR latch.

3 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 3/15 Today s Lecture Clock signals in digital circuits. D latches. Introduction to D flip-flops. Related reading in Harris & Harris: Sections

4 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 4/15 Clock signals A clock signal in a digital circuit is a periodic square wave : 1 t H t L T C time T C is the period of the clock, also called the cycle time. The clock frequency f C is related to the period as f C = 1/T C. If the frequency of a clock is 2.5 GHz, what is its period? The duty cycle is defined as (t H /T C ) 1%. Usually t H = t L =.5T C, so the duty cycle is 5%, but that s not true for all clock signals.

5 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 5/15 Clock signals and sequential logic systems In the most common kind of sequential circuit, a common clock signal is supplied to all of the D latches and/or D flip-flops in the circuit. (D latches and D flip-flops are important sequential logic components that will be presented very soon.) In digital integrated circuit design, distributing a common clock signal to all the latches and flip-flops in the circuit is just as important as making sure V DD and ground are connected to all combinational and sequential elements.

6 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 6/15 uick review of the SR latch, part 1 R S N S R N A pulse on S sets the state drives it to 1. A pulse on R resets the state drives it to. If there are no pulses on S or R, the state maintains its value as long as the circuit is powered up. In normal operation, N =.

7 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 7/15 uick review of the SR latch, part 2 R S N Asserting S and R at the same time (in other words, making S = R = 1) should be avoided. When S = R = 1, it s possible that = N. For the NOR-based SR latch, we saw that when S = R = 1, = N =. (For a NAND-based SR latch, when S = R = 1, it turns out that = N = 1.) Behaviour of an SR latch when S and R make 1 transitions at nearly the same time is unpredictable.

8 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 8/15 The D latch A D latch has two input wires. One of them is called D, for data. The other is usually called CLK, and is usually connected to a clock signal. One way to make a D latch is with an SR latch... CLK R D S N Why is it safe to label the D latch outputs as and, rather than and N as was done for the SR latch?

9 Behaviour of a D latch slide 9 CLK R D S N Let s complete the timing diagram below, then make some notes about D latch behaviour. CLK 1 D 1 S 1 R 1 1

10 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 1/15 Symbols for D latches and D flip-flops Left: D latch. Right: D flip-flop. CLK CLK D D The symbols look very similar, but there is a really significant difference in behaviour! We ll now move on to studying D flip-flops.

11 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 11/15 D Flip-Flops: Essential components in almost all sequential circuits!!! In learning about combinational logic circuits, it would be impossible to make progress without knowing exactly what NOT, AND and OR gates do. Similarly, it is impossible to understand most sequential circuits without knowing exactly what the basic behaviour of a D flip-flop is... how the state of a D flip-flop changes in response to its input signals.

12 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 12/15 Clock edges Transitions between logic levels in a clock signal are usually called clock edges. A 1 transition is called a rising edge or a positive edge. A 1 transition is called a falling edge or a negative edge. Let s make a sketch of a clock signal and label the rising and falling edges.

13 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 13/15 A good quote from your textbook From page 114 of Harris and Harris: A D flip-flop copies D to on the rising edge of the clock, and remembers its state at all other times. Reread this definition until you have it memorized; one of the most common problems for beginning digital designers is to forget what a flip-flop does.

14 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 14/15 Learning D flip-flip behaviour by example CLK Let s complete the timing diagram. D CLK 1 D 1 1 1

15 ENEL 353 F13 Section 2 Slides for Lecture 23 slide 15/15 Upcoming topics Building a D flip-flop out of two D latches in a master-slave configuration. Registers: Storing multiple bits in collection of D flip-flops. Enabled flip-flops and resettable flip-flops. Synchronous sequential logic. Related reading in Harris & Harris: Sections , 3.3.2