How To Make A Lock Iagram From A Ircuit (Programming) To A Lock And Control A Lock On A Slave (Programmer) (Programmers) (Computer) (Time) (Control A Slave) (Power) (
|
|
|
- Sharleen Booth
- 3 years ago
- Views:
Transcription
1 4- Figure 4- lock iagram of a Sequential ircuit Inputs Outputs ombinational circuit Next state Storage elements Present state 2 Prentice Hall, Inc.
2 4-2 Figure 4-2 Logic Structures for Storing Information (a) t pd (b) t pd 2 t pd (d) 2 t pd t pd (c) 2 Prentice Hall, Inc.
3 4-3 Figure 4-3 Synchronous locked Sequential ircuit Inputs ombinational circuit lock pulses Flip-flops Outputs (a) lock diagram (b) Timing diagram of clock pulses 2 Prentice Hall, Inc.
4 4-4 Figure 4-4 S Ltch with NO Gates (eset) S Set state S (Set) eset state Undefined (a) Logic diagram (b) Function table 2 Prentice Hall, Inc.
5 4-5 Figure 4-5 Logic Simulation of S Latch ehavior S i g i t a l T 5n n 5n Time (Seconds) 2n 25n 2 Prentice Hall, Inc.
6 4-6 Figure 4-6 S Latch with NN Gates S (Set) S Set state (eset) eset state Undefined (a) Logic diagram (b) Function table 2 Prentice Hall, Inc.
7 4-7 Figure 4-7 S Latch with ontrol Input S S Next state of No change No change = ; eset state = ; Set state Undefined (a) Logic diagram (b) Function table 2 Prentice Hall, Inc.
8 4-8 Figure 4-8 Latch S (a) Logic diagram Next state of No change = ; eset state = ; Set state (b) Function table 2 Prentice Hall, Inc.
9 4-9 Figure 4-9 Latch with Transmission Gates TG TG 2 Prentice Hall, Inc.
10 4- Figure 4- S Mster-Slave Flip-Flop S S Y S Y 2 Prentice Hall, Inc.
11 4- Figure 4- Logic Simulation of a Master-Slave Flip-Flop S i g i t a l Y T 5n n 5n Time (Seconds) 2n 2 Prentice Hall, Inc.
12 4-2 Figure 4-2 Master-Slave JK Flip-Flop J K S S (a) J K (b) Next State of 2 Prentice Hall, Inc.
13 4-3 Figure 4-2 -Type Positive Edge-Triggered Flip-Flop S 2 Prentice Hall, Inc.
14 4-4 Figure 4-4 Positive Edge-Triggered JK Flip-Flop J K S 2 Prentice Hall, Inc.
15 4-5 Figure 4-5 Standard Graphic Symbols for Latch and Flip-Flops S S S S with ontrol with ontrol (a) Latches S S J K J K Triggered S Triggered S Triggered JK Triggered JK (b) Master-Slave Flip-Flops J K J K Triggered Triggered Triggered JK Triggered JK 2 Prentice Hall, Inc. (c) Edge-Triggered Flip-Flops
16 4-6 Table 4- Flip-Flop haracteristic Table (a) JK Flip-Flop (b) S Flip-Flop J K (t ) Operation S (t ) Operation (t) No change (t) No change eset eset Set Set t () omplement? Undefined (c) Flip-Flop (d) T Flip-Flop (t ) Operation T (t ) Operation eset (t) No change Set t () omplement 2 Prentice Hall, Inc.
17 4-7 Figure 4-6 JK Flip-Flop with irect Set and eset S J K S J K Undefined No change omplement (a) Graphic symbols (b) Function table 2 Prentice Hall, Inc.
18 4-8 Figure 4-7 Implementing Input Equations Y J K lock 2 Prentice Hall, Inc.
19 4-9 Figure 4-8 Example of a Sequential ircuit lock Y 2 Prentice Hall, Inc.
20 4-2 Present State Input Next State Output Y Table 4-2 State Table for ircuit of Figure Prentice Hall, Inc.
21 4-2 Table 4-3 Two-dimensional State Table for the ircuit in Figure 4-8 Present state Next state Output = -= = -= Y Y 2 Prentice Hall, Inc.
22 4-22 Figure 4-9 Logic iagram and State Table for = Y Z Y (a) lock Present state Inputs Y Next state (b) State table Output Z 2 Prentice Hall, Inc.
23 4-23 Present state Input Next state Flip-flop inputs J K J K Table 4-4 State Table for ircuit with JK Flip-Flops 2 Prentice Hall, Inc.
24 4-24 Figure 4-2 State iagrams / / / / / /, / / (a), / / (b),, 2 Prentice Hall, Inc.
25 4-25 Figure 4-2 onstruction of a State iagram / / / (a) (b) / / / / (c) / / / / / / / (d) / 2 Prentice Hall, Inc.
26 4-26 Table 4-5 State Table for State iagram in Figure 4-2 Present State Next State Output Z 2 Prentice Hall, Inc.
27 4-27 Table 4-6 Sequence Tables for ode onverter Example 2 Prentice Hall, Inc.
28 4-28 Figure 4-22 onstruction of a State iagram / / (a) (b) / / / / (c) / / / / / / / / (d) / 2 Prentice Hall, Inc.
29 4-29 Table 4-7 Table 4-5 with Names eplaced by inary odes Next State Output Z Present State Prentice Hall, Inc.
30 4-3 Present State Input Next State Output Y Table 4-8 State Table for esign Example 2 Prentice Hall, Inc.
31 4-3 Figure 4-23 State iagram for esign Example / / / / / / / / 2 Prentice Hall, Inc.
32 4-32 Figure 4-24 Maps for Input Equations and Output Y = + = + + Y = 2 Prentice Hall, Inc.
33 4-33 Figure 4-25 Logic iagram for Sequential ircuit with Flip-Flops lock Y 2 Prentice Hall, Inc.
34 4-34 Present State Input Next State Table 4-9 State Table for Second esign Example 2 Prentice Hall, Inc.
35 4-35 Figure 4-26 Maps for Simplifying Input Equations = + + = + = 2 Prentice Hall, Inc.
36 4-36 (a) JK Flip-Flop (b) S Flip-Flop (t) (t ) J K (t) (t ) S (c) Flip-Flop (d) T Flip-Flop (t) (t ) (t) (t ) T Table 4- Flip-Flop Excitation Table 2 Prentice Hall, Inc.
37 4-37 Present State Input Next State Flip-Flop Inputs J K J K Table 4- State Table with JK Flip-Flop Inputs 2 Prentice Hall, Inc.
38 4-38 Figure 4-27 Maps for J and K Input Equations J = K = 2 Prentice Hall, Inc. J = K = + =
39 4-39 Figure 4-28 Logic iagram for Sequential ircuit with JK Flip-Flops Y N Z N O T N Z N Z S J J K F F E K K N L K NZ S J J K F F E K K N 2 Prentice Hall, Inc.
40 4-4 Figure 4-29 Logic Simulation Verification for the ircuit in Figure 4-28 : : : * * : * * Y: * * * These responses are asynchronous with the cloc k and thus do not wait for the next positive clock edge. (a) ircuit test and expected results LK i g i t a l Y T 5n n 5n Time (Seconds) 2n 25n 3n (b) Simulation results 2 Prentice Hall, Inc.
41 4-4 Figure 4-3 VHL Process escription of Positive Edge-Triggered Flip-flop with eset -- Positive Edge-Triggered Flip-Flop with eset: -- VHL Process escription library ieee; use ieee.std_logic_64.all; entity dff is port(lk, ESET, : in std_logic; : out std_logic); end dff; architecture pet_pr of dff is -- Implements positive edge-triggered bit state storage -- with asynchronous reset. begin process (LK, ESET) begin if (ESET = '') then <= ''; elsif (LK'event and LK = '') then <= ; end if; end if; end process; end; 2 Prentice Hall, Inc.
42 4-42 Figure 4-3 VHL Process escription of a Sequence ecognizer -- Sequence ecognizer: VHL Process escription -- (See Figure 4-2 for state diagram) library ieee; use ieee.std_logic_64.all; entity seq_rec is port(lk, ESET, : in std_logic; Z: out std_logic); end seq_rec; architecture process_3 of seq_rec is type state_type is (,,, ); signal state, next_state : state_type; begin -- Process - state_register: implements positive edgetriggered -- state storage with asynchronous reset. state_register: process (LK, ESET) begin if (ESET = '') then state <= ; elsif (LK event and LK = '') then state <= next_state; end if; end if; end process; 2 Prentice Hall, Inc. -- Process 2 - next_state_function: implements next state as -- a function of input and state. next_state_func: process (, state) begin case state is when => if = '' then next_state <= ; else next_state <= ; end if; when => if = '' then next_state <= ; else next_state <= ; end if;
43 4-43 Figure 4-32 VHL Process escription of a Sequence ecognizer (continued) -- Sequence ecognizer: VHL Process escription (continued) when => if = '' then next_state <= ; else next_state <= ; end if; when => if = '' then next_state <= ; else next_state <= ; end if; end case; end process; -- Process 3 - output_function: implements output as function -- of input and state. output_func: process (, state) begin case state is when => Z <= ''; when => Z <= ''; when => Z <= ''; when => if = '' then Z <= ''; else Z <= ''; end if; end case; end process; 2 Prentice Hall, Inc.
44 4-44 Table 4-2 Illustration of Generation of Storage in VHL Inputs ction ESET = LK = LK event FLSE FLSE FLSE Unspecified FLSE FLSE TUE Unspecified FLSE TUE FLSE Unspecified FLSE TUE TUE <= TUE <= '' 2 Prentice Hall, Inc.
45 4-45 Figure 4-33 Verilog Process escription of Positive Edge-Triggered Flip-Flop with eset // Positive Edge-Triggered Flip-Flop with eset: // Verilog Process escription module dff_v(lk, ESET,, ); input LK, ESET, ; output ; reg ; LK or posedge ESET) begin if (ESET) <= ; else <= ; end endmodule 2 Prentice Hall, Inc.
46 4-46 Figure 4-34 Verilog Process of a Sequence ecognizer 2 Prentice Hall, Inc. // Sequence ecognizer: Verilog Process escription // (See Figure 4-2 for state diagram) module seq_rec_v(lk, ESET,, Z); input LK, ESET, ; output Z; reg [:] state, next_state; parameter = 2'b, = 2'b, = 2'b, = 2'b; reg Z; // state register: implements positive edge-triggered // state storage with asynchronous reset. LK or posedge ESET) begin if (ESET == ) state <= ; else state <= next_state; end // next state function: implements next state as function // of and state or state) begin case (state) : if ( == ) next_state <= ; else next_state <= ; : if() next_state <= ;else next_state <= ; : if() next_state <= ;else next_state <= ; : if() next_state <= ;else next_state <= ; endcase end // output function: implements output as function // of and state or state) begin case (state) : Z <= ; : Z <= ; : Z <= ; : Z <=? : ; endcase end endmodule
47 4-47 Table 4-3 Illustration of Generation of Storage in Verilog Inputs ction posegdge ESET and ESET = posedge LK FLSE FLSE Unspecified FLSE TUE <= TUE FLSE <= TUE TUE <= 2 Prentice Hall, Inc.
Engr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;
CHAPTER 11 LATCHES AND FLIP-FLOPS
CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop
Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
7. Latches and Flip-Flops
Chapter 7 Latches and Flip-Flops Page 1 of 18 7. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The
LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters
LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters LAB OBJECTIVES 1. Introduction to latches and the D type flip-flop 2. Use of actual flip-flops to help you understand sequential
ECE380 Digital Logic
ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during
Theory of Logic Circuits. Laboratory manual. Exercise 3
Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices
Memory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Min-elay
Registers & Counters
Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multi-bit storage devices. Introduce counters by adding logic to registers implementing
WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
Lecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch Edge-Triggered D Flip-Flop (FF) S-R Flip-Flop (FF) J-K Flip-Flop (FF) T Flip-Flop
Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
CSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic
To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
L4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified
Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
ECE 451 Verilog Exercises. Sept 14, 2007. James Barnes (James.Barnes@colostate.edu)
ECE 451 Verilog Exercises Sept 14, 2007 James Barnes (James.Barnes@colostate.edu) Organization These slides give a series of self-paced exercises. Read the specification of each exercise and write your
Master/Slave Flip Flops
Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave
CNC FOR EDM MACHINE TOOL HARDWARE STRUCTURE. Ioan Lemeni
CNC FOR EDM MACHINE TOOL HARDWARE STRUCTURE Ioan Lemeni Computer and Communication Engineering Department Faculty of Automation, Computers and Electronics University of Craiova 13, A.I. Cuza, Craiova,
Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012
Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
if-then else : 2-1 mux mux: process (A, B, Select) begin if (select= 1 ) then Z <= A; else Z <= B; end if; end process;
if-then else : 2-1 mux mux: process (A, B, Select) begin if (select= 1 ) then Z
Digital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register
Sequential Logic Design Principles.Latches and Flip-Flops
Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch
Modeling Latches and Flip-flops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
Lecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing
Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Flip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Verilog: always @ Blocks
Verilog: always @ Blocks hris Fletcher U Berkeley Version 0.2008.9.4 September 5, 2008 Introduction Sections. to.6 discuss always@ blocks in Verilog, and when to use the two major flavors of always@ block,
Digital Design with VHDL
Digital Design with VHDL CSE 560M Lecture 5 Shakir James Shakir James 1 Plan for Today Announcement Commentary due Wednesday HW1 assigned today. Begin immediately! Questions VHDL help session Assignment
Lecture 11: Sequential Circuit Design
Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking 2 Sequencing Combinational logic output depends on current
Set-Reset (SR) Latch
et-eset () Latch Asynchronous Level sensitive cross-coupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0-? 0-? Indeterminate cross-coupled Nand gates
Chapter 5. Sequential Logic
Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends
2 n. (finite state machines).
. - S,, T FI-FO. ;. 2. ;,,.,, (sequential).. ( )... 3. ; (state) (state variables),.,, (state)..,,..,,. 4. ;. n 2 n., 2 n,, (finite state machines). 5. (feedback).,..,.,,. 6.,,., ( ).. ,.,. 7., ( ).,..,
DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
VHDL GUIDELINES FOR SYNTHESIS
VHDL GUIDELINES FOR SYNTHESIS Claudio Talarico For internal use only 1/19 BASICS VHDL VHDL (Very high speed integrated circuit Hardware Description Language) is a hardware description language that allows
Sequential Circuits. Combinational Circuits Outputs depend on the current inputs
Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating
Counters & Shift Registers Chapter 8 of R.P Jain
Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with and without
Counters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0
ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle.
Lesson 12 Sequential Circuits: Flip-Flops
Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
Topics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology
Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Two-phase clocking. Testing of combinational (Chapter 4) and sequential (Chapter
ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog
ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();
ENEE 244 (01**). Spring 2006. Homework 5. Due back in class on Friday, April 28.
ENEE 244 (01**). Spring 2006 Homework 5 Due back in class on Friday, April 28. 1. Fill up the function table (truth table) for the following latch. How is this latch related to those described in the lectures
Combinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate K-maps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
ECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)
ECE 3401 Lecture 7 Concurrent Statements & Sequential Statements (Process) Concurrent Statements VHDL provides four different types of concurrent statements namely: Signal Assignment Statement Simple Assignment
Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)
IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) Elena Dubrova KTH / ICT / ES dubrova@kth.se BV pp. 584-640 This lecture IE1204 Digital Design, HT14 2 Asynchronous Sequential Machines
Flip-Flops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
Counters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
Finite State Machine Design and VHDL Coding Techniques
Finite State Machine Design and VHDL Coding Techniques Iuliana CHIUCHISAN, Alin Dan POTORAC, Adrian GRAUR "Stefan cel Mare" University of Suceava str.universitatii nr.13, RO-720229 Suceava iulia@eed.usv.ro,
ASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
More Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset.
More Verilog 8-bit Register with Synchronous Reset module reg8 (reset, CLK, D, Q); input reset; input [7:0] D; output [7:0] Q; reg [7:0] Q; if (reset) Q = 0; else Q = D; module // reg8 Verilog - 1 Verilog
Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts)
Dr. Greg Tumbush, gtumbush@uccs.edu Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement
Sequential Logic: Clocks, Registers, etc.
ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design
Module 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
路 論 Chapter 15 System-Level Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS
Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
Chapter 9 Latches, Flip-Flops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, Flip-Flops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
EXPERIMENT 8. Flip-Flops and Sequential Circuits
EXPERIMENT 8. Flip-Flops and Sequential Circuits I. Introduction I.a. Objectives The objective of this experiment is to become familiar with the basic operational principles of flip-flops and counters.
Modeling Registers and Counters
Lab Workbook Introduction When several flip-flops are grouped together, with a common clock, to hold related information the resulting circuit is called a register. Just like flip-flops, registers may
Asynchronous & Synchronous Reset Design Techniques - Part Deux
Clifford E. Cummings Don Mills Steve Golson Sunburst Design, Inc. LCDM Engineering Trilobyte Systems cliffc@sunburst-design.com mills@lcdm-eng.com sgolson@trilobyte.com ABSTRACT This paper will investigate
Wiki Lab Book. This week is practice for wiki usage during the project.
Wiki Lab Book Use a wiki as a lab book. Wikis are excellent tools for collaborative work (i.e. where you need to efficiently share lots of information and files with multiple people). This week is practice
ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
Chapter 8. Sequential Circuits for Registers and Counters
Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters T-FF Basic Counting element State
Timing Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency
Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking
A New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
Understanding Verilog Blocking and Non-blocking Assignments
Understanding Verilog Blocking and Non-blocking Assignments International Cadence User Group Conference September 11, 1996 presented by Stuart HDL Consulting About the Presenter Stuart has over 8 years
SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
Using Xilinx ISE for VHDL Based Design
ECE 561 Project 4-1 - Using Xilinx ISE for VHDL Based Design In this project you will learn to create a design module from VHDL code. With Xilinx ISE, you can easily create modules from VHDL code using
CS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 16 Timing and Clock Issues 1 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on
Chapter 7: Advanced Modeling Techniques
Chapter 7: Advanced Modeling Techniques Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL
Lecture-3 MEMORY: Development of Memory:
Lecture-3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,
LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER
LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER OBJECTIVES 1. Learn the basic elements of VHDL that are implemented in Warp. 2. Build a simple application using VHDL and
CHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
Asynchronous counters, except for the first block, work independently from a system clock.
Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flip-flops, they can be asynchronous or synchronous and they can
Design: a mod-8 Counter
Design: a mod-8 Counter A mod-8 counter stores a integer value, and increments that value (say) on each clock tick, and wraps around to 0 if the previous stored value was 7. So, the stored value follows
Design Verification & Testing Design for Testability and Scan
Overview esign for testability (FT) makes it possible to: Assure the detection of all faults in a circuit Reduce the cost and time associated with test development Reduce the execution time of performing
Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann
Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7- Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users
Systems I: Computer Organization and Architecture
Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store
Digital Electronics Detailed Outline
Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept
12. A B C A B C A B C 1 A B C A B C A B C JK-FF NETr
2..,.,.. Flip-Flops :, Flip-Flops, Flip Flop. ( MOD)... -8 8, 7 ( ).. n Flip-Flops. n Flip-Flops : 2 n. 2 n, Modulo. (-5) -4 ( -), (-) - ( -).. / A A A 2 3 4 5 MOD-5 6 MOD-6 7 MOD-7 8 9 / A A A 2 3 4 5
COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
Sequential Circuit Design
Sequential Circuit Design Lan-Da Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,
Upon completion of unit 1.1, students will be able to
Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal
So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
Cascaded Counters. Page 1 BYU
Cascaded Counters Page 1 Mod-N Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A mod-n counter has N states Counts from 0 to N-1 then rolls
Digital Design Verification
Digital Design Verification Course Instructor: Debdeep Mukhopadhyay Dept of Computer Sc. and Engg. Indian Institute of Technology Madras, Even Semester Course No: CS 676 1 Verification??? What is meant
Register File, Finite State Machines & Hardware Control Language
Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework
Asynchronous Counters. Asynchronous Counters
Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter
A Verilog HDL Test Bench Primer Application Note
A Verilog HDL Test Bench Primer Application Note Table of Contents Introduction...1 Overview...1 The Device Under Test (D.U.T.)...1 The Test Bench...1 Instantiations...2 Figure 1- DUT Instantiation...2
Multilevel Sequential Logic Circuit Design
International Journal of Electronics and Electrical Engineering Vol., No. 4, December, 4 Multilevel Sequential Logic Circuit Design vni Morgül FSM Vakıf University, iomedical Eng. Dept, Istanbul, Turkey
CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS
CHAPTER IX-1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249-275 FROM MANO AN KIME CHAPTER IX-2 INTROUCTION -INTROUCTION Like combinational building blocks, we can also develop
DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department
Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and
University of Toronto Faculty of Applied Science and Engineering
Print : First Name :............................. Last Name :............................. Student Number:............................................... University of Toronto Faculty of Applied Science