Figure 7.1. Control of an alarm system. Figure 7.2. A simple memory element. Figure 7.3. A controlled memory element.

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Abraham Dalton
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1 Sensor Set Memory element On Off Alarm A B Figure 7.. Control of an alarm system. Figure 7.2. A simple memory element. Load ata G A B Output Set G2 Figure 7.3. A controlled memory element. Figure 7.4. A memory element with NOR gates. R S a b S R a b // (no change) (b) ruth table R S a t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t? S Clk R b? (c) iming diagram ime Figure 7.5. A latch built with NOR gates. Figure 7.7. Gated SR latch with NAN gates.

2 P3 t su t h 2 P 5 Clk 3 P2 6 4 P4 (b) Graphical symbol Figure 7.9. Setup and hold times. Figure 7.. A positive-edge-triggered flip-flop. Preset Clear Clear Preset Clear (b) Graphical symbol Figure 7.3. Master-slave flip-flop with Clear and Preset. Figure 7.5. Synchronous reset for a flip-flop. In Out J K t t In = Out J K ( t+ ) () t () t J K t 2 t 3 t 4 t 5 t 6 (b) ruth table (c) Graphical symbol t 7 (b) A sample sequence Figure 7.7. JK flip-flop. Figure 7.8. A simple shift register.

3 Parallel output Serial input Shift/Load Parallel input Count (b) iming diagram Figure 7.9. Parallel access shift register. Figure 7.2. A three-bit up-counter. 2 2 cycle changes 2 changes Count (b) iming diagram Figure 7.2. A three-bit down-counter. able 7.. erivation of the synchronous up-counter. 2 3 Enable Clear 2 3 Count (b) iming diagram Figure A four-bit synchronous up-counter. Figure Inclusion of Enable and Clear capability.

4 Enable 2 Load Count (b) iming diagram 2 Count (b) iming diagram Figure A modulo-6 counter with synchronous reset. Figure A modulo-6 counter with asynchronous reset. Enable BC n Load Clear Enable Load BC Figure A two-digit BC counter. Figure 7.3. Johnson counter. ata Latch Figure 7.3. hree types of storage elements in a schematic. Figure Gated latch generated by CA tools.

5 module _latch (, Clk, ); input, Clk; output ; reg ; or Clk) if (Clk) = ; Figure iming simulation of storage elements. Figure Code for a gated latch. module flipflop (,, ); input, ; output ; reg ; ) = ; module example7_3 (,,, 2); input, ; output, 2; reg, 2; ) = ; 2 = ; Endmodule Figure Code for a flip-flop. Figure Incorrect code for two cascaded flip-flops. module example7_4 (,,, 2); input, ; output, 2; reg, 2; 2 ) <= ; 2 <= ; Figure Circuit for Example 7.3. Figure Code for two cascaded flip-flops.

6 module example7_5 (x, x2, x3,, f, g); input x, x2, x3, ; output f, g; reg f, g; 2 ) f = x & x2; g = f x3; Figure 7.4. Circuit defined in Figure Figure 7.4. Code for Example 7.5. x 3 x g module example7_6 (x, x2, x3,, f, g); input x, x2, x3, ; output f, g; reg f, g; x 2 f ) f <= x & x2; g <= f x3; Figure Circuit for Example 7.5. Figure Code for Example 7.6. x 3 g module flipflop (,, n, ); input,, n; output ; reg ; x x 2 f n or posedge ) if (!n) <= ; <= ; Figure Circuit for Example 7.6. Figure flip-flop with asynchronous reset.

7 module flipflop (,, n, ); input,, n; output ; reg ; ) if (!n) <= ; <= ; Figure flip-flop with synchronous reset. Figure he lpm_ff parameterized flip-flop module. Figure An adder with registered feedback. Figure iming simulation. module shift (,, w, Load, R, ); input,, w, Load; input [3:] R; output [3:] ; lpm_shiftreg shift_right (.data(r),.aclr(),.clock(),.load(load),.shiftin(w),.q()); defparam shift_right.lpm_width = 4; defparam shift_right.lpm_direction = "RIGH"; module regn (,, n, ); parameter n = 6; input [n-:] ; input, n; output [n-:] ; reg [n-:] ; n or posedge ) if (!n) <= ; <= ; Figure 7.5. Instantiation of the lpm_shiftreg module. Figure 7.5. Code for an n-bit register with asynchronous clear.

8 module muxdff (,, Sel,, ); input,, Sel, ; output ; reg ; ) if (!Sel) <= ; <= ; module shift4 (R, L, w,, ); input [3:] R; input L, w, ; output [3:] ; wire [3:] ; muxdff Stage3 (w, R[3], L,, [3]); muxdff Stage2 ([3], R[2], L,, [2]); muxdff Stage ([2], R[], L,, []); muxdff Stage ([], R[], L,, []); Figure Code for a flip-flop with a 2-to- multiplexer on the input. Figure Hierarchical code for a four-bit shift register. module shift4 (R, L, w,, ); input [3:] R; input L, w, ; output [3:] ; reg [3:] ; ) <= R; [] <= []; [] <= [2]; [2] <= [3]; [3] <= w; Figure Alternative code for a four-bit shift register. module shiftn (R, L, w,, ); parameter n = 6; input [n-:] R; input L, w, ; output [n-:] ; reg [n-:] ; integer k; ) <= R; for (k = ; k < n-; k = k+) [k] <= [k+]; [n-] <= w; Figure An n-bit shift register. module upcount (n,, E, ); input n,, E; output [3:] ; reg [3:] ; n or posedge ) if (!n) <= ; if (E) <= + ; module upcount (R, n,, E, L, ); input [3:] R; input n,, E, L; output [3:] ; reg [3:] ; n or posedge ) if (!n) <= ; <= R; if (E) <= + ; Figure Code for a four-bit up-counter. Figure A four-bit up-counter with parallel load.

9 module downcount (R,, E, L, ); parameter n = 8; input [n-:] R; input, L, E; output [n-:] ; reg [n-:] ; ) <= R; if (E) <= - ; Figure A down-counter with a parallel load. module updowncount (R,, L, E, up_down, ); parameter n = 8; input [n-:] R; input, L, E, up_down; output [n-:] ; reg [n-:] ; integer direction; ) if (up_down) direction = ; direction = -;- <= R; if (E) <= + direction; Figure Code for an up/down counter. ata Extern Bus R R 2 Rk R in R out R 2 in R 2 out Rk in Rk out Function Control circuit Figure 7.6. A digital system with k registers. Figure 7.6. etails for connecting registers to a bus. R 2 out, R 3 in R out, R 2 in R 3 out, R in R 2 out, R 3 in R out, R 2 in R 3 out, R in w w P Figure A shift-register control circuit. Figure A modified control circuit.

10 R 2 out, R 3 in R out, R 2 in R 3 out, R in Bus w R in R 2 in Rk R R 2 in Rk ata S Multiplexers S j Figure A control circuit that does not require flip-flop preset inputs. Figure Using multiplexers to implement a bus. module regn (R, Rin,, ); parameter n = 8; input [n-:] R; input Rin, ; output [n-:] ; reg [n-:] ; ) if (Rin) <= R; module trin (Y, E, F); parameter n = 8; input [n-:] Y; input E; output [n-:] F; wire [n-:] F; assign F = E? Y : 'bz; Figure Code for an n-bit register of the type in Figure 7.6. Figure Code for an n-bit tri-state module. module shiftr (n, w,, ); parameter m = 4; input n, w, ; output [:m] ; reg [:m] ; integer k; n or posedge ) if (!n) <= ; for (k = m; k > ; k = k-) [k] <= [k-]; [] <= w; Figure Code for the shift register in Figure Figure iming simulation.

11 Figure A digital system that implements a simple processor. able 7.2. Operations performed in the processor. I I I 2 I 3 X X X 2 X 3 Y Y Y 2 Y 3 y y y 2 y 3 y y y 2 y 3 y y y 2 y to-4 decoder w w En 2-to-4 decoder w w En 2-to-4 decoder w w En y y y 2 y 3 2-to-4 decoder w w En Clear Up-counter FR in Function Register f f Rx Rx Ry Ry Function Figure A part of the control circuit for the processor. Figure he function register and decoders. module upcount (Clear,, ); input Clear, ; output [:] ; reg [:] ; ) if (Clear) <= ; <= + ; able 7.3. Control signals asserted in each operation/time step. Figure A two-bit up-counter with synchronous reset.

12 module reaction (c9,, w, Pushn, LEn, igit, igit); input c9,, w, Pushn; output LEn; output [:7] igit, igit; wire LEn; wire [:7] igit, igit; reg LE; wire [3:] BC, BC; c9) if (Pushn == ) LE <= ; if (w) LE <= ; assign LEn = ~LE; BCcount counter (c9,, LE, BC, BC); seg7 seg (BC, igit); seg7 seg (BC, igit); Figure iming simulation of the processor. Figure Code for the reaction timer. Figure Simulation of the reaction-timer circuit. Figure P7.. iming diagram for problem 7.. A 2 C E B Figure P7.2. Circuit for problem 7.9. Figure P7.3. he circuit for problem 7.8.

13 J S S K Clk R Clk R f Figure P7.4. he circuit for problem 7.9. Figure P7.5. A ring oscillator. A Interval ns A Figure P7.6. iming of signals for problem 7.3. Figure P7.7. Circuit and timing diagram for problem Start f g module lfsr (R, L,, ); input [:2] R; input L, ; output [:2] ; reg [:2] ; ) <= R; <= {[2], [] ^ [2], []}; Figure P7.8. iming diagram for problem Figure P7.9. Code for a linear-feedback shift register.

14 module lfsr (R, L,, ); input [:2] R; input L, ; output [:2] ; reg [:2] ; ) <= R; <= {[2], [], [] ^ [2]}; module lfsr (R, L,, ); input [:2] R; input L, ; output [:2] ; reg [:2] ; ) <= R; [] = [2]; [] = [] ^ [2]; [2] = []; Figure P7.. Code for a linear-feedback shift register. Figure P7.. Code for problem module lfsr (R, L,, ); input [:2] R; input L, ; output [:2] ; reg [:2] ; ) <= R; [] = [2]; [] = []; [2] = [] ^ [2]; Figure P7.2. Code for problem 7.38.

Flip-Flops, Registers, Counters, and a Simple Processor

June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number