PART B (Answer all five units, 5 X 10 = 50 Marks) UNIT I

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1 B.Tech II Year I Semester () Supplementary Examinations November/December 2016 SWITCHING THEY & LOGIC DESIGN (Common to ECE and EIE) (a) What is the decimal equivalent of hexadecimal number 1A53? (b) Simplify the following Boolean expression: (A BC ) + (AB C). (c) Simplify the following function using K- map: F(x, y, z) = Σ(2, 3, 4, 5). (d) Construct a logic circuit using NAND gates only for the expression x = A.(B + C). (e) What do you understand by Combinational logic circuits? Give example. (f) What is multiplexer? Draw the block diagram of 4-input MUX. (g) What is the difference between latch and flip flop? (h) What is shift register? List out some applications of Shift Register. (i) How race around condition can be eliminated? (j) What are hazards in digital logic circuits? How they can be resolved? 2 Simplify the following identities using Boolean algebra: (a) (A+B)(A+(AB) )C+A (B+C )+A B+ABC. (b) 3 (a) Simplify and draw the logic diagram for the given expression: F = (ABC) + (AB) C+ A BC + A(BC) + AB C (b) Simplify the expressions using Boolean postulates: F= XY + (XZ) + XY Z (XY + Z). I 4 (a) Simplify the following expression using the K-map: Y = A B C + AC D + AB + ABCD + A B C (b) Write the expression for Boolean function F (A, B, C) = m (1, 4, 5, 6, 7) in standard POS form. 5 Simplify the following expression to sum of products using Tabulation Method: F(a, b, c, d)= m(0,4,8,10,12,13,15) +d(1,2) 6 Discuss in detail, the working of full adder logic circuit and extend your discussion to explain a binary adder, which can be used to add two binary numbers. 7 (a) Draw the logic circuit of a 3 to 8 decoder and explain its working. (b) Explain the working of a De-multiplexer with the help of an example. V 8 Using D-Flip flops and waveforms, explain the working of a 4-bit SISO shift register. 9 With the help of clocked JK flip flops and waveforms, explain the working of a 3-bit binary ripple counter. Write truth table for clock transitions. 10 Difference between static and dynamic RAM. Draw the circuits of one cell of each and explain its working. 11 Is the ROM a volatile memory? Explain. Also draw the logic diagram of 16-bit ROM Array and explain its principle of operation.

2 /SS B.Tech II Year II Semester () Supplementary Examinations December/January 2015/2016 SWITCHING THEY & LOGIC DESIGN (Common to EEE and ECE) (a) State and Prove consensus theorem. (b) Find the 2 s complement of representation of -9. (c) Design a X gate using minimum number of NAND gates. (d) Find the minimum number of literals for the following function using 2 variable Karnaugh Map. F = = m (1) + d (3). d - Don t care. (e) Write the sum and carry expression for half adder. (f) Implement the function F = m (0, 2) using a 2 4 decoder. (g) Write the characteristic equation for JK Flip-flop. (h) How many states are there in a n-bit ring counter? (i) Compare PROM & PAL. (j) What is meant by cycle in asynchronous circuits? 2 (a) Express the following function F = xy + x y in a product of max-terms. (b) Check if N gate is associative or not. 3 (a) Show that a positive logic NAND gate is a negative logic gate (b) Obtain the truth table of the following function and express in sum of min-terms and product of maxterms: F = (A + B).(B + C). I 4 Simplify the Boolean function using K map technique: (a) F = π M (3, 4, 6, 7, 11, 12, 13, 14, 15). (b) F = m (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14). 5 Simplify the following Boolean function using tabulation method: F = m (0, 1, 2, 3, 5, 7, 8, 10, 14, 15). 6 Design a 4-Bit Magnitude comparator using logic gates. 7 (a) Implement the function F = m (0, 1, 2, 4, 5, 8, 11, 12, 15) using 8:1 multiplexer. (b) Design a half subtractor using logic gates. V 8 Design a 4 bit universal shift register with neat diagram. 9 Design a 3 bit synchronous up counter using T Flip-flops. 10 Implement the following functions using PLA with three inputs, four product terms and two outputs. F1 (A, B, C) = m (3, 5, 6, 7), F2 (A, B, C) = m (0, 2, 4, 7). 11 Implement the switching function F = m (1, 3, 5, 7, 8, 9, 14, 15) by a static hazard free two level AND- network.

3 B.Tech II Year I Semester () Regular & Supplementary Examinations December 2015 SWITCHING THEY & LOGIC DESIGN (Common to ECE and EIE) (a) State and prove De-Morgans theorem. (b) What do you understand by universal gate? (c) Convert the given equation Y=AB+AC +BC into standard SOP form. (d) Implement the following Boolean equation using only NAND gates Y=AB+CDE+F. (e) Draw the logic diagram of full adder circuit and form the truth table. (f) What is multiplier? Draw the block diagram of 4-input MUX. (g) Give the comparison between combinational circuits and sequential circuits. (h) What is shift register? Give the classification of them. (i) What are the steps involved in designing an asynchronous sequential circuits? (j) What are hazards in digital logic circuits? How it can be resolved? 2 Simplify the following Boolean expression: (i) F = (A+B)(A +C)(B+C). (ii) F = A+B+C +D(E+F) 3 (a) Expand the following Boolean functions F = xy+x zin a standard product of maxterm form. (b) Minimize the following Boolean function: f(a,b,c,d)= m(5,7,8,10,13,15)+ d(0,1,2,3). I 4 (a) Simplify the following expression using the K-map for the 4-variable: Y = AB C+A BC+A B C+A B C +AB C (b) Implement the following Boolean function using N gates Y=(AB +A B)(C+D ). 5 Simplify the Boolean function by using tabulation method. F(a,b,c,d)= m(0,1,2,5,6,7,8,9,10,14) 6 Discuss in detail about the design procedure for binary serial and parallel adder with diagram. 7 Implement a 2-bit Magnitude comparator and write down its design procedure. V 8 A sequential circuit with two D-flip flops A and B, two inputs x and y and one output z is specified by the following next state and output equation. A(t+1) = x y+xa, B(t+1) = x B+xA and Z = B (i) Draw the logic diagram of the circuit. (ii) List the state table and draw the corresponding state diagram. 9 Design and implement 3-bit ripple counter using J-K flip flop. Draw the state diagram, logic diagram and timing diagram for the same. 10 What is critical and non-critical races in asynchronous circuits? How to avoid races? Illustrate with one example. 11 Design and implement the following Boolean functions in PAL. (a) A(w,x,y,z)= m(0,2,6,7,8,9,12,13) (b) B(w,x,y,z)= m(0,2,6,7,8,9,12,13,14) (c) C(w,x,y,z)= m(1,3,4,6,10,12,13) (d) D(w,x,y,z)= m(1,3,4,6,9,12,14)

4 B.Tech II Year I Semester () Supplementary Examinations June 2015 SWITCHING THEY AND LOGIC DESIGN (Common to ECE & EIE) PART - A (a) Find the complement of the function and show that. (b) Perform the subtraction operation on 22-7 using 2 s complement form. (c) Convert the expression in standard POS form. (d) Simplify (e) Obtain the prime implicates for given Boolean expression. using k-map. (f) Design a 4 bit parallel adder using Full adders. (g) Explain how decoder can be converted into a demultiplexer with a neat block diagram. (h) Compare PROM, PLA & PAL. (i) Compare level and edge triggering. (j) Assume that the 5 bit binary counter starts in the 0000 state then what will be the count after 144 input pulses. PART - B UNIT - I 2 Encode the decimal number 365 in (i) Binary (ii) BCD (iii) ASCII (iv) Excess 3. 3 Given the 8 bit data word generate the 12 bit composite word for the hamming code that corrects and detects single errors. UNIT - II 4 (a) Implement the Boolean expression for Ex- gate using NAND gates. (b) Simplify the Boolean expression to one literal. 5 (a) Implement Ex- N gate using only N gates. (b) Use the K-map method to simplify the following 5-variable function UNIT - III 6 (a) What is a decoder? Construct decoder using logic gates and also write truth table. (b) Design a 4 bit odd parity generator. Mentions its truth table. 7 (a) Implement the following Boolean function using 8:1 multiplexer. (b) Design a 2 bit comparator using gates. UNIT - IV 8 (a) Construct a JK flip-flop using D flip-flop, multiplexer and an inverter. (b) Convert SR flip flop to T flip flop. 9 Define the following terms in connection with a flip-flop (i) Setup time (ii) Hold time (iii) Propagation delay time (iv) Preset (v) Clear. Page 1 of 2 Contd. in page 2

5 10 A sequential circuit has one input and one output. The state diagram is shown below: Design the sequential circuit with (a) D flip-flop (b) RS flip-flop (c) JK flip-flop. 11 (a) Implement the following Boolean function using PLA (b) What is hazard in switching circuits? Explain the design of hazard free switching circuit with an example. Page 2 of 2

6 B.Tech II Year I Semester () Regular Examinations December 2014 SWITCHING THEY & LOGIC DESIGN (Common to ECE and EIE) (a) If = X 6, then X is.. (b) Minimum number of two input NAND gates required to implement Y = A + B C. (c) What is the importance of don t care conditions? (d) SOP of F(x, y, z)= (2, 3, 6, 7). (e) Implement gate using only two input NAND gates? (f) Draw the block diagram of 2x4 decoder with enable. (g) Draw the block diagram of sequential circuit using combinational circuit and memory unit. (h) Draw the logic circuit of flip-flop and truth table using N gates. (i) What is the function of EAROM? (j) Mention few applications of PLA. 2 (a) Convert the following to Decimal and then to Octal. (i) (ii) (b) Implement the function with N-N logic Y= A C + B C + A B+ D. 3 (a) Convert the following to Decimal and then to Hexadecimal. ( i) (ii) (b) Find the complement of the following Boolean function and reduce into minimum number of literals. Y= BC +A D)(DB +CD I 4 Simplify the following Boolean expressions using K-map and implement them using NAND gates. F(W,X,Y,Z)= XZ+W XY +WXY+W YZ+WY Z 5 Simplifying the following expression using tabulation technique. F= m(0,1,2,8,9,15,17,21,24,25,27,31) 6 (a) Design a 4 bit binary-to-gray code converter. (b) Realize a 2-bit comparator. 7 (a) Design a 4 bit binary-to-bcd code converter. (b) Design 32:1 Mux using two 16:1 Muxs and one 2:1 Mux. V 8 (a) Draw the circuit of JK flip flop using NAND gates and explain its operation. (b) Design a 2-input 2-output detector which produces an output 1 every time the sequence 0101 is detected. Implement the sequence detector using JK flip-flops. 9 (a) Convert S-R flip flop into JK-flip flop. Draw and explain the logic diagram. (b) A clocked sequential circuit with single input x and single output z produces an output z=1 whenever the input x compares the sequence 1011 and overlapping is allowed. Obtain the state diagram, state table and design the circuit with D flip-flops. 10 (a) Explain about ROM and PROM. (b) Design a BCD to excess-3 code converter using ROM. 11 (a) What is Race-free state Assignment? Explain. (b) Realize f= m(0,2,3,7,9,11,15,16) using ROM.