5 Combinatorial Components. 5.0 Full adder. Full subtractor

Transcription

1 5 Combatorial Components Use for data transformation, manipulation, terconnection, and for control: arithmetic operations - addition, subtraction, multiplication and division. logic operations - AND, OR, XOR, and NOT. comparison operations - greater than, equal to, and less than. bit manipulation operations - shift, rotation, extraction, and sertion. terconnect components - selectors, and buses - used to connect different components together. conversion components - decoders and encoders - used for conversion between different codes. universal components - ROMs and programmable-logic arrays (PLAs) - used primarily the design of control units. 5. Full adder x i y i c i c i+ s i i c i+ = x i ' y i ' c i + x i ' y i c i ' + x i y i ' c i ' + x i y i c i = (x i ' y i + x i y i ') c i ' + (x i ' y i ' + x i y i ) c i = (x i y i ) c i ' + (x i ~ y i ) c i = (x i y i ) c i = x i ' y i c i + x i y i ' c i + x i y i c i ' + x i y i c i = x i y i (c i ' + c i ) + c i (x i ' y i + x i y i ') = x i y i + c i (x i y i ) x i y i X c i+ c i Cout C S Circuit for Full Adder s i Full subtractor b x y b out d Comment x-b -y = d = - = -- = borrow 2- = --= with no borrow --= with no borrow x=-=- because of b =, therefore, borrow 2-=. Fally, -= x-b -y=borrow 2--= --= with no borrow x-b =-=. Then -=borrow 2-=

2 2 x'y 2 x'b yb xy b xy b b = x b + x y + yb out x y d = x y b = b = b = b + xyb ( x y + xy) + b ( x y + xy ) ( x y) + b ( x y) x y + x yb + xy b b X b out b out FS b d Circuit for Full Subtractor 5. Ripple-carry adders d x 7 y 7 x 6 y 6 x 5 y 5 x 4 y 4 x y x 2 y 2 x y x y c out c 7 c 6 c c c 5 c 4 2 c c s 7 s 6 s 5 s 4 s s 2 s s 5. Adder / Subtractor S x 7 y 7 x 6 y 6 x 5 y 5 x 4 y 4 x y x 2 y 2 x y x y S Function Comment X + Addition X + + Subtraction c c 6 c c out 5 c c 4 2 c 7 c c f 7 f 6 f 5 f 4 f f 2 f f 5.4 Logic Unit

3 5.5 Arithmetic-Logic Unit (ALU) a b a 2 b 2 a b a b S S M c c c 4 c 2 c Overflow f f 2 f f Arithmetic Extender () The modifies the second operand and passes it to the to perform the arithmetic. M S S Function Name Function X c Decrement A A all s Add A + B A B Subtract A + B + A B Increment A + A all s Functional table M S S b i y i Truth table SS bi 2 y i = MS b i + MS b i Map representation S'b'i S'bi S S M b i y i = MS S b i + MS S b i + MS S b i + MS S b i = MS b i (S + S ) + MS b i (S + S ) = MS b i + MS b i y i Schematic diagram

4 Logic Extender () The logic operations are performed the logic extender. The s are used simply as connections for the outputs. M S S Function Name Function X c Complement A A AND A AND B A AND B Identity A A OR A OR B A OR B Functional table a i b i M S S x i Indices map a i, 4 a i b i a i, 4 a i + b i 7,, 5 X X a i pass to Truth table S S M x i Schematic diagram M = M = SS ai bi S S M a i b i x i = M S S a i + M S S b i + S a i b i + S a i + Ma i Map representation Simplified schematic diagram x i Carry signal c Notice that the functional table, c = MS Overflow signal c 4 The carry-out of the most significant bit represents an overflow the case of unsigned arithmetic. Overflow The XOR of the carry-outs of the two most significant bits represents the overflow the case of 2 s complement arithmetic.

5 5.6 Decoders / Demultiplexers To enable only one of n components. E A A C C 2 C C A A E Decoder 2 C C 2 C C 2-to-4 Decoder E A 2 A A E E E E E E E C 7 C 6 C 5 C 4 C C 2 C C -to-8 decoder implemented with -to-2 decoders 5.7 s / Multiplexers (MUX) S S D D D 2 D S S D D 2 D D 2 MUX 4-to- MUX D 7 D 6 D 5 D 4 D D 2 D D D 7 D 6 D 5 D 4 D D 2 D D S S S S S S S S S S 2 Decoder S S 2 S 8-to- mux implemented with 2-to- muxes y y 8-to- mux implemented with a decoder

6 5.8 Buses A bus is for connectg several components together, however, only one component can send data to the bus at any one time. To construct a bus, use a tristate driver, whose output provides three different values,,, and Z. The value Z represents a high-impedance state which can be thought of as a disconnection from the bus. E D E D Bus E Z D 5.9 Priority Encoders A priority encoder has: n puts, D n-, D, m outputs, A m-, A, where n = 2 m, which represents the dex (decimal value) of the most significant put bit D i that has a value equal to. an additional output call Any, which will be whenever any of the puts has a value that is different from. 2-to- priority encoder D D Encoder Any A 4-to-2 priority encoder D D 2 D 2 Encoder Any A A D D D A Any X D D 2 D D A A Any X X X X X X 5. Magnitude Comparators A comparator compares two positive tegers X and and then generates two boolean results G and L as follows: Test G L X > X X < X X X = For the n-bit tegers X and, we compare them one bit at a time, startg with the most significant bit, G i = (x i > y i ) or [(x i = y i ) and (G i- > L i- )] L i = (x i < y i ) or [(x i = y i ) and (G i- < L i- )]

7 x y x y G L a b a b a b a b G = a b + a a b + b a b 2 x y x y G L = a b + a a b + b a b L 5. Shifters and Rotators Use selectors to implement. S 2 S S Comment D No shift Not used ShiftLeft(D) Shift left RotateLeft(D) Rotate left ShiftRight(D) Shift right RotateRight(D) Rotate right

8 Left Input S d d 2 d d Right Input S S 2 y y 2 y y 5.2 Read-Only Memories ROMs can be thought of as a universal logic element that is able to implement concurrently several different Boolean functions that are defed on the same set of variables. A 6 4 ROM can implement 4 functions. Programmable ANDs and ORs. a a b c d b c = d a a b c d b c = d Use a 6 4 ROM to implement the followg two functions: f = w x' y' z + w x' y z' + w' x y' z' f = x y + w' z + w x' y OR array z y x w A A A 2 A to-6 7 decoder f f

9 5. Programmable Logic Arrays (PLA) ROMs are not very efficient when we use them to implement sparse functions, i.e. functions with only a small number of s because such cases, many of the words the ROM will have a value of, which is a waste of silicon area. A PLA differs from a ROM the address decoder. Instead of a full decoder, PLAs use a programmable decoder call an AND array. Use a PLA to implement the followg two functions: f = w x' y' z + w x' y z' + w' x y' z' f = w' x y + w y' z M S S A A 2 A b A OR array AND array output array f f 2 f f c y