United States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1


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1 United States Naval Academy Electrical and Computer Engineering Department EC262 Exam 29 September 2. Do a page check now. You should have pages (cover & questions). 2. Read all problems in their entirety. Answer the question asked. 3. Work neatly and show all of your work to receive maximum partial credit. 4. Explicitly state any assumptions and highlight your final answer. 5. You have minutes to complete the examination. 6. When directed by your instructor, you may commence work. 7. No calculators are permitted. I will not discuss this exam with anyone until after 2 nd period on Friday 3 September 2. (Signature) Page Points Possible TOTAL Name: Section EC262 Fall 2 Page of
2 ) [5 pts] Use the Karnaugh maps to find one minimum SOP (2 possible solutions) and one minimum POS expressions for the following logic function: f = b'c' + bc + c'd' (or bd' ) f = (b' + c + d' ) (b + c' ) (,,, ) = (,, 4, 6, 7,8,5) + ( 9,,2,4) f abcd m d Minimum SOP: f(a,b,c,d) = Minimum POS: f(a,b,c,d) = EC262 Fall 2 Page 2 of
3 2) [2 pts] Using Boolean (switching) algebra, reduce the expressions below to a minimum sum of products expression. Indicate the property BY NUMBER that you used. x' y' z' a) (4 pts) f(w, x, y, z) = (x' y' + z')(x' y' + z) (x y' z + x' z') ( term and 3 literals) b) (4 pts) f(w, x, y, z) = x' y' z' + x' y' z + x' y z +x y' z' (2 terms and 4 literals) y' z' + x' z c) (4 pts) f(a, b, c) = a + (a + b + c) ' + b' c (2 terms and 2 literals) a + b' EC262 Fall 2 Page 3 of
4 3) [5 pts] Binary analysis. Show ALL WORK! (just an answer will not suffice) a) (4 pts) What are the maximum negative number and the maximum positive number (in decimal) of a 2 s complement number that has 7 bits? 63 N 64 b) (4 pts) What is the minimum number of bits you need to represent C 6 unique values? How many unused unique combinations will there be? 32 unique combinations 4 unused unique combinations c) (7 pts) Suppose we use 6 bits to store signed numbers (2 s complement). Compute f = a  b. Show a, b and f in decimal as well as binary. Indicate if overflow does or does not occur. Show all carry bits. a = 2 b = 2 f = a  b f = 2 f= 2 (6) = 6 No overflow Write your signed binary result here: Write your signed decimal result here: Overflow occurred? (YES or NO) EC262 Fall 2 Page 4 of
5 4) [2 pts] The figure below shows an intersection of a main highway with a secondary access road. Vehicle detection sensors are placed along lanes A, B, C and D. The sensors outputs are LOW () when no vehicle is present and HIGH () when a vehicle is present. The intersection traffic light is to be controlled according to the following logic: The eastwest (EW) traffic light will be green whenever both lanes C and D are occupied. The EW traffic light will be green whenever either C or D lane is occupied but lanes A and B are not both occupied. The northsouth (NS) traffic light will be green whenever both lanes A and B are occupied but C and D are not both occupied. The NS traffic light will be green whenever either A or B lane is occupied and C and D are both vacant. The EW traffic light will be green whenever no vehicles are present. A C E N S W D B a) (8 pts) Develop a truth table for a logic circuit to control the EW and NS traffic lights at this intersection (assume that logic = green light). EC262 Fall 2 Page 5 of
6 b) (6 pts) Find the minimum SOP expressions for the outputs of this circuit. EW = CD + A'B' + A'D + A'C + B'D + B'C NS = BC'D' + AC'D'+ ABC' + ABD' c) (6 pts) Draw a block diagram for the circuit that controls the NS traffic light. Assume that only uncomplemented inputs are available. EC262 Fall 2 Page 6 of
7 5) [8 pts] The figure below shows a logic circuit and a symbol for a bit comparator (a=b,a<b,a>b). a b A circuit for a bit comparator = < > bit comparator a symbol for a bit comparator = < > a) (3 pts) If the propagation delay for each gate is Δ (assume that the propagation delay of an inverter is already included in Δ), find the worst case propagation delay for this bit comparator. = 2Δ < 2Δ > 2Δ b) (5 pts) A 3bit comparator can be built by cascading 3 bit comparators as shown below, find the total (worstcase) propagation delay for this 3bit comparator. For full credit, explain or show on the figure how you obtain your answer. A 2 B 2 A B A B = = bit comparator bit comparator bit comparator < > 5Δ EC262 Fall 2 Page 7 of
8 6) [ pts] The truth table for a logic controller is shown below. Draw a block diagram of this circuit using only 2to4 decoders (shown below) and OR gates. Note that you cannot use an inverter in your circuit. xyz f g 2to4 decoder x 2to4 Decoder 2 3 y z 2to4 Decoder 2 3 f y z 2to4 Decoder 2 3 g EC262 Fall 2 Page 8 of
9 7) [ pts] We want to build a circuit to compute the of a 6bit number A (A 5 A 4 A 3 A 2 A A ). The is defined as if and only if there are an odd number of s in the number (For example: if A = then = ; if A = then = ). One way of doing this is to build the circuit bit at a time (as in the adder), such that the circuit computes the after that bit as a function of the up to that bit and the one input bit. A block diagram of such a circuit is shown below. A 5 A 4 A 3 A 2 A A Parity bit P 4 bit P 3 bit P 2 bit P bit P bit a) (5 pts) Show a circuit to compute bit using AND, OR and NOT gates only. Assume that inputs are available only uncomplemented. A i P i P (i) b) (2 pts) If the propagation delay for each gate is Δ, compute the maximum delay for each module ( bit circuit in part a). Again, assume that inputs are available only uncomplemented. State any assumptions made. 3 Δ c) (3 pts) Compute the total (worstcase) delay for 6bits. 8 Δ EC262 Fall 2 Page 9 of
10 8) [ pts] Design a circuit that accepts a 4bit input signed number (2 s complement) and produces the absolute value of that number. Assume the following components are available: Full adders AND, OR, NOT, and XOR gates. Draw a block diagram for this circuit using as many of these components as needed. X 3 X 2 X X FA FA FA Y 3 Y 2 Y Y EC262 Fall 2 Page of
11 EC262 Fall 2 Page of
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