CSE140: Components and Design Techniques for Digital Systems

Transcription

1 CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing

2 What we covered thus far: Number representations Logic gates Boolean algebra Introduction to CMOS HW#2 due, HW#3 assigned Where we are going: Logic representations SOP and POS K-maps lgorithm for simplification Where we are now 2

3 Combinational Circuit Introduction Digital circuit We ll start with a simple form of circuit: Combinational circuit digital circuit whose outputs depend solely on the present combination of the circuit inputs values Built out of simple components: switches and gates a b a b Combinational digital circuit Sequential digital circuit? F F 3

4 Combinational Logic Design Process 2.7 Step Step Capture the function Description Create a truth table or equations to describe the desired behavior of the combinational logic. Step 2 Convert to equations This step is only necessary if you captured the function using a truth table instead of equations. Simplify the equations if desired. Step 3 Implement as a gatebased circuit For each output, create a circuit corresponding to the output s equation. 4

5 Example: Three s Detector Problem: Detect 3 consecutive s in 8-bit input: abcdefgh a Step : Capture the function Truth table or equation? a b c d abc bcd Step 2: Convert to equation e f cde def y Step 3: Implement with gates g efg fgh h 5

6 Example: Seat Belt Warning Light System Design circuit for warning light Sensors s=: seat belt fastened k=: key inserted p=: person in seat Capture logic equation What are conditions for warning light to go on? Convert equation to circuit 6

7 Example: Number of s Count Problem: Output in binary on two outputs yz the number of s on three inputs Step : Capture the function Truth table or equation? Step 2: Convert to equation Step 3: Implement as gates a b c a b c a y a b c a b c a b c z b a b c 7

8 Design example: -bit binary adder Inputs:, B, Carry-in Outputs: Sum, Carry-out Cout Cin B B B B B S S S S S B Cin Cout S B Cin S Cout 8

9 CSE4: Components and Design Techniques for Digital Systems Representation of logic functions Tajana Simunic Rosing 9

10 Canonical Form -- Sum of Minterms Truth tables are too big for numerous inputs Use standard form of equation instead Known as canonical form Regular algebra: group terms of polynomial by power ax 2 + bx + c (3x 2 + 4x + 2x > 5x 2 + 4x + 4) Boolean algebra: create a sum of minterms Minterm: product term with every literal (e.g. a or a ) appearing exactly once Determine if F(a,b)=ab+a is same function as F(a,b)=a b +a b+ab, by converting the first equation to the canonical form

11 Sum-of-products canonical forms lso known as disjunctive normal form Minterm expansion: F = F = B C + BC + B C + BC + BC B C F F F = B C + BC + B C

12 Sum-of-products canonical form (cont d) Product minterm NDed product of literals input combination for which output is each variable appears exactly once, true or inverted (but not both) B C minterms B C m B C m BC m2 BC m3 B C m4 B C m5 BC m6 BC m7 short-hand notation for minterms of 3 variables F in canonical form: F(, B, C) = m(,3,5,6,7) = m + m3 + m5 + m6 + m7 = B C + BC + B C + BC + BC canonical form minimal form F(, B, C) = B C + BC + B C + BC + BC = ( B + B + B + B)C + BC = (( + )(B + B))C + BC = C + BC = BC + C = B + C 2

13 Product-of-sums canonical form lso known as conjunctive normal form lso known as maxterm expansion Implements zeros of a function B C F F F = F = ( + B + C) ( + B + C) ( + B + C) F = ( + B + C ) ( + B + C ) ( + B + C ) ( + B + C) ( + B + C ) 3

14 Product-of-sums canonical form (cont d) Sum term (or maxterm) ORed sum of literals input combination for which output is false each variable appears exactly once, true or inverted (but not both) B C maxterms +B+C M +B+C M +B +C M2 +B +C M3 +B+C M4 +B+C M5 +B +C M6 +B +C M7 short-hand notation for maxterms of 3 variables F in canonical form: F(, B, C) = M(,2,4) = M M2 M4 = ( + B + C) ( + B + C) ( + B + C) canonical form minimal form F(, B, C) = ( + B + C) ( + B + C) ( + B + C) = ( + B + C) ( + B + C) ( + B + C) ( + B + C) = ( + C) (B + C) 4

15 Mapping between canonical forms Minterm to maxterm conversion use maxterms whose indices do not appear in minterm expansion e.g., F(,B,C) = m(,3,5,6,7) = M(,2,4) Maxterm to minterm conversion use minterms whose indices do not appear in maxterm expansion e.g., F(,B,C) = M(,2,4) = m(,3,5,6,7) Minterm expansion of F to minterm expansion of F use minterms whose indices do not appear e.g., F(,B,C) = m(,3,5,6,7) F (,B,C) = m(,2,4) Maxterm expansion of F to maxterm expansion of F use maxterms whose indices do not appear e.g., F(,B,C) = M(,2,4) F (,B,C) = M(,3,5,6,7) 5

16 Incompletely specified functions Example: binary coded decimal increment by BCD digits encode the decimal digits 9 B C D W X Y Z X X X X X X X X X X X X X X X X X X X X X X X X Don t cares and canonical forms so far, only represented on-set also represent don t-care-set need two of the three sets (on-set, off-set, dc-set) off-set of W on-set of W don t care (DC) set of W these inputs patterns should never be encountered in practice "don t care" about associated output values, can be exploited in minimization 6

17 lternative two-level implementations of F = B + C B C F F2 canonical sum-of-products minimized sum-of-products F3 canonical product-of-sums F4 minimized product-of-sums 7

18 CSE4: Components and Design Techniques for Digital Systems Logic simplification Tajana Simunic Rosing 8 Sources:

19 Key to simplification: the uniting theorem Uniting theorem: (B + B) = Essence of simplification of two-level logic find two element subsets of the ON-set where only one variable changes its value this single varying variable can be eliminated and a single product term used to represent both elements F = B +B = ( +)B = B B F B has the same value in both on-set rows B remains has a different value in the two rows is eliminated 9

20 Boolean cubes Visual technique for applying the uniting theorem n input variables = n-dimensional "cube" -cube X Y X 2-cube 3-cube Y Z 4-cube X Y Z X W 2

21 Mapping truth tables onto Boolean cubes Uniting theorem combines two faces" of a cube into a larger face" Example: B F B F two faces of size (nodes) combine into a face of size (line) varies within face, B does not this face represents the literal B' ON-set = solid nodes OFF-set = empty nodes DC-set = 'd nodes 2

22 Three variable example Binary full-adder carry-out logic ('+)BCin B Cin Cout B C B(Cin'+Cin) (B+B')Cin the on-set is completely covered by the combination (OR) of the subcubes of lower dimensionality - note that is covered three times Cout = BCin+B+Cin 22

23 Higher dimensional cubes Sub-cubes of higher dimension than 2 F(,B,C) = m(4,5,6,7) on-set forms a square - a cube of dimension 2 B C In a 3-cube (three variables): This subcube represents the literal a -cube, i.e., a single node, yields a term in 3 literals a -cube, i.e., a line of two nodes, yields a term in 2 literals a 2-cube, i.e., a plane of four nodes, yields a term in literal a 3-cube, i.e., a cube of eight nodes, yields a constant term "" In general, an m-subcube within an n-cube (m < n) yields a term with n m literals 23

24 Flat map of Boolean cube wrap around at edges Karnaugh maps hard to draw and visualize for more than 4 dimensions virtually impossible for more than 6 dimensions lternative to truth-tables to help visualize adjacencies guide to applying the uniting theorem on-set elements with only one variable changing value are adjacent unlike the situation in a linear truth-table B 2 3 B F 24

25 Karnaugh maps (cont d) Numbering scheme based on Gray code e.g.,,,, only a single bit changes in code for adjacent map cells C C B B 6 4 B C C D 5 B 4 C 3 B

26 F = Cout = Karnaugh map examples B Cin B f(,b,c) = m(,4,5,7) C C B B C B 26

27 CSE4: Components and Design Techniques for Digital Systems Logic simplification cont. Tajana Simunic Rosing 27 Sources:

28 ~ 5 5 ~ ~ 5 5 ~ 2 2 ~ ~ 3 3 ~ ~ 4 4 ~ ~ 5 5 ~ ~ 6 6 ~ ~ 7 7 ~ ~ 8 8 ~ ~ 9 9 ~ ~ Students (%) CSE4a HW2 Stats 3.% 2.%.%.% HW2 Grade Distribution Bucket of Points buckets # students students (%) ~ % 5 ~.% ~ 5.% 5 ~ 2.% 2 ~ 25.% 25 ~ 3.66% 3 ~ 35.% 35 ~ 4.% 4 ~ 45.% 45 ~ 5.66% 5 ~ % 55 ~ 6.% 6 ~ % 65 ~ % 7 ~ % 75 ~ % 8 ~ % 85 ~ % 9 ~ % 95 ~ % Total students enrolled : 5 # Solutions received : 37 Max score :. Min score (w/o s) : 3. Mean score : 86.3 Median score : 89.

29 Where we are now What we covered thus far: Chap Logic representations SOP and POS K-maps HW#3 due, HW#4 assigned Midterm # next week on Th Where we are going: K-maps more examples Mux and Demux 29

30 Karnaugh map: 4-variable example F(,B,C,D) = m(,2,3,5,6,7,8,,,4,5) F = C B D C D B find the smallest number of the largest possible subcubes to cover the ON-set (fewer terms with fewer inputs per term) 3

31 Karnaugh maps: don t cares f(,b,c,d) = m(,3,5,7,9) + d(6,2,3) without don't cares with don t cares f = f = X X C X B X D C X B X D don't cares can be treated as s or s depending on which is more advantageous 3

32 nother Example F = m(, 2, 7, 8, 4, 5) + d(3, 6, 9, 2, 3) X X X D C X X B 32

33 Design example: two-bit comparator N N2 B C D LT EQ GT block diagram and truth table B < C D B = C D B > C D B C D LT EQ GT we'll need a 4-variable Karnaugh map for each of the 3 output functions 33

34 Design example: two-bit comparator (cont d) D D D C B C B C B K-map for LT K-map for EQ K-map for GT LT = EQ = GT = ' B' D + ' C + B' C D ' B' C' D' + ' B C' D + B C D + B' C D = ( xnor C) (B xnor D) B C' D' + C' + B D' LT and GT are similar (flip /C and B/D) 34

35 Design example: 2x2-bit multiplier 2 B B2 block diagram and truth table P P2 P4 P8 2 B2 B P8 P4 P2 P 4-variable K-map for each of the 4 output functions 35

36 Design example: 2x2-bit multiplier (cont d) 2 K-map for P8 K-map for P4 2 B B B2 B2 2 K-map for P2 K-map for P 2 B B B2 B2 36

37 Design example: BCD + I I2 I4 I8 block diagram and truth table O O2 O4 O8 I8 I4 I2 I O8 O4 O2 O X X X X X X X X X X X X X X X X X X X X X X X X 4-variable K-map for each of the 4 output functions 37

38 Design example: BCD + (cont d) I8 X O8 O4 I8 X X I X I I2 I4 X X X X I2 I4 X X X X I8 X O2 O I8 X X I X I I2 I4 X X X X I2 I4 X X X X 38

39 CSE4: Components and Design Techniques for Digital Systems Muxes and demuxes Tajana Simunic Rosing 39

40 Contention: X Contention: circuit tries to drive output to and ctual value somewhere in between Could be,, or in forbidden zone Might change with voltage, temperature, time, noise Often causes excessive power dissipation = B = Y = X Warnings: Contention usually indicates a bug. X is used for don t care and contention - look at the context to tell them apart

41 Transmission Gate: Mux/Tristate building block nmos pass s poorly pmos pass s poorly Transmission gate is a better switch passes both and well When EN =, the switch is ON: EN = and is connected to B When EN =, the switch is OFF: is not connected to B EN EN B

42 Floating: Z Floating, high impedance, open, high Z Floating output might be,, or somewhere in between voltmeter won t indicate whether a node is floating Tristate Buffer E Y E Y Z Z

43 shared bus Tristate Busses Floating nodes are used in tristate busses many different drivers, but only one is active at once processor en to bus from bus video en2 to bus from bus Ethernet en3 to bus from bus memory en4 to bus from bus

44 2: Multiplexer or Mux Selects between one of N inputs to connect to output log 2 N-bit select input control input Example: 2: Mux D D S Y Logic gates Tristates Pass gates Y D D S D S Y S D D Y S Y D D D S D Y = D S + D S D Y

45 2: mux: Z = 'I + I Multiplexers 4: mux: Z = 'B'I + 'BI + B'I 2 + BI 3 8: mux: Z = 'B'C'I + 'B'CI + 'BC'I 2 + 'BCI 3 + B'C'I 4 + B'CI 5 + BC'I 6 + BCI 7 In general: Z = 2 n -(m k I k ) k= in minterm shorthand form for a 2 n : Mux I I 2: mux Z I I I2 I3 4: mux B Z I I I2 I3 I4 I5 I6 I7 8: mux B C Z 45

46 Logic using Multiplexers Using the mux as a lookup table B Y Y = B B Y

47 Logic using Multiplexers Reducing the size of the mux Y = B B Y Y B B Y

48 Mux example: Logical function unit C C C2 Function Comments always + B logical OR ( B)' logical NND xor B logical xor xnor B logical xnor B logical ND ( + B)' logical NOR always 2 3 8: MUX S2 S S F C C C2 48

49 Mux as general-purpose logic 2 n- : multiplexer can implement any function of n variables with n- variables used as control inputs and the data inputs tied to the last variable or its complement Example: F(,B,C) = C + BC' + 'B C 49

50 Demux or Decoder N inputs, 2 N outputs One-hot outputs: only one output HIGH at once 2:4 Decoder Y 3 Y 2 Y Y Y 3 Y 2 Y Y

51 Decoder: logic equations Decoders/demultiplexers control inputs (called selects (S)) represent binary index of output to which the input is connected data input usually called enable (G) :2 Decoder: O = G S O = G S 2:4 Decoder: O = G S S O = G S S O2 = G S S O3 = G S S 3:8 Decoder: O = G S2 S S O = G S2 S S O2 = G S2 S S O3 = G S2 S S O4 = G S2 S S O5 = G S2 S S O6 = G S2 S S O7 = G S2 S S 5

52 Decoder Implementation Y 3 Y 2 Y Y

53 Logic Using Decoders OR minterms B 2:4 Decoder Minterm B B B B 2 3 3:8 DEC S2 S S 'B'C' 'B'C 'BC' 'BC B'C' B'C BC' BC Y = B + B = B Y B C

54 Example of demux as general-purpose logic F = 'BC'D + 'B'CD + BCD F2 = BC'D' + BC F3 = (' + B' + C' + D') Enable 4:6 DEC 'B'C'D' 'B'C'D 2 'B'CD' 3 'B'CD 4 'BC'D' 5 'BC'D 6 'BCD' 7 'BCD 8 B'C'D' 9 B'C'D B'CD' B'CD 2 BC'D' 3 BC'D 4 BCD' 5 BCD B C D

55 F(,B,C) = M(,2,4) nother example 55

56 CSE4: Components and Design Techniques for Digital Systems Timing and hazards Tajana Simunic Rosing 56

57 Timing Delay between input change and output changing How to build fast circuits? Y delay Y Time

58 Propagation & Contamination Delay Propagation delay: t pd = max delay from input to output Contamination delay: t cd = min delay from input to output Y t pd Y t cd Time

59 Propagation & Contamination Delay Delay is caused by Capacitance and resistance in a circuit Speed of light limitation Reasons why t pd and t cd may be different: Different rising and falling delays Multiple inputs and outputs, some of which are faster than others Circuits slow down when hot and speed up when cold

60 Critical (Long) & Short Paths Critical (Long) Path: t pd = 2t pd_nd + t pd_or Short Path: t cd = t cd_nd Critical Path B C D n Short Path n2 Y

61 Glitches or Hazards Glitch occurs when an input change causes multiple output changes; circuit with a potential for a glitch has a hazard There are 3 types of hazards: Static- : output should be but has a glitch Static- : output should be but has a glitch Dynamic: transition -> or -> with a glitch Example: = B = C = Short Path B n2 n n2 Critical Path Y = B C Y C B What happens if =, C =, & B falls? Y n Y = B + BC Y glitch Time

62 Fixing a hazard Y C B C Y = B + BC + C = B = Y = C =

63 nother example F(,B,C,D)= m(,3,5,7,8,9,2,3) Test two single bit input transitions: -> -> C D C B Z D 63

64 CSE4: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing 64

65 Multiple-Output Circuits: Priority Circuit Output asserted corresponds to the most significant TRUE input 3 2 Y 3 Y 2 Y Y X PRIORITY CiIRCUIT Y 3 Y 2 Y Y X X X Y 3 Y 2 Y Y X X 3 2 Y 3 Y 2 Y Y

66 Multiple-Output Circuits Many circuits have more than one output Can give each a separate circuit, or can share gates Ex: F = ab + c, G = ab + bc Option : Separate circuits Option 2: Shared gates 66

67 Multi-level logic x = D F + E F + B D F + B E F + C D F + C E F + G reduced sum-of-products form already simplified 6 x 3-input ND gates + x 7-input OR gate (that may not even exist!) 25 wires (9 literals plus 6 internal wires) x = ( + B + C) (D + E) F + G factored form not written as two-level S-o-P x 3-input OR gate, 2 x 2-input OR gates, x 3-input ND gate wires (7 literals plus 3 internal wires) B C X D E F G

68 Multiple-Output Example: BCD to 7-Segment Converter a f b g e c d abcdefg = (a) a = w x y z + w x yz + w x yz + w xy z + w xyz + w xyz + wx y z + wx y z b = w x y z + w x y z + w x yz + w x yz + w xy z + w xyz + wx y z + wx y z (b) 68