INSTITUTE OF BUSINESS ADMINISTRATION, KARACHI Digital Logic Design (CSE-241) Laboratory Manual LAB # 16 Asynchronous Counters

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1 INSTITUTE OF BUSINESS ADMINISTRATION, KARACHI Digital Logic Design (CSE-241) Laboratory Manual LAB # 16 Asynchronous Counters Objective: The aim of this experiment is to understand the working of Asynchronous Counters using Flip-Flops Equipment: 1. One- Single Polarity Variable DC Power Supply 2. Digital Oscilloscope 3. Digital Function Generator 4. Logic Probe Components: 1. One-74LS76 JK-Flip-Flop 2. Switches 3. One- Bread Board Note: Do consult the data sheets before connecting you ICs THEORY: COUNTERS: Flip-flops can be connected together to perform counting. Such a group of flip-flops is known as a counter. Counters are mainly used in counting applications, where they either measure the time interval between two unknown time instants or measure the frequency of a given signal. Counters are classified into two broad categories according to the way they are clocked, asynchronous and synchronous. ASYNCHRONOUS COUNTER OPERATION: An asynchronous counter or a serial counter, the clock input is applied only to the first flip-flop, also called the input flip-flop, in the cascaded arrangement. The clock input to any subsequent flip-flop comes from the output of its immediately preceding flip-flop. For instance, the output of the first flip- Faculty of Computer Science Page 1

2 flop acts as the clock input to the second flip-flop, the output of the second flip-flop feeds the clock input of the third flip-flop and so on. 2-Bit Asynchronous Binary Counter: A 2-bit counter connected for Asynchronous operation is shown in the figure below. Notice that the clock signal is applied to only the first flip-flop which is always the LSB. And the second flip-flop is clocked through the output of the first. FF0 changes state on the positive edge of the clock whereas FF1 changes state on the positive going transition of the Q o.due to the inherent propagation delay time through a flip-flop, a transition of input clock pulse and a transition of the Q o can never occur at the same time. This is the reason why the counter operation is asynchronous. Faculty of Computer Science Page 2

3 Note in the figure above that the 2-bit counter exhibits four different states (2 2 = 4). Also notice that the sequence of counter states represents a sequence of binary numbers. Since it goes through a binary sequence, the counter is a Binary counter. It actually counts Clock pulses up to three, and on fourth pulse it recycles to its original state (Q0 = Q1 = Low). The term Recycle refers to the transition from its final state back to its original state. 3-Bit Asynchronous Binary Counter: The basic operation is the same as that of the 2-bit counter just discussed. The only difference is that the 3-bit counter has eight states, due to its three flip-flops. Faculty of Computer Science Page 3

4 PROPOGATION DELAY: These counters are also known as ripple counters because the effect of input is first felt at FF0. This effect can t reach FF1 immediately because of the propagation delay through FF0. Then there is a propagation delay through FF1 before FF2 can be triggered. Thus the effect of input clock pulse ripples through the counter. Faculty of Computer Science Page 4

5 This property of the ripple counters also bring our attention to the point that the greater the number of flip-flops used in the counter the greater will be the delay from first stage to the last. This cumulative delay of an asynchronous counter is a major disadvantage in many applications because it limits the rate at which the counter can be clocked and creates decoding problems. The maximum cumulative delay in a counter must be less that the period of the clock waveform. 4-bit Asynchronous Counter: Faculty of Computer Science Page 5

6 MODULUS OF A COUNTER: The modulus of a counter is the number of unique states that the counter will sequence through. The maximum possible number of states (maximum modulus) of a counter is 2 n. Where n is the number of flip-flops in the counter. TRUNCATED SEQUENCES: Counters can also be designed that have a number of states in their sequence that is less than the maximum of 2 n.the resulting sequence is called a truncated sequence. Faculty of Computer Science Page 6

7 ASYNCHRONOUS DECADE COUNTER: To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all of its possible states. For example, the BCD decade counter must recycle back to the 0000 state after the 1001 state. One way to make the counter recycle after the count of nine (1001) is to decode count ten (1010) with a NAND gate and connect the output the clear (CLR) input. PARTIAL DECODING: Notice in the figure that only Q1 and Q3 are connected to the NAND gate inputs. This arrangement is an example of partial decoding; in which the two unique states (Q1 = 1 and Q3 =1 ) are sufficient to decode the count of ten because none of the other states (zero through nine) have both Q1 and Q3 HIGH at the same time. When the counter goes into count ten (1010), the decoding gate output goes LOW and asynchronously resets the flip-flops. Faculty of Computer Science Page 7

8 Task 1: Construct a 2-bit Asynchronous counter (not on MultiSim) using the figure given below. o Verify the correct operation using oscilloscope. VCC 5V XSC1 U2 100 Hz 2 U1A 7 U1B 4 1J 1Q CLK 1K ~1PR ~1Q J 2Q CLK 2K ~2PR ~2Q 10 + A _ B + _ Ext Trig + _ ~1CLR 3 ~2CLR 8 Faculty of Computer Science Page 8

9 Task 2: Construct a 3-bit Asynchronous counter (in MultiSim). Use the logic analyzer provided in MultiSim to observe all the outputs simultaneously, and verify corrext operation. VCC 5V 1 XLA1 2 U1A 7 U1B ~1PR ~2PR 2 ~1PR U3A U2 100 Hz 4 1J 1Q CLK 1K ~1CLR 3 ~1Q J 2Q CLK 2K ~2CLR 8 ~2Q J 1Q CLK 1K ~1CLR 3 ~1Q 14 F C Q T Task 3: Construct a decade counter using the figure given in the theory section. Again use logic analyzer to observe all the outputs simultaneously. Faculty of Computer Science Page 9