Arithmetic Logic Unit (ALU) Storage Elements. Today s Lecture

Size: px
Start display at page:

Download "Arithmetic Logic Unit (ALU) Storage Elements. Today s Lecture"

Transcription

1 Arithmetic Logic Unit (ALU) Storge Elements Computer Science 4 Tody s Lecture Homework #4 coming soon Building the uilding locks Outline Review igitl uilding locks An Arithmetic Logic Unit (ALU) Storge Elements Register File Reding Chpter 4.2 strt reding 4. & 4.3 2

2 Review: Boolen Functions nd Expressions F(A, B, C) = (A * B) + (~A * C) A B C F 3 Review: Boolen Gtes Gtes re electronics devices tht implement simple Boolen functions Exmples AN(,) OR(,) NOT() XOR(,) NAN(,) NOR(,) XNOR(,) 4

3 Review: Boolen Functions, Gtes nd Circuits Circuits re mde from network of gtes. (function compositions). XOR(,) F = ~* + ~* XOR(,) F 5 Circuit Exmple: ecoder I I 2 3 6

4 Circuit Exmple: 2x MUX Multiplexor (MUX) selects one of mny inputs y MUX(A, B, S) = (A * S) + (B * ~S) s B Gte Gte 3 Y = (A * S) + (B * ~S) A Gte 2 S 7 Exmple 4x MUX 3 c d y c d 2 y 2 s s S 8

5 Arithmetic nd Logicl Opertions in ISA Wht opertions re there? Arithmetic Logic Unit (ALU) Hrdwre tht performs opertions Only one opertion t time How do we implement the opertions? Consider AN, OR, NOT, nd A Input is two its, output 9 Truth Tle for -it Addition + C in Sum C out Wht is the circuit for Sum nd for Cout?

6 A -it Full Adder Cin Sum + Cout C in Sum C out Exmple: 4-it dder S3 S2 S S C out Full Adder Full Adder Full Adder Full Adder C in This is clled Ripple Crry Adder: There re fster, more complex dder circuits. 2

7 ALU Slice (Almost) C in 3 2 F + NOT 2 OR 3 AN Adder 2 C ou t F 3 Sutrction How do we perform integer sutrction? Wht is the hrdwre (circuit)? 4

8 ALU Slice C in 3 2 A F NOT - 2 OR - 3 AN ~Add/Su Adder 2 C ou t F 5 Exmple: 2 (= 53 ) + 2 (= 42 ) 2 (=-33 ) Overflow Exmple2: 2 (=-43 ) + 2 (=-54 ) 2 (= 3 ) Exmple3: 2 (= 53 ) + 2 (=-22 ) 2 (= 3 ) Exmple4: 2 (= 2 ) + 2 (= 42 ) 2 (= 63 ) 6

9 Overflow etection for 4-it dder OVERFLOW S3 S2 S S C out Full Adder Full Adder Full Adder Full Adder C in The ALU Overflow = Zero n- n-2 ALU Slice ALU Slice ALU Slice ALU Slice ALU control n- n- n-2 n-2 8

10 Astrction: The ALU Generl structure Two opernd inputs Control inputs ALU Opertion Input A Zero ALU Result We cn uild circuits for Multipliction ivision They re more complex Input B Crry Out Overflow 9 The Shift Opertion Consider n 8-it mchine How do I implement the shift opertion? 2

11 Shifter 2 Summry thus fr Given Boolen function, generte circuit tht relizes the function. Constructed circuits tht cn dd nd sutrct. The ALU: circuit tht cn dd, sutrct, detect overflow, compre, nd do it-wise opertions (AN, OR, NOT) Shifter Next up: Storge Elements: Registers, Ltches, Buses 22

12 Memory Elements All the circuits we looked t so fr re comintionl circuits: the output is Boolen function of the inputs. We need circuits tht cn rememer vlues. (registers) The output of the circuit is function of the input AN function of stored vlue (stte). Circuits with memory re clled sequentil circuits. 23 Set-Reset Ltch R R S S R S - on t set oth S & R to 24

13 Set-Reset Ltch (Continued) R R S S Time S R 25 t Ltch ( Ltch) E nle t E - Time oes not ffect Output E 26

14 Flip-Flop C ltch E ltch E On C is trnsferred to the first ltch nd the second is stle. On C the output of the first stge is trnsferred to the second (output), nd the first stge is stle. Output chnges only on the edge of clock 27 Register File Register File = the set of loctions for register vlues E.g., it registers How do I uild Register File using Flip-Flops? Wht other components do I need? 28

15 Register File Circuit to determine which of 32 registers? Circuit to get just the dt from one of 32 registers? 29 Tri-Stte river The Tri-Stte driver is like (one directionl) switch: When the Enle is on (E=) it trnsfers the input to the output. When the Enle is off (E=) it disconnects the output. E E - Z E Z :- High Impednce 3

16 Bus Connections The Bus: Mny to mny connections. Mutul exclusion: At most one Enle is on! Control must ensure this! Note: Bus sometimes used to denote multiple prllel wires 3 Register Cells on us IE E ltch OE IE E ltch OE IE E ltch OE IE E ltch OE One cn source nd sink from ny cell on the us y ctivting the right controls, IE--input enle, nd OE--output enle. 32

17 t-in 3-Port Register Cell Bus-C Bus-B Complement Bus-A in E nle OutA OutB Stores one it of register Cn Red onto Bus-A & Bus-B nd Write from Bus-C Simultneously 33 3-Port Register File EC EA EB Bus-C Bus-B Bit- Bus-A Bus-C Bus-B Bit- Bus-A 34

18 Address ecode Circuit t-in Bus-C Bus-B Register ddress: E nle OutA Bus-A OutB A A EA B B EB C C EC 35 Register File (Four 4-it Registers) Reg-3 Reg-2 Reg- Reg- A3 B3 C3 A2 B2 C2 A B C A B C A-En Add-A Add-A B -En Add-B Add-B C -En Add-C Add-C 36

19 igitl Logic Summry Given Boolen function, generte circuit to relize the function. Constructed circuits tht cn dd nd sutrct. The ALU: circuit tht cn dd, sutrct, detect overflow, compre, nd do it-wise opertions (AN, OR, NOT) Shifter Memory Elements: SR-Ltch, Ltch, Flip-Flop Tri-stte drivers & Bus Communiction vs. MUX Register Files Control Signls modify wht circuit does with inputs ALU, Shift, Register Red/Write 37 The ALU & Shifter Summry Storge elements S-R ltch, -Ltch, Flip-Flop Register File Next time Finite stte mchines HCL 38

Register File, Finite State Machines & Hardware Control Language

Register File, Finite State Machines & Hardware Control Language Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework

More information

Understanding Logic Design

Understanding Logic Design Understanding Logic Design ppendix of your Textbook does not have the needed background information. This document supplements it. When you write add DD R0, R1, R2, you imagine something like this: R1

More information

CS99S Laboratory 2 Preparation Copyright W. J. Dally 2001 October 1, 2001

CS99S Laboratory 2 Preparation Copyright W. J. Dally 2001 October 1, 2001 CS99S Lortory 2 Preprtion Copyright W. J. Dlly 2 Octoer, 2 Ojectives:. Understnd the principle of sttic CMOS gte circuits 2. Build simple logic gtes from MOS trnsistors 3. Evlute these gtes to oserve logic

More information

Two hours UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE. Date: Friday 16 th May 2008. Time: 14:00 16:00

Two hours UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE. Date: Friday 16 th May 2008. Time: 14:00 16:00 COMP20212 Two hours UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE Digitl Design Techniques Dte: Fridy 16 th My 2008 Time: 14:00 16:00 Plese nswer ny THREE Questions from the FOUR questions provided

More information

Learning Outcomes. Computer Systems - Architecture Lecture 4 - Boolean Logic. What is Logic? Boolean Logic 10/28/2010

Learning Outcomes. Computer Systems - Architecture Lecture 4 - Boolean Logic. What is Logic? Boolean Logic 10/28/2010 /28/2 Lerning Outcomes At the end of this lecture you should: Computer Systems - Architecture Lecture 4 - Boolen Logic Eddie Edwrds eedwrds@doc.ic.c.uk http://www.doc.ic.c.uk/~eedwrds/compsys (Hevily sed

More information

Let s put together a Manual Processor

Let s put together a Manual Processor Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce

More information

Binary Adders: Half Adders and Full Adders

Binary Adders: Half Adders and Full Adders Binary Adders: Half Adders and Full Adders In this set of slides, we present the two basic types of adders: 1. Half adders, and 2. Full adders. Each type of adder functions to add two binary bits. In order

More information

Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language

Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,

More information

5 Combinatorial Components. 5.0 Full adder. Full subtractor

5 Combinatorial Components. 5.0 Full adder. Full subtractor 5 Combatorial Components Use for data transformation, manipulation, terconnection, and for control: arithmetic operations - addition, subtraction, multiplication and division. logic operations - AND, OR,

More information

One Minute To Learn Programming: Finite Automata

One Minute To Learn Programming: Finite Automata Gret Theoreticl Ides In Computer Science Steven Rudich CS 15-251 Spring 2005 Lecture 9 Fe 8 2005 Crnegie Mellon University One Minute To Lern Progrmming: Finite Automt Let me tech you progrmming lnguge

More information

ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path

ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data

More information

Binary Representation of Numbers Autar Kaw

Binary Representation of Numbers Autar Kaw Binry Representtion of Numbers Autr Kw After reding this chpter, you should be ble to: 1. convert bse- rel number to its binry representtion,. convert binry number to n equivlent bse- number. In everydy

More information

Engineer-to-Engineer Note

Engineer-to-Engineer Note Engineer-to-Engineer Note EE-265 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our

More information

ASYNCHRONOUS COUNTERS

ASYNCHRONOUS COUNTERS LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

More information

DEPARTMENT OF INFORMATION TECHNLOGY

DEPARTMENT OF INFORMATION TECHNLOGY DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453

More information

Rotating DC Motors Part II

Rotating DC Motors Part II Rotting Motors rt II II.1 Motor Equivlent Circuit The next step in our consiertion of motors is to evelop n equivlent circuit which cn be use to better unerstn motor opertion. The rmtures in rel motors

More information

CSE140 Homework #7 - Solution

CSE140 Homework #7 - Solution CSE140 Spring2013 CSE140 Homework #7 - Solution You must SHOW ALL STEPS for obtaining the solution. Reporting the correct answer, without showing the work performed at each step will result in getting

More information

Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

More information

earlier in the semester: The Full adder above adds two bits and the output is at the end. So if we do this eight times, we would have an 8-bit adder.

earlier in the semester: The Full adder above adds two bits and the output is at the end. So if we do this eight times, we would have an 8-bit adder. The circuit created is an 8-bit adder. The 8-bit adder adds two 8-bit binary inputs and the result is produced in the output. In order to create a Full 8-bit adder, I could use eight Full -bit adders and

More information

2 DIODE CLIPPING and CLAMPING CIRCUITS

2 DIODE CLIPPING and CLAMPING CIRCUITS 2 DIODE CLIPPING nd CLAMPING CIRCUITS 2.1 Ojectives Understnding the operting principle of diode clipping circuit Understnding the operting principle of clmping circuit Understnding the wveform chnge of

More information

Figure 8-1 Four Possible Results of Adding Two Bits

Figure 8-1 Four Possible Results of Adding Two Bits CHPTER EIGHT Combinational Logic pplications Thus far, our discussion has focused on the theoretical design issues of computer systems. We have not yet addressed any of the actual hardware you might find

More information

NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.

NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell. CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache

More information

Sistemas Digitais I LESI - 2º ano

Sistemas Digitais I LESI - 2º ano Sistemas Digitais I LESI - 2º ano Lesson 6 - Combinational Design Practices Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA - PLDs (1) - The

More information

Section 5.2, Commands for Configuring ISDN Protocols. Section 5.3, Configuring ISDN Signaling. Section 5.4, Configuring ISDN LAPD and Call Control

Section 5.2, Commands for Configuring ISDN Protocols. Section 5.3, Configuring ISDN Signaling. Section 5.4, Configuring ISDN LAPD and Call Control Chpter 5 Configurtion of ISDN Protocols This chpter provides instructions for configuring the ISDN protocols in the SP201 for signling conversion. Use the sections tht reflect the softwre you re configuring.

More information

Lectures 8 and 9 1 Rectangular waveguides

Lectures 8 and 9 1 Rectangular waveguides 1 Lectures 8 nd 9 1 Rectngulr wveguides y b x z Consider rectngulr wveguide with 0 < x b. There re two types of wves in hollow wveguide with only one conductor; Trnsverse electric wves

More information

Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

More information

Computer organization

Computer organization Computer organization Computer design an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine inputs

More information

FAULT TREES AND RELIABILITY BLOCK DIAGRAMS. Harry G. Kwatny. Department of Mechanical Engineering & Mechanics Drexel University

FAULT TREES AND RELIABILITY BLOCK DIAGRAMS. Harry G. Kwatny. Department of Mechanical Engineering & Mechanics Drexel University SYSTEM FAULT AND Hrry G. Kwtny Deprtment of Mechnicl Engineering & Mechnics Drexel University OUTLINE SYSTEM RBD Definition RBDs nd Fult Trees System Structure Structure Functions Pths nd Cutsets Reliility

More information

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous

More information

Lec 2: Gates and Logic

Lec 2: Gates and Logic Lec 2: Gtes nd Logic Kvit Bl CS 34, Fll 28 Computer Science Cornell University Announcements Clss newsgroup creted Posted on we-pge Use it for prtner finding First ssignment is to find prtners Due this

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: Computer Organization and Architecture Lecture 9 - Register Transfer and Microoperations Microoperations Digital systems are modular in nature, with modules containing registers, decoders, arithmetic

More information

OUTLINE SYSTEM-ON-CHIP DESIGN. GETTING STARTED WITH VHDL August 31, 2015 GAJSKI S Y-CHART (1983) TOP-DOWN DESIGN (1)

OUTLINE SYSTEM-ON-CHIP DESIGN. GETTING STARTED WITH VHDL August 31, 2015 GAJSKI S Y-CHART (1983) TOP-DOWN DESIGN (1) August 31, 2015 GETTING STARTED WITH VHDL 2 Top-down design VHDL history Min elements of VHDL Entities nd rhitetures Signls nd proesses Dt types Configurtions Simultor sis The testenh onept OUTLINE 3 GAJSKI

More information

Virtual Machine. Part II: Program Control. Building a Modern Computer From First Principles. www.nand2tetris.org

Virtual Machine. Part II: Program Control. Building a Modern Computer From First Principles. www.nand2tetris.org Virtul Mchine Prt II: Progrm Control Building Modern Computer From First Principles www.nnd2tetris.org Elements of Computing Systems, Nisn & Schocken, MIT Press, www.nnd2tetris.org, Chpter 8: Virtul Mchine,

More information

Example 27.1 Draw a Venn diagram to show the relationship between counting numbers, whole numbers, integers, and rational numbers.

Example 27.1 Draw a Venn diagram to show the relationship between counting numbers, whole numbers, integers, and rational numbers. 2 Rtionl Numbers Integers such s 5 were importnt when solving the eqution x+5 = 0. In similr wy, frctions re importnt for solving equtions like 2x = 1. Wht bout equtions like 2x + 1 = 0? Equtions of this

More information

Binary full adder. 2-bit ripple-carry adder. CSE 370 Spring 2006 Introduction to Digital Design Lecture 12: Adders

Binary full adder. 2-bit ripple-carry adder. CSE 370 Spring 2006 Introduction to Digital Design Lecture 12: Adders SE 370 Spring 2006 Introduction to Digital Design Lecture 12: dders Last Lecture Ls and Ls Today dders inary full 1-bit full omputes sum, carry-out arry-in allows cascaded s = xor xor = + + 32 ND2 11 ND2

More information

A.7.1 Trigonometric interpretation of dot product... 324. A.7.2 Geometric interpretation of dot product... 324

A.7.1 Trigonometric interpretation of dot product... 324. A.7.2 Geometric interpretation of dot product... 324 A P P E N D I X A Vectors CONTENTS A.1 Scling vector................................................ 321 A.2 Unit or Direction vectors...................................... 321 A.3 Vector ddition.................................................

More information

CS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on

CS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on CS 61C: Great Ideas in Computer Architecture Finite State Machines Instructors: Krste Asanovic & Vladimir Stojanovic hbp://inst.eecs.berkeley.edu/~cs61c/sp15 1 Levels of RepresentaKon/ InterpretaKon High

More information

Physics 43 Homework Set 9 Chapter 40 Key

Physics 43 Homework Set 9 Chapter 40 Key Physics 43 Homework Set 9 Chpter 4 Key. The wve function for n electron tht is confined to x nm is. Find the normliztion constnt. b. Wht is the probbility of finding the electron in. nm-wide region t x

More information

(1) /30 (2) /30 (3) /40 TOTAL /100

(1) /30 (2) /30 (3) /40 TOTAL /100 Your Name: SI Number: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY AVIS IRVINE LOS ANGELES RIVERSIE SAN IEGO SAN FRANCISCO epartment of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA

More information

16-bit ALU, Register File and Memory Write Interface

16-bit ALU, Register File and Memory Write Interface CS M152B Fall 2002 Project 2 16-bit ALU, Register File and Memory Write Interface Suggested Due Date: Monday, October 21, 2002 Actual Due Date determined by your Lab TA This project will take much longer

More information

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction

More information

ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog

ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();

More information

Or more simply put, when adding or subtracting quantities, their uncertainties add.

Or more simply put, when adding or subtracting quantities, their uncertainties add. Propgtion of Uncertint through Mthemticl Opertions Since the untit of interest in n eperiment is rrel otined mesuring tht untit directl, we must understnd how error propgtes when mthemticl opertions re

More information

LECTURE #05. Learning Objective. To describe the geometry in and around a unit cell in terms of directions and planes.

LECTURE #05. Learning Objective. To describe the geometry in and around a unit cell in terms of directions and planes. LECTURE #05 Chpter 3: Lttice Positions, Directions nd Plnes Lerning Objective To describe the geometr in nd round unit cell in terms of directions nd plnes. 1 Relevnt Reding for this Lecture... Pges 64-83.

More information

CHAPTER 3 Boolean Algebra and Digital Logic

CHAPTER 3 Boolean Algebra and Digital Logic CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4

More information

Example A rectangular box without lid is to be made from a square cardboard of sides 18 cm by cutting equal squares from each corner and then folding

Example A rectangular box without lid is to be made from a square cardboard of sides 18 cm by cutting equal squares from each corner and then folding 1 Exmple A rectngulr box without lid is to be mde from squre crdbord of sides 18 cm by cutting equl squres from ech corner nd then folding up the sides. 1 Exmple A rectngulr box without lid is to be mde

More information

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits

More information

SELECT INPUTS STROBE OUTPUTS

SELECT INPUTS STROBE OUTPUTS 1 9. 1. I SN74153. 4x1 U1 74153 2 21 22 23 1. SN74153 ( ), ogic Is-MUs MUX. SEET DT INPUTS STROE OUTPUT INPUTS 1 2 3 G Y X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1. SN74153. : SEET INPUTS

More information

Lesson 12 Sequential Circuits: Flip-Flops

Lesson 12 Sequential Circuits: Flip-Flops Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability

More information

ECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)

ECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process) ECE 3401 Lecture 7 Concurrent Statements & Sequential Statements (Process) Concurrent Statements VHDL provides four different types of concurrent statements namely: Signal Assignment Statement Simple Assignment

More information

License Manager Installation and Setup

License Manager Installation and Setup The Network License (concurrent-user) version of e-dpp hs hrdwre key plugged to the computer running the License Mnger softwre. In the e-dpp terminology, this computer is clled the License Mnger Server.

More information

Regular Sets and Expressions

Regular Sets and Expressions Regulr Sets nd Expressions Finite utomt re importnt in science, mthemtics, nd engineering. Engineers like them ecuse they re super models for circuits (And, since the dvent of VLSI systems sometimes finite

More information

List of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC-7447).

List of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC-7447). G. H. RAISONI COLLEGE OF ENGINEERING, NAGPUR Department of Electronics & Communication Engineering Branch:-4 th Semester[Electronics] Subject: - Digital Circuits List of Experiment Sr. Name Of Experiment

More information

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one

More information

Use Geometry Expressions to create a more complex locus of points. Find evidence for equivalence using Geometry Expressions.

Use Geometry Expressions to create a more complex locus of points. Find evidence for equivalence using Geometry Expressions. Lerning Objectives Loci nd Conics Lesson 3: The Ellipse Level: Preclculus Time required: 120 minutes In this lesson, students will generlize their knowledge of the circle to the ellipse. The prmetric nd

More information

(Refer Slide Time: 00:01:16 min)

(Refer Slide Time: 00:01:16 min) Digital Computer Organization Prof. P. K. Biswas Department of Electronic & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Lecture No. # 04 CPU Design: Tirning & Control

More information

5 a LAN 6 a gateway 7 a modem

5 a LAN 6 a gateway 7 a modem STARTER With the help of this digrm, try to descrie the function of these components of typicl network system: 1 file server 2 ridge 3 router 4 ckone 5 LAN 6 gtewy 7 modem Another Novell LAN Router Internet

More information

BINARY CODED DECIMAL: B.C.D.

BINARY CODED DECIMAL: B.C.D. BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.

More information

Small Business Networking

Small Business Networking Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd processes. Introducing technology

More information

How To Network A Smll Business

How To Network A Smll Business Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd processes. Introducing technology

More information

More Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset.

More Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset. More Verilog 8-bit Register with Synchronous Reset module reg8 (reset, CLK, D, Q); input reset; input [7:0] D; output [7:0] Q; reg [7:0] Q; if (reset) Q = 0; else Q = D; module // reg8 Verilog - 1 Verilog

More information

Chapter. Contents: A Constructing decimal numbers

Chapter. Contents: A Constructing decimal numbers Chpter 9 Deimls Contents: A Construting deiml numers B Representing deiml numers C Deiml urreny D Using numer line E Ordering deimls F Rounding deiml numers G Converting deimls to frtions H Converting

More information

Mathematics. Vectors. hsn.uk.net. Higher. Contents. Vectors 128 HSN23100

Mathematics. Vectors. hsn.uk.net. Higher. Contents. Vectors 128 HSN23100 hsn.uk.net Higher Mthemtics UNIT 3 OUTCOME 1 Vectors Contents Vectors 18 1 Vectors nd Sclrs 18 Components 18 3 Mgnitude 130 4 Equl Vectors 131 5 Addition nd Subtrction of Vectors 13 6 Multipliction by

More information

Homework 3 Solutions

Homework 3 Solutions CS 341: Foundtions of Computer Science II Prof. Mrvin Nkym Homework 3 Solutions 1. Give NFAs with the specified numer of sttes recognizing ech of the following lnguges. In ll cses, the lphet is Σ = {,1}.

More information

Small Business Networking

Small Business Networking Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd business. Introducing technology

More information

CHAPTER 11: Flip Flops

CHAPTER 11: Flip Flops CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach

More information

VMware Horizon Mirage Web Manager Guide

VMware Horizon Mirage Web Manager Guide VMwre Horizon Mirge We Mnger Guide Horizon Mirge 4.3 This document supports the version of ech product listed nd supports ll susequent versions until the document is replced y new edition. To check for

More information

CS101 Lecture 26: Low Level Programming. John Magee 30 July 2013 Some material copyright Jones and Bartlett. Overview/Questions

CS101 Lecture 26: Low Level Programming. John Magee 30 July 2013 Some material copyright Jones and Bartlett. Overview/Questions CS101 Lecture 26: Low Level Programming John Magee 30 July 2013 Some material copyright Jones and Bartlett 1 Overview/Questions What did we do last time? How can we control the computer s circuits? How

More information

and thus, they are similar. If k = 3 then the Jordan form of both matrices is

and thus, they are similar. If k = 3 then the Jordan form of both matrices is Homework ssignment 11 Section 7. pp. 249-25 Exercise 1. Let N 1 nd N 2 be nilpotent mtrices over the field F. Prove tht N 1 nd N 2 re similr if nd only if they hve the sme miniml polynomil. Solution: If

More information

PROF. BOYAN KOSTADINOV NEW YORK CITY COLLEGE OF TECHNOLOGY, CUNY

PROF. BOYAN KOSTADINOV NEW YORK CITY COLLEGE OF TECHNOLOGY, CUNY MAT 0630 INTERNET RESOURCES, REVIEW OF CONCEPTS AND COMMON MISTAKES PROF. BOYAN KOSTADINOV NEW YORK CITY COLLEGE OF TECHNOLOGY, CUNY Contents 1. ACT Compss Prctice Tests 1 2. Common Mistkes 2 3. Distributive

More information

Multiplication and Division - Left to Right. Addition and Subtraction - Left to Right.

Multiplication and Division - Left to Right. Addition and Subtraction - Left to Right. Order of Opertions r of Opertions Alger P lese Prenthesis - Do ll grouped opertions first. E cuse Eponents - Second M D er Multipliction nd Division - Left to Right. A unt S hniqu Addition nd Sutrction

More information

Small Business Networking

Small Business Networking Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd business. Introducing technology

More information

Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas

Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas Take-Home Exercise Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count

More information

APPLICATION NOTE Revision 3.0 MTD/PS-0534 August 13, 2008 KODAK IMAGE SENDORS COLOR CORRECTION FOR IMAGE SENSORS

APPLICATION NOTE Revision 3.0 MTD/PS-0534 August 13, 2008 KODAK IMAGE SENDORS COLOR CORRECTION FOR IMAGE SENSORS APPLICATION NOTE Revision 3.0 MTD/PS-0534 August 13, 2008 KODAK IMAGE SENDORS COLOR CORRECTION FOR IMAGE SENSORS TABLE OF FIGURES Figure 1: Spectrl Response of CMOS Imge Sensor...3 Figure 2: Byer CFA Ptterns...4

More information

Counters and Decoders

Counters and Decoders Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

More information

Small Business Networking

Small Business Networking Why network is n essentil productivity tool for ny smll business Effective technology is essentil for smll businesses looking to increse the productivity of their people nd processes. Introducing technology

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED 2nd (Spring) term 22/23 5. LECTURE: REGISTERS. Storage registers 2. Shift

More information

United States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1

United States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1 United States Naval Academy Electrical and Computer Engineering Department EC262 Exam 29 September 2. Do a page check now. You should have pages (cover & questions). 2. Read all problems in their entirety.

More information

12. A B C A B C A B C 1 A B C A B C A B C JK-FF NETr

12. A B C A B C A B C 1 A B C A B C A B C JK-FF NETr 2..,.,.. Flip-Flops :, Flip-Flops, Flip Flop. ( MOD)... -8 8, 7 ( ).. n Flip-Flops. n Flip-Flops : 2 n. 2 n, Modulo. (-5) -4 ( -), (-) - ( -).. / A A A 2 3 4 5 MOD-5 6 MOD-6 7 MOD-7 8 9 / A A A 2 3 4 5

More information

Gates, Plexers, Decoders, Registers, Addition and Comparison

Gates, Plexers, Decoders, Registers, Addition and Comparison Introduction to Digital Logic Autumn 2008 Gates, Plexers, Decoders, Registers, Addition and Comparison karl.marklund@it.uu.se ...open up a command shell and type logisim and press enter to start Logisim.

More information

Memory Elements. Combinational logic cannot remember

Memory Elements. Combinational logic cannot remember Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic

More information

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements

More information

Solenoid Operated Proportional Directional Control Valve (with Pressure Compensation, Multiple Valve Series)

Solenoid Operated Proportional Directional Control Valve (with Pressure Compensation, Multiple Valve Series) Solenoid Operted Proportionl Directionl Control Vlve (with Pressure Compenstion, Multiple Vlve Series) Hydrulic circuit (Exmple) v Fetures hese stcking type control vlves show pressure compensted type

More information

Vectors 2. 1. Recap of vectors

Vectors 2. 1. Recap of vectors Vectors 2. Recp of vectors Vectors re directed line segments - they cn be represented in component form or by direction nd mgnitude. We cn use trigonometry nd Pythgors theorem to switch between the forms

More information

Engineer-to-Engineer Note

Engineer-to-Engineer Note Engineer-to-Engineer Note EE-280 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors or e-mil

More information

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital

More information

, and the number of electrons is -19. e e 1.60 10 C. The negatively charged electrons move in the direction opposite to the conventional current flow.

, and the number of electrons is -19. e e 1.60 10 C. The negatively charged electrons move in the direction opposite to the conventional current flow. Prolem 1. f current of 80.0 ma exists in metl wire, how mny electrons flow pst given cross section of the wire in 10.0 min? Sketch the directions of the current nd the electrons motion. Solution: The chrge

More information

[ 4 ] Logic Symbols and Truth Table

[ 4 ] Logic Symbols and Truth Table [ 4 ] Logic s and Truth Table 1. How to Read MIL-Type Logic s Table 1.1 shows the MIL-type logic symbols used for high-speed CMO ICs. This logic chart is based on MIL-TD-806. The clocked inverter and transmission

More information

Lab 1: Full Adder 0.0

Lab 1: Full Adder 0.0 Lab 1: Full Adder 0.0 Introduction In this lab you will design a simple digital circuit called a full adder. You will then use logic gates to draw a schematic for the circuit. Finally, you will verify

More information

MA 15800 Lesson 16 Notes Summer 2016 Properties of Logarithms. Remember: A logarithm is an exponent! It behaves like an exponent!

MA 15800 Lesson 16 Notes Summer 2016 Properties of Logarithms. Remember: A logarithm is an exponent! It behaves like an exponent! MA 5800 Lesson 6 otes Summer 06 Rememer: A logrithm is n eponent! It ehves like n eponent! In the lst lesson, we discussed four properties of logrithms. ) log 0 ) log ) log log 4) This lesson covers more

More information

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

More information

Operations with Polynomials

Operations with Polynomials 38 Chpter P Prerequisites P.4 Opertions with Polynomils Wht you should lern: Write polynomils in stndrd form nd identify the leding coefficients nd degrees of polynomils Add nd subtrct polynomils Multiply

More information

Chapter 10 Computer Design Basics

Chapter 10 Computer Design Basics Logic ad Computer Desig Fudametals Chapter 10 Computer Desig Basics Part 1 Datapaths Charles Kime & Thomas Kamiski 2004 Pearso Educatio, Ic. Terms of Use (Hyperliks are active i View Show mode) Overview

More information

. At first sight a! b seems an unwieldy formula but use of the following mnemonic will possibly help. a 1 a 2 a 3 a 1 a 2

. At first sight a! b seems an unwieldy formula but use of the following mnemonic will possibly help. a 1 a 2 a 3 a 1 a 2 7 CHAPTER THREE. Cross Product Given two vectors = (,, nd = (,, in R, the cross product of nd written! is defined to e: " = (!,!,! Note! clled cross is VECTOR (unlike which is sclr. Exmple (,, " (4,5,6

More information

Binary Division. Decimal Division. Hardware for Binary Division. Simple 16-bit Divider Circuit

Binary Division. Decimal Division. Hardware for Binary Division. Simple 16-bit Divider Circuit Decimal Division Remember 4th grade long division? 43 // quotient 12 521 // divisor dividend -480 41-36 5 // remainder Shift divisor left (multiply by 10) until MSB lines up with dividend s Repeat until

More information

Bayesian Updating with Continuous Priors Class 13, 18.05, Spring 2014 Jeremy Orloff and Jonathan Bloom

Bayesian Updating with Continuous Priors Class 13, 18.05, Spring 2014 Jeremy Orloff and Jonathan Bloom Byesin Updting with Continuous Priors Clss 3, 8.05, Spring 04 Jeremy Orloff nd Jonthn Bloom Lerning Gols. Understnd prmeterized fmily of distriutions s representing continuous rnge of hypotheses for the

More information

Logic in Computer Science: Logic Gates

Logic in Computer Science: Logic Gates Logic in Computer Science: Logic Gates Lila Kari The University of Western Ontario Logic in Computer Science: Logic Gates CS2209, Applied Logic for Computer Science 1 / 49 Logic and bit operations Computers

More information