Two hours UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE. Date: Friday 16 th May Time: 14:00 16:00

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1 COMP20212 Two hours UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE Digitl Design Techniques Dte: Fridy 16 th My 2008 Time: 14:00 16:00 Plese nswer ny THREE Questions from the FOUR questions provided This is CLOSED ook exmintion The use of electronic clcultors is permitted provided they re not progrmmle nd do not store text. [PTO]

2 Pge 2 of 7 COMP ) Explin the effects of CMOS process scling on: i) Drin to source current. ii) Totl power consumption on chip. iii) Gte dely. You my ssume tht: I 2 Vgs Vt ds 0 2 t ox W L V gs V V t ds where the symols hve their usul significnce. (6 Mrks) ) A CMOS gte hs gte dely of 0.2ns nd is connected to n identicl gte y 5mm of 500 nm wide trck. The sheet resistnce of the trck is 0.06 Ohms/squre nd the trck cpcitnce is 0.1 ff/ m 2. The gte input cpcitnce is 25 ff. Clculte the rtio of the gte dely to the trck dely for the two gtes. If the process used to fricte the gtes is scled down y fctor of 5 ut the interconnect stys the sme length, clculte the increse in trck dely. Hence the new rtio of gte dely to trck dely. Comment on the implictions of this result for CMOS process scling. (8 Mrks) c) Descrie three wys in which performnce improvement hs een mde in modern CMOS processing which do not require dimensionl scling. (6 Mrks)

3 Pge 3 of 7 COMP ) Three different CMOS implementtions of the sme logic function re given in Figure 1. i) Wht is the logic function? ii) iii) iv) Which implementtion uses the lest silicon re? Which is the complex gte implementtion? Wht is the min disdvntge of the circuit shown in Figure 1 (i) nd how might it e overcome? (5 Mrks) Vdd q q i ii iii Vs q Figure 1 ) Drw stick digrm of the lyout for the implementtion shown in Figure 1 (iii) nd provide suitle key to the digrm. (9 Mrks) c) The CMOS NAND gtes in Figure 1 (ii) re constructed from n-chnnel devices with n effective chnnel resistnce of 5k Ohms nd p-chnnel devices with n effective chnnel resistnce of 7k Ohms. Both MOSFETS hve n input cpcitnce of 5 ff nd the gte hs n unloded output cpcitnce of 1 ff. Clculte the worst-cse output rise nd fll propgtion delys for the circuit stting ny ssumptions mde in your clcultion. (6 Mrks) [PTO]

4 Pge 4 of 7 COMP ) Using suitle digrm, discuss the control nd opertion of 2 n :1 multiplexer. Wht two primry functions cn multiplexer e used for? (3 mrks) ) If multiplexer hs 2 n dt inputs nd cn implement function of k vriles, wht is the mximum vlue of k, without the need for extr logic, if, i) The input vriles re only connected to the multiplexer select inputs? ii) The input vriles re connected to the multiplexer dt nd select inputs? (2 mrks) c) Multiplexers re often implemented using trnsmission gtes. Using suitle digrm discuss the opertion of trnsmission gte. Why is complementry rrngement of trnsistors dopted? Using the symol representtion of trnsmission gte, show how 2:1 multiplexer my e implemented using trnsmission gtes nd inverters. (6 mrks) d) Implement the following functions using 4:1 multiplexers, illustrte your implementtions. i) Z A.C B.C A.B.C, using A nd B s the dt select inputs ii) iii) The sum nd crry locks of full dder, with the Multiplexer dt inputs function of the crry in signl Z A.B.C.D A.C.D A.B.C+A.C.D+A.B.D using A nd B s the dt select inputs. (9 mrks)

5 Pge 5 of 7 COMP ) The ASM chrt illustrted in Figure 2 hs numer of errors. Identify the mistkes, stting why they re errors. If the ASM chrt were corrected, wht type of mchine would e implemented? (5 mrks) Figure 2 (Question 4 continues on the following pge)

6 Pge 6 of 7 COMP20212 (Question 4 continues from the previous pge) ) Discuss the disdvntge of the ripple crry dder illustrted in Figure 3. Sketch modified circuit tht will permit oth ddition nd sutrction of 2-s complement inry numers. How cn n overflow condition e detected? (6 mrks) Figure 3 c) Figure 4 illustrtes 4-it seril dder with ccumultor. Briefly descrie the opertion of this circuit showing the contents of the ccumultor nd ddend register fter ech clock pulse with the initil contents illustrted? (4 mrks) Accumultor x i y i Full Adder s i Addend register c i c o P shift Control Circuit D SET CLR Q Q N (Strt) Figure 4 Seril Adder (Question 4 continues on the following pge)

7 Pge 7 of 7 COMP20212 (Question 4 continues from the previous pge) d) Figure 5 illustrtes the ASM chrt descriing the opertion of the seril dder control circuit. Produce stte tle from this ASM chrt. You my ssume tht ech stte is ssigned the stte codes illustrted in Figure 5. Using mp-entered vriles where required, construct two-vrile next stte nd output Krnugh mps nd produce logic equtions for their implementtion. (5 mrks) Figure 5 END OF EXAMINATION