OUTLINE SYSTEMONCHIP DESIGN. GETTING STARTED WITH VHDL August 31, 2015 GAJSKI S YCHART (1983) TOPDOWN DESIGN (1)


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1 August 31, 2015 GETTING STARTED WITH VHDL 2 Topdown design VHDL history Min elements of VHDL Entities nd rhitetures Signls nd proesses Dt types Configurtions Simultor sis The testenh onept OUTLINE 3 GAJSKI S YCHART (193) 4 TOPDOWN DESIGN (1) BEHAVIORAL DOMAIN STRUCTURAL DOMAIN BEHAVIORAL DOMAIN STRUCTURAL DOMAIN Systems Algorithms Register trnsfers Logi Trnsfer funtions Trnsistor lyout Cell lyout Module lyout Proessors ALUs, RAMs, et. Gtes, flipflops, et. Trnsistors Topdown struturl deomposition + ottomup lyout onstrution Floorpln PHYSICAL DOMAIN PHYSICAL DOMAIN
2 5 6 TOPDOWN DESIGN (2) VHDL HISTORY d e f Struturl deomposition Communition does not hnge! d e f Inititive of the US Deprtment of Defense, prt of the Very High Speed Integrted Ciruit (VHSIC) progrmme running in the 0s, with gol of setting stndrd. VHDL = VHSIC Hrdwre Desription Lnguge Designed y group of experts Expliit support for multiple views: Seprtion of entity from rhiteture Stndrdized severl times y IEEE: Most importnt stndrds: 197, 1993 (used here!), 200. Grdully gined wide eptne (together with rivl lnguge Verilog) 7 EXAMPLE HARDWARE: siso ENTITY AND ARCHITECTURE lk reset dt_in siso dt_out req redy Seril in, seril out it dt Environment provides new dt_in when req is high Environment should ollet dt_out when redy is high. req, redy, nd dt_out re updted on rising edge of lk. dt_in is onsumed (nd should e stle) on rising edge of lk. VHDL diretly supports the onept of one ommunition interfe for lok with multiple desriptions of its ontents. Entity: delrtion of ommunition Arhiteture: delrtion of ontent: ehvior, struture or mix One entity n hve multiple rhitetures. Chek files: siso_ent.vhd siso_opy_rh.vhd siso_gd_rh.vhd
3 9 10 LIBRARIES, PACKAGES, SIGNALS AND PROCESSES Points of ttention: Lirry: preompiled design informtion, grouped y lirry nme. Pkge: design informtion of generl nture to e used in more speifi designs. Exmple: olletion of dt types nd funtions tht operte on them. Signl: rrier of vlues tht hnge in time, normlly ssoited to wire or wire undle in hrdwre. Proess: desription of how signls hnge their vlues. Multiple proesses model prllelism. COMBINATIONAL AND SEQUENTIAL LOGIC Points of ttention: Proesses n model logi with or without internl memory, sequentil resp. omintionl logi. Sensitivity list Coding style for synhronous sequentil logi with synhronous reset SIMULATOR BASICS The simultion engine of VHDL is solled eventdriven simultor. Events re signl hnges. An event triggers new events fter some dely. Events tke ple t some time. The simultor hndles events in the order of their tivtion time. In VHDL proesses re tivted for events on signls in their sensitivity lists. Proess tivtion generlly retes new events. Even when no dely is speified in the VHDL ode, the simultor will introdue n infinitesiml dely, solled delt dely. SIGNALS AND VARIABLES (1) A signl in VHDL is the equivlent of physil wire. Proesses ommunite vi signl hnges. Signls re lwys delred outside proess. Signl ssignments re indited y <= nd re never immedite, tke t lest delt dely. Signl ssignments n our outside proesses: onurrent ssignment, proess on its own.
4 13 SIGNALS AND VARIABLES (2) A signl ssignment orresponds to hrdwre: the omintion of signls t the righthnd side produes the signl t the lefthnd side. <= g(, ) <= f1( ) <= h(, ) Multiple ssignments to the sme signls is like shorting two outputs: it is not llowed unless the signl is resolved. 14 SIGNALS AND VARIABLES (3) Proesses n lso hve lol vriles: Delred inside proess Not visile to other proesses Vrile ssignment is indited y := nd is immedite. It is therefore llowed to perform multiple ssignments to vrile without dvning simultion time: This does not hve hrdwre equivlent. Avoid the use of vriles in the hrdwre tht you design! <= f1( ) <= f2( )?? 15 DATA TYPES IN VHDL Few uiltin dt types: integers, hrters, strings, time. Mehnism to define new dt types y enumertion, rrys, reords. Very ommon nonntive dt type: std_logi, defined in stndrdized pkge std_logi_1164, ompiled in lirry ieee (inluding funtions suh s Boolen opertors). Atully n enumertion of 9 hrters: 0, 1, Z, U, X, , et. Assoited vetor type std_logi_vetor, with onstnts written s strings, e.g std_logi is resolved type, i.e. resolution funtion omputes signl vlue in the se of multiple drivers. 16 NUMERIC DATA TYPES A sequene of its n e interpreted s numer. Multiple interprettions exist. The pkge numeri_std, stndrdized y the IEEE, ville in lirry ieee defines two interprettions for std_logi vetors: signed: signed numer enoded s 2 s omplement unsigned: positive inry numers. VHDL hs strong typing: ssignments from std_logi_vetor to signed/unsigned require type sting.
5 17 1 TESTBENCH (1) TESTBENCH (2) Simultion is the most ommon method to verify the orretness of design, the design under verifition (DUV). In order to simulte design, speifi signl ptterns need to e supplied to the inputs. It is onvenient to use universl HDL to desrie this signl genertion, in this se VHDL. It is lso onvenient to monitor the outputs of the DUV; sometimes input signls n e generted depending on the reeived outputs. This results in testvetor ontroller (TVC) with opposite I/O ptterns to the DUV. DUV + TVC = testenh (TB) The testenh does not hve ny I/O signls! Chek files: t_siso.vhd Note: TB hs struturl rhiteture. t_siso tv_siso dt_in req lk siso reset dt_out redy 19 CONFIGURATIONS A VHDL simultor is supposed to store ompiled versions of ll rhitetures of n entity simultneously. Question: how does one indite whih of the rhitetures should e simulted? Answer: VHDL onfigurtions define whih rhitetures to use for eh entity ll the wy down the hierrhy. Chek files: onf_t_siso_opy.vhd onf_t_siso_gd.vhd
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