16-bit ALU, Register File and Memory Write Interface
|
|
- Drusilla Miles
- 7 years ago
- Views:
Transcription
1 CS M152B Fall 2002 Project 2 16-bit ALU, Register File and Memory Write Interface Suggested Due Date: Monday, October 21, 2002 Actual Due Date determined by your Lab TA This project will take much longer time than the previous one. The three components you are building in the project will be put all together and program to the board to be tested. The three components do not depend on each other. Therefore, I suggest you to start them in parallel. The only thing that prevents you from fully parallelizing the work is because there is only one workstation for each group. So, you should consider how to fully utilizing your resources (your team members and the workstation) to finish this project soon. However, keep in mind that you should know how to build each component even if you are not participating in building some of the components. PART 0 In project 1, the & and functions are specified as logical, they should be bitwise. They are meant to be bitwise if you look at the expected test results. Sorry for the confusion. Now, do a modification to the 4-bit ALU built in project 1. Add the complement (bitwise NOT) operation. The control signal is 110 for NOT. Make sure your 4-bit ALU is built with minimum area. The chip area is measured in SLICEs. The chip has 768 SLICEs available. You can check the number of SLICEs used in your design from the Place & Route Report. The TA s implementation used 10 SLICEs for the 4-bit ALU. PART 1 16-Bit ALU Design You are asked to build a 16-bit asynchronous ALU that can do addition, subtraction, bitwise AND, bitwise OR, increment, decrement, bitwise NOT, shifting, and comparison. The top level schematic is shown in the following figure. Page 1 of 7
2 A(15:0) Cout zero S(15:0) B(15:0) ALUctrl(3:0) The following is the functional truth table. ALU Ctrl Function 0000 S = A + B 0001 S = A B 0010 S = A & B (bitwise AND) 0011 S = A B (bitwise OR) 0100 S = A S = A S = ~A (complement) 1100 S = A << B(3:0) (logical shift) 1110 S = A >> B(3:0) (logical shift) 1000 S = A << B(3:0) (arithmetic shift) 1010 S = A >> B(3:0) (arithmetic shift) 1001 If (A < B) S = 1 else S = 0 * The output zero is 1 when S is 0, otherwise zero is 0. * Be aware that the control signal is now 4 bits wide. * The shifting must be asynchronous (i.e. can t use shift register); the shifting distance range is between 0 and 15. * The ripple-carry is used between the 4-bit ALUs. * Your first priority is to minimize the area of your design; second priority is performance (delay) * You are welcome to use Schematic VHDL CORE IP Your previous project or any combination of the above Page 2 of 7
3 Hint: You can t put 4 copies your project 1 together plus some other components to build this 16- bit ALU. You can use it as the least significant 4-bit of the ALU but it requires some modifications for the most significant 12-bit of the ALU. Think about the A+1 and A-1 cases. One of the design choices of the shifting is barrel shifter. The (A < B) comparator can be done by a subtraction with the ALU. Simulation With ModelSim, simulate each function with some numbers for A and B of your choice just to make sure that it really works. PART 2 Register File Design You are asked to build a register file with eight 16-bit registers. It should have two read ports and one write port. The top level schematic is shown below. Ra Rb Rw WrEn busw Reg. File busa busb * busa, busb and busw are each 16 bits wide; Ra, Rb, and Rw are each 3 bits wide. * it works as the following: busa <= R[Ra]; busb <= R[Rb]; when WrEn is 1, R[Rw] <= busw at next clock cycle; * R[0] always holds value of 0; * Your first priority is to minimize the area of your design; second priority is performance (delay) * You are welcome to use Schematic VHDL CORE IP or any combination of the above Page 3 of 7
4 Suggestion: use FD16CE symbol as a single register to start building the register file. Simulation With ModelSim, simulate writing/reading values to/from the register file to make sure that it really works. PART 3 Memory Write Interface Design In order to write to the SRAM using the provided VHDL file sraminterfacewithpportsv01.vhd, you need to implement the protocol specified in page 3 of tutorial 2. The module that implements the protocol is referred as the Memory Interface here. Basically, the Memory Interface is a state machine. Therefore you need to understand the protocol and implement the state machine to interact with the provided VHDL module to write data. The following is the top level schematic of the memory interface and the sraminterfacewithpport-sv01.vhd module. IssueWrite resetl CanWrite DoWrite Memory Write Interface (to be built) WriteAddr WriteData Sraminterfacewithpportsv02.vhd (provided) WriteDone Memory Write Interface Module Inputs : ResetL (active low; to initial state) IssueWrite; CanWrite; Outputs: DoWrite; WriteDone; Page 4 of 7
5 * The interface should work according to the following: When writing a data, within the same clock cycle do { send the data on WriteData; send the addr on WriteAddr; assert the IssueWrite } after some number of clock cycles, the WriteDone signal goes high, meaning the write operation is done. * You can use Behavioral VHDL as long as it can be synthesis and other tools as usual to implement state machine. Simulate With ModelSim, verify the state transition goes correctly in your state machine design. Putting it all together Now, you should have a working 16-bit ALU, a register file and a memory write interface. Let s create a top level schematic that put all of these together like the following figure. Ra Rb Control Module provided by TA SelectL button WriteL button Reg. File busa ALU Ctrl Clk ResetL IssueWr NextWr Addr zero Memory write interface issuewrite resetl WriteDone canwrite dowrite Rw WrEn BusW busb ALU WriteAddr WriteData ALU Ctrl sraminterfacewithpport Go to My Network Places\Computers Near Me\152b-lab-01\Project2Files folder, copy all files to your local project directory. They includes the Control Module (TACM) and the sraminterfacewithpport files. Page 5 of 7
6 This circuit will allow you to do an ALU operation on two registers and write the result back into a register as well as write to the memory, from where you can dump to check the result. PIN allocation: a single reset input connect to the resets of the control module, the memory write interface and the sraminterfacewithpport module; this single reset <= push button 1 (remember, all reset should be active low) a single input connect to the of all modules that has the inputs. This single <= usual pin. Control Module o SelectL button(active low) <= push button 4 o WriteL button(active low) <= push button 3 Register File (because we only have 8 dip switches, the MS bit of Rb is forced to 1 ) o Ra(2:0) <= dip switch(1:3) o Rb(1:0) <= dip switch(4:5) o Rw <= dip switch(6:8) Make an output bus from ALUCtrl o ALUCtrl(3:0) <= bar LED(9:6) And don t forget to connect the pins for the sraminterfacewithpport o the left bank SRAM ldata(15:0) laddr(18:0) lcen loen lwen o the parallel port ppdata(7:0) ppstatus(6:3) Program to the Board and Test After you finish this top level schematic, you can simulate it with ModelSim (optional). Then you need to program it to the board. Testing Procedure: 1. Press the push button 1 to reset. 2. Flip to dip switches to select the operands and the destination register. 3. Repeat pressing the push button 4 to select an ALU function of your choice (the control code of the operation is shown on bar LED (9:6) 4. Press the push button 3 to write 5. Dump the memory contents to the screen. 6. If you want to test more, go back to step 2. Page 6 of 7
7 Project Report Describe your design for PART 1-3. Report the number of SLICEs used for each part (1-3) separately. (the SLICEs information can be found in the Place & Route Report) Report the Maximum Net Delay of each part (1-3) separately. (the Delay information can be found in the Asynchronous Delay Report) The End of Project 2. General Hints in Using the Tools If you need to put a lot of the same components in the schematic, put one first, draw wires to all inputs/outputs. Then select this component and all the wires by drawing selecting square. Then copy & paste. You can get 1, 2, 4, 8, 16, 32 of the same components with wires fast by repeating copy & paste. (Notice that the copy and paste will not copy the wire name) When you backup your file, you should select Project -> Delete Implementation Data, then select Project-> Archive to create a zip file. You can unzip a file from the DOS prompt by unzip [zipfile] d [directory] (Notice that if you delete the implementation data, you need to redo the Synthesize and Implement steps to your design in order to program to the board. Components generated from COREgen IP tend to take up more SLICEs than the symbols from the library. In schematic, two wires are connected if they have the same name even they appear to be not connected in the editor. As the design gets big, it will make the schematic really messy if all the wires are connected. Another thing is that you don t need to use any bus trap. Just name a wire called ABC(2:0), and name other wires ABC(0), ABC(1), ABC(2). Then they are connected just like there were the bus traps. Page 7 of 7
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data
More informationXilinx ISE. <Release Version: 10.1i> Tutorial. Department of Electrical and Computer Engineering State University of New York New Paltz
Xilinx ISE Tutorial Department of Electrical and Computer Engineering State University of New York New Paltz Fall 2010 Baback Izadi Starting the ISE Software Start ISE from the
More informationComputer organization
Computer organization Computer design an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine inputs
More informationCHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
More informationEXPERIMENT 8. Flip-Flops and Sequential Circuits
EXPERIMENT 8. Flip-Flops and Sequential Circuits I. Introduction I.a. Objectives The objective of this experiment is to become familiar with the basic operational principles of flip-flops and counters.
More informationModeling Latches and Flip-flops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
More informationChapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language
Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,
More informationMore Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset.
More Verilog 8-bit Register with Synchronous Reset module reg8 (reset, CLK, D, Q); input reset; input [7:0] D; output [7:0] Q; reg [7:0] Q; if (reset) Q = 0; else Q = D; module // reg8 Verilog - 1 Verilog
More information(Refer Slide Time: 00:01:16 min)
Digital Computer Organization Prof. P. K. Biswas Department of Electronic & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Lecture No. # 04 CPU Design: Tirning & Control
More informationETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
More informationMICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1
MICROPROCESSOR A microprocessor incorporates the functions of a computer s central processing unit (CPU) on a single Integrated (IC), or at most a few integrated circuit. It is a multipurpose, programmable
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationRegisters & Counters
Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multi-bit storage devices. Introduce counters by adding logic to registers implementing
More informationModeling Registers and Counters
Lab Workbook Introduction When several flip-flops are grouped together, with a common clock, to hold related information the resulting circuit is called a register. Just like flip-flops, registers may
More information5 Combinatorial Components. 5.0 Full adder. Full subtractor
5 Combatorial Components Use for data transformation, manipulation, terconnection, and for control: arithmetic operations - addition, subtraction, multiplication and division. logic operations - AND, OR,
More informationJianjian Song LogicWorks 4 Tutorials (5/15/03) Page 1 of 14
LogicWorks 4 Tutorials Jianjian Song Department of Electrical and Computer Engineering Rose-Hulman Institute of Technology March 23 Table of Contents LogicWorks 4 Installation and update...2 2 Tutorial
More informationLab 1: Introduction to Xilinx ISE Tutorial
Lab 1: Introduction to Xilinx ISE Tutorial This tutorial will introduce the reader to the Xilinx ISE software. Stepby-step instructions will be given to guide the reader through generating a project, creating
More informationDecimal Number (base 10) Binary Number (base 2)
LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be
More informationECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog
ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();
More informationTo design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
More informationAfter opening the Programs> Xilinx ISE 8.1i > Project Navigator, you will come to this screen as start-up.
After opening the Programs> Xilinx ISE 8.1i > Project Navigator, you will come to this screen as start-up. Start with a new project. Enter a project name and be sure to select Schematic as the Top-Level
More information150127-Microprocessor & Assembly Language
Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs an
More informationMICROPROCESSOR AND MICROCOMPUTER BASICS
Introduction MICROPROCESSOR AND MICROCOMPUTER BASICS At present there are many types and sizes of computers available. These computers are designed and constructed based on digital and Integrated Circuit
More informationGenerating MIF files
Generating MIF files Introduction In order to load our handwritten (or compiler generated) MIPS assembly problems into our instruction ROM, we need a way to assemble them into machine language and then
More informationThe 104 Duke_ACC Machine
The 104 Duke_ACC Machine The goal of the next two lessons is to design and simulate a simple accumulator-based processor. The specifications for this processor and some of the QuartusII design components
More informationSerial Communications
April 2014 7 Serial Communications Objectives - To be familiar with the USART (RS-232) protocol. - To be able to transfer data from PIC-PC, PC-PIC and PIC-PIC. - To test serial communications with virtual
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
More informationEXPERIMENT 4. Parallel Adders, Subtractors, and Complementors
EXPERIMENT 4. Parallel Adders, Subtractors, and Complementors I. Introduction I.a. Objectives In this experiment, parallel adders, subtractors and complementors will be designed and investigated. In the
More informationECE 451 Verilog Exercises. Sept 14, 2007. James Barnes (James.Barnes@colostate.edu)
ECE 451 Verilog Exercises Sept 14, 2007 James Barnes (James.Barnes@colostate.edu) Organization These slides give a series of self-paced exercises. Read the specification of each exercise and write your
More informationLAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters
LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters LAB OBJECTIVES 1. Introduction to latches and the D type flip-flop 2. Use of actual flip-flops to help you understand sequential
More informationUNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180B Lab 7: MISP Processor Design Spring 1995
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180B Lab 7: MISP Processor Design Spring 1995 Objective: In this lab, you will complete the design of the MISP processor,
More informationLab 1: Full Adder 0.0
Lab 1: Full Adder 0.0 Introduction In this lab you will design a simple digital circuit called a full adder. You will then use logic gates to draw a schematic for the circuit. Finally, you will verify
More informationRegister File, Finite State Machines & Hardware Control Language
Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework
More informationState Machines in VHDL
State Machines in VHDL Implementing state machines in VHDL is fun and easy provided you stick to some fairly well established forms. These styles for state machine coding given here is not intended to
More informationMS Visual C++ Introduction. Quick Introduction. A1 Visual C++
MS Visual C++ Introduction 1 Quick Introduction The following pages provide a quick tutorial on using Microsoft Visual C++ 6.0 to produce a small project. There should be no major differences if you are
More informationTRILOGI 5.3 PLC Ladder Diagram Programmer and Simulator. A tutorial prepared for IE 575 by Dr. T.C. Chang. Use On-Line Help
TRILOGI 5.3 PLC Ladder Diagram Programmer and Simulator A tutorial prepared for IE 575 by Dr. T.C. Chang 1 Use On-Line Help Use on-line help for program editing and TBasic function definitions. 2 Open
More informationDebouncing Switches. Mechanical switches are one of the most common interfaces to a uc.
Mechanical switches are one of the most common interfaces to a uc. Switch inputs are asynchronous to the uc and are not electrically clean. Asynchronous inputs can be handled with a synchronizer (2 FF's).
More informationTwo's Complement Adder/Subtractor Lab L03
Two's Complement Adder/Subtractor Lab L03 Introduction Computers are usually designed to perform indirect subtraction instead of direct subtraction. Adding -B to A is equivalent to subtracting B from A,
More informationA Verilog HDL Test Bench Primer Application Note
A Verilog HDL Test Bench Primer Application Note Table of Contents Introduction...1 Overview...1 The Device Under Test (D.U.T.)...1 The Test Bench...1 Instantiations...2 Figure 1- DUT Instantiation...2
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationCSE 141L Computer Architecture Lab Fall 2003. Lecture 2
CSE 141L Computer Architecture Lab Fall 2003 Lecture 2 Pramod V. Argade CSE141L: Computer Architecture Lab Instructor: TA: Readers: Pramod V. Argade (p2argade@cs.ucsd.edu) Office Hour: Tue./Thu. 9:30-10:30
More informationCS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
More informationLAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER
LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER OBJECTIVES 1. Learn the basic elements of VHDL that are implemented in Warp. 2. Build a simple application using VHDL and
More informationA New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
More informationModeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationLab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts)
Dr. Greg Tumbush, gtumbush@uccs.edu Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts) Objective The objective of lab assignments 5 through 9 are to systematically design and implement
More informationMACHINE ARCHITECTURE & LANGUAGE
in the name of God the compassionate, the merciful notes on MACHINE ARCHITECTURE & LANGUAGE compiled by Jumong Chap. 9 Microprocessor Fundamentals A system designer should consider a microprocessor-based
More informationA Program for PCB Estimation with Altium Designer
A Program for PCB Estimation with Altium Designer By: Steve Hageman AnalogHome.com One thing that I have had to do over and over on my new PCB jobs is to make an estimate of how long I think the layout
More informationLAB4: Audio Synthesizer
UC Berkeley, EECS 100 Lab LAB4: Audio Synthesizer B. Boser NAME 1: NAME 2: The 555 Timer IC SID: SID: Inductors and capacitors add a host of new circuit possibilities that exploit the memory realized by
More informationEC313 - VHDL State Machine Example
EC313 - VHDL State Machine Example One of the best ways to learn how to code is seeing a working example. Below is an example of a Roulette Table Wheel. Essentially Roulette is a game that selects a random
More informationComputer Organization and Components
Computer Organization and Components IS1500, fall 2015 Lecture 5: I/O Systems, part I Associate Professor, KTH Royal Institute of Technology Assistant Research Engineer, University of California, Berkeley
More informationLab 11 Digital Dice. Figure 11.0. Digital Dice Circuit on NI ELVIS II Workstation
Lab 11 Digital Dice Figure 11.0. Digital Dice Circuit on NI ELVIS II Workstation From the beginning of time, dice have been used for games of chance. Cubic dice similar to modern dice date back to before
More informationCombinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate K-maps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More information1. Product Information
ORIXCLOUD BACKUP CLIENT USER MANUAL LINUX 1. Product Information Product: Orixcloud Backup Client for Linux Version: 4.1.7 1.1 System Requirements Linux (RedHat, SuSE, Debian and Debian based systems such
More informationCS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on
CS 61C: Great Ideas in Computer Architecture Finite State Machines Instructors: Krste Asanovic & Vladimir Stojanovic hbp://inst.eecs.berkeley.edu/~cs61c/sp15 1 Levels of RepresentaKon/ InterpretaKon High
More informationPart I. The Picture class
CS 161 LAB 5 This lab will have two parts. In the first part, we will create a class to automate the drawing of the robot from the second lab. For the second part, we will begin a ClunkyCalculator class
More informationMentor Tools tutorial Bold Browser Design Manager Design Architect Library Components Quicksim Creating and Compiling the VHDL Model.
Mentor Tools tutorial Bold Browser Design Manager Design Architect Library Components Quicksim Creating and Compiling the VHDL Model. Introduction To Mentor Graphics Mentor Graphics BOLD browser allows
More informationDesign Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
More informationl C-Programming l A real computer language l Data Representation l Everything goes down to bits and bytes l Machine representation Language
198:211 Computer Architecture Topics: Processor Design Where are we now? C-Programming A real computer language Data Representation Everything goes down to bits and bytes Machine representation Language
More informationDigital Design with VHDL
Digital Design with VHDL CSE 560M Lecture 5 Shakir James Shakir James 1 Plan for Today Announcement Commentary due Wednesday HW1 assigned today. Begin immediately! Questions VHDL help session Assignment
More informationDigitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah
(DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de NIOS II 1 1 What is Nios II? Altera s Second Generation
More informationTechnical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students
Session: 2220 Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students Adam S. El-Mansouri, Herbert L. Hess, Kevin M. Buck, Timothy Ewers Microelectronics
More informationMAX II ISP Update with I/O Control & Register Data Retention
MAX II ISP Update with I/O Control & Register Data Retention March 2006, ver 1.0 Application Note 410 Introduction MAX II devices support the real-time in-system mability (ISP) feature that allows you
More informationPacket Tracer 3 Lab VLSM 2 Solution
Packet Tracer 3 Lab VLSM 2 Solution Objective Create a simulated network topology using Packet Tracer Design an IP addressing scheme using a Class B subnetwork address and VLSM Apply IP addresses to the
More informationDDS. 16-bit Direct Digital Synthesizer / Periodic waveform generator Rev. 1.4. Key Design Features. Block Diagram. Generic Parameters.
Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core 16-bit signed output samples 32-bit phase accumulator (tuning word) 32-bit phase shift feature Phase resolution of 2π/2
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationModelSim-Altera Software Simulation User Guide
ModelSim-Altera Software Simulation User Guide ModelSim-Altera Software Simulation User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01102-2.0 Document last updated for Altera Complete
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 9 - Register Transfer and Microoperations Microoperations Digital systems are modular in nature, with modules containing registers, decoders, arithmetic
More informationRAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston
More informationTechnical Note. Micron NAND Flash Controller via Xilinx Spartan -3 FPGA. Overview. TN-29-06: NAND Flash Controller on Spartan-3 Overview
Technical Note TN-29-06: NAND Flash Controller on Spartan-3 Overview Micron NAND Flash Controller via Xilinx Spartan -3 FPGA Overview As mobile product capabilities continue to expand, so does the demand
More informationBINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
More informationStart Active-HDL by double clicking on the Active-HDL Icon (windows).
Getting Started Using Aldec s Active-HDL This guide will give you a short tutorial in using the project mode of Active-HDL. This tutorial is broken down into the following sections 1. Part 1: Compiling
More informationDEPARTMENT OF INFORMATION TECHNLOGY
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453
More information9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More informationAn Introduction to MPLAB Integrated Development Environment
An Introduction to MPLAB Integrated Development Environment 2004 Microchip Technology Incorporated An introduction to MPLAB Integrated Development Environment Slide 1 This seminar is an introduction to
More informationPhysics 226 FPGA Lab #1 SP Wakely. Terasic DE0 Board. Getting Started
Physics 226 FPGA Lab #1 SP Wakely I Terasic DE0 Board The DE0 Development and Education board is designed in a compact size with all the essential tools for novice users to gain knowledge in areas of digital
More informationDesigning VM2 Application Boards
Designing VM2 Application Boards This document lists some things to consider when designing a custom application board for the VM2 embedded controller. It is intended to complement the VM2 Datasheet. A
More informationThe WIMP51: A Simple Processor and Visualization Tool to Introduce Undergraduates to Computer Organization
The WIMP51: A Simple Processor and Visualization Tool to Introduce Undergraduates to Computer Organization David Sullins, Dr. Hardy Pottinger, Dr. Daryl Beetner University of Missouri Rolla Session I.
More informationVHDL Test Bench Tutorial
University of Pennsylvania Department of Electrical and Systems Engineering ESE171 - Digital Design Laboratory VHDL Test Bench Tutorial Purpose The goal of this tutorial is to demonstrate how to automate
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationQuartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1
(DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera
More informationOnline Backup Client User Manual Linux
Online Backup Client User Manual Linux 1. Product Information Product: Online Backup Client for Linux Version: 4.1.7 1.1 System Requirements Operating System Linux (RedHat, SuSE, Debian and Debian based
More informationENGI E1112 Departmental Project Report: Computer Science/Computer Engineering
ENGI E1112 Departmental Project Report: Computer Science/Computer Engineering Daniel Estrada Taylor, Dev Harrington, Sekou Harris December 2012 Abstract This document is the final report for ENGI E1112,
More informationFORDHAM UNIVERSITY CISC 3593. Dept. of Computer and Info. Science Spring, 2011. Lab 2. The Full-Adder
FORDHAM UNIVERSITY CISC 3593 Fordham College Lincoln Center Computer Organization Dept. of Computer and Info. Science Spring, 2011 Lab 2 The Full-Adder 1 Introduction In this lab, the student will construct
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
More informationLesson 1 - Creating a Project
Lesson 1 - Creating a Project The goals for this lesson are: Create a project A project is a collection entity for an HDL design under specification or test. Projects ease interaction with the tool and
More informationDesigning a Schematic and Layout in PCB Artist
Designing a Schematic and Layout in PCB Artist Application Note Max Cooper March 28 th, 2014 ECE 480 Abstract PCB Artist is a free software package that allows users to design and layout a printed circuit
More informationTutorial: Configuring GOOSE in MiCOM S1 Studio 1. Requirements
Tutorial: Configuring GOOSE in MiCOM S1 Studio 1. Requirements - Two (2) MiCOM Px4x IEDs with Version 2 implementation of IEC 61850 - Two (2) Cat 5E Ethernet cable - An Ethernet switch 10/100 Mbps - MiCOM
More information1. Convert the following base 10 numbers into 8-bit 2 s complement notation 0, -1, -12
C5 Solutions 1. Convert the following base 10 numbers into 8-bit 2 s complement notation 0, -1, -12 To Compute 0 0 = 00000000 To Compute 1 Step 1. Convert 1 to binary 00000001 Step 2. Flip the bits 11111110
More informationInterfacing Analog to Digital Data Converters
Converters In most of the cases, the PIO 8255 is used for interfacing the analog to digital converters with microprocessor. We have already studied 8255 interfacing with 8086 as an I/O port, in previous
More informationPROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 TUTORIAL OUTCOME 2 Part 1
UNIT 22: PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 TUTORIAL OUTCOME 2 Part 1 This work covers part of outcome 2 of the Edexcel standard module. The material is
More informationFlip-Flops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationFinal Project: Enhanced Music Synthesizer and Display Introduction
Final Project: Enhanced Music Synthesizer and Display Introduction The final project will provide you with a complete digital systems design experience. It encompasses all of the elements you have encountered
More information- 35mA Standby, 60-100mA Speaking. - 30 pre-defined phrases with up to 1925 total characters.
Contents: 1) SPE030 speech synthesizer module 2) Programming adapter kit (pcb, 2 connectors, battery clip) Also required (for programming) : 4.5V battery pack AXE026 PICAXE download cable Specification:
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More informationCadence Verilog Tutorial Windows Vista with Cygwin X Emulation
Cadence Verilog Tutorial Windows Vista with Cygwin X Emulation This tutorial will serve as an introduction to the use of the Cadence Verilog simulation environment and as a design tool. The Cadence design
More information1 Description of The Simpletron
Simulating The Simpletron Computer 50 points 1 Description of The Simpletron In this assignment you will write a program to simulate a fictional computer that we will call the Simpletron. As its name implies
More information