Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-265 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our on-line resources nd Using Blckfin Processor Flg Pins to Emulte the PCM Interfce Contributed by Shilendr Miglni Rev 1 Mrch 23, 2005 Introduction The PCM interfce is seril interfce used to trnsfer speech dt. This ppliction note discusses how to emulte the PCM interfce using four progrmmble flg pins (GPIOs) of the Blckfin processor. This ppliction note pplies to designs in which ll of the seril interfces present on the devices re in use nd hence the need for emultion of the PCM interfce rises. Bsics of the PCM Protocol In the PCM mode of opertion, there re four signls (PCM_CLK, PCM_SYNC, PCM_OUT, nd PCM_IN). There re three modes of opertion for PCM: (1) Short frme sync mode (2) Long frme sync mode (3) Multi-slot mode The timing nd description of ll three modes re discussed below. In short frme sync mode (Figure 1), the flling edge of PCM_SYNC indictes the strt of the PCM word. PCM_SYNC is lwys one clock cycle long. In the next rising edge following the frme sync, dt is driven out. Figure 1. Short Frme Sync Mode The timing for the long frme sync mode is shown in Figure 2: Figure 2. Long Frme Sync Mode In long frme sync mode, the rising edge of PCM_SYNC indictes the strt of the PCM word. The timing for the multi-slot opertion is shown in Figure 3. Copyright 2005, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 PF12 DR Figure 4. Interfce to SPORT (Flg in Trnsmit Mode) for Long nd Short Frme Sync Figure 3. Multi-Slot Mode In multi-slot mode, fter receiving short frme sync or long frme sync, the trnsmitter sends out three words of dt. The progrmmble flg-bsed PCM interfce is implemented for trnsmit s well s receive. The Seril Port of is used to verify the logic for both trnsmit nd receive. When the flg pins trnsmit, the SPORT receives the dt with the externl clock nd frme sync. When the flg pins receive the dt, the SPORT trnsmits with the internl clock nd frme sync. Short nd Long Frme Sync Implementtion The PCM interfce cn be emulted using four progrmmble flgs. This implementtion uses,, PF11, nd PF12. is used s the clock. is used s the frme sync. PF11 is used s the dt receive, nd PF12 is used s the dt trnsmit. For dt receive, the dt is sent through the SPORT nd the dt is received through the flgs. In trnsmit mode, the dt is trnsmitted through the SPORT nd is received through the progrmmble flgs. PF11 TCLK TFS DT Figure 5. Interfce to SPORT (Flg in Receive Mode) for Long nd Short Frme Sync Trnsmit in Short nd Long Frme Sync In this mode, the core timer is used to generte the interrupt t rte twice tht of the desired clock rte, since the flg pins hve to toggle twice per clock cycle. In this mode, the,, nd PF11 flg pins re configured s outputs. In short frme sync mode, when timer interrupt is generted, the code brnches to the ISR nd is toggled inside the ISR to generte the clock. Eight-bit dt trnsfers re ssumed in this mode. The frme sync is sserted t the rising edge of the clock s per the specifiction of the PCM interfce. The frme sync will be ctive for one clock cycle. After the frme sync is desserted nd on the immedite next rising Using Blckfin Processor Flg Pins to Emulte the PCM Interfce (EE-265) Pge 2 of 5

3 edge, the dt is driven out bit by bit for one byte. Figure 6 shows timing for short frme sync mode. Figure 6. Wveforms of Clock (Green), Frme Sync (Green) nd Dt (Yellow) for Short Frme Sync In long frme sync mode, when the timer interrupt is sserted the code brnches to the ISR nd strts toggling to generte the clock. Eight-bit dt trnsfers re ssumed in this scenrio. The frme sync is sserted t the rising edge of the clock s per the specifiction of the PCM interfce. After frme sync is sserted, in the sme rising edge, the dt is driven out bit by bit for one byte. Figure 7 shows timing for long frme sync. The frme sync is ctive throughout the dt trnsfer. To vlidte whether the logic hs been implemented correctly, the dt is received through the SPORT1 in erly frme sync mode for short frme sync (nd lte frme sync mode for long frme sync). Receive in Short nd Long Frme Sync In the receive mode, flg pins re connected to the Seril Ports nd the dt is trnsmitted through the SPORT interfce nd received through the PCM interfce relized through the flg pins. In receive mode;,, nd PF12 re configured s inputs. In the implementtion, is configured s edge sensitive for rising edge, nd the interrupt is enbled for the sme. As soon s the clock is pplied, the code brnches into the interrupt service routine (ISR) nd frme sync ssertion is checked. Inside the ISR, if the frme sync is not shown sserted, the code continuously brnches to the ISR, but no dt is driven in. In short frme sync mode, s soon s the frme sync is sserted nd then desserted (s mentioned erlier, this is checked inside the ISR of ) from the Seril Port, the dt is driven in bit by bit by reding PF11. The width of the dt is lso eight bits. Figure 7. Wveforms of Clock (Yellow), Frme Sync (Violet) nd Dt (Green) for Long Frme Sync Figure 8. Wveforms of Clock (Yellow), Frme Sync (Green) nd Dt (Violet) for Multi-Slot Mode Using Blckfin Processor Flg Pins to Emulte the PCM Interfce (EE-265) Pge 3 of 5

4 In long frme sync mode, s soon s the frme sync is sserted from the Seril Port, the dt is driven in bit by bit by reding PF11. The width of the dt is eight bits. Trnsmit nd Receive in Multi- Slot Mode For multi-slot mode, the SPORT interfce supports minimum of eight chnnels. In the present implementtion, erly frme sync is considered. In this mode, fter the frme sync, three chnnels (words) re trnsmitted by the GPIOs, nd three chnnels (words) re received by the SPORTs. PF12 BF 561 DR Figure 9. Interfce to SPORT (Flg in Trnsmit Mode) for Multi-Slot Mode PF11 DT Figure 10. Interfce to SPORT (Flg in Receive Mode) for Multi-Slot Mode In receive mode, when the SPORT is trnsmitting nd the progrmmble flgs re receiving, the SPORT is trnsmitting three of the eight chnnels, nd the progrmmble flgs re receiving three chnnels. In this scenrio, for there is no problem receiving dt, since the logic of the flg pins re implemented in such wy tht fter the frme sync, it will receive three words nd then wit for the next frme sync nd then drive three dt words. Hence, there is no problem for the logic s fr s five inctive slots out of eight re concerned, since fter receiving three dt words, it will wit for the next frme sync. The logic hs been verified by trnsmitting set of dt by SPORT nd receiving the sme set by the flg pins. Hence, for trnsmit, fter getting the frme sync followed by the flling edge of frme sync, three words re trnsmitted. For the, minimum of eight words re expected by the SPORT interfce. Hence, to verify tht the logic is working correctly, three words re sent nd then three words re received nd then stopping with SPORT receiving in multichnnel mode. The trnsmitted dt is viewed on scope plots to verify the dt trnsmission. Clock Frequency When the SPORT is trnsmitting the dt, the clock rte is specified by the SPORT1_TSCLKDIV register. For trnsmit, the clock is generted using flgs. After generting the timer interrupt, inside the ISR the flg is toggled twice to generte the clock. For exmple, to generte n 8 khz clock rte, the interrupt for the timer should be generted t 16 khz. If the EZ-KIT Lite bord is running t core clock frequency of 300 MHz nd generting n interrupt t 16 khz, the timer should be progrmmed to generte n interrupt for cycles. In similr fshion, the timer prmeters should be configured for the desired clock rte. Using Blckfin Processor Flg Pins to Emulte the PCM Interfce (EE-265) Pge 4 of 5

5 Test Cse Implementtion Three test cses re ttched to this ppliction note: (1) Short frme sync mode (2) Long frme sync mode (3) Multi-slot mode Ech test cse includes one trnsmit code exmple nd one receive code exmple. The trnsmit code exmple genertes internl frme sync nd clock using flgs, nd the receive code exmple tkes the externl frme nd clock. Ech test cse is verified by using SPORTs. Conclusion PCM interfce hs been successfully relized using the flg pins of processor. References [1] Blckfin Processor Hrdwre Reference. Rev 0.2, Anlog Devices, Inc. [2] Blckfin Embedded Symmetric Multiprocessor Dt Sheet. Rev PrE, Anlog Devices, Inc. [3] EZ-KIT Lite Mnul. Rev 1.1, Anlog Devices, Inc. Document History Revision Rev 1 Mrch 23, 2005 by Shilendr Miglni Description Initil Relese Using Blckfin Processor Flg Pins to Emulte the PCM Interfce (EE-265) Pge 5 of 5