Chapter 10 Computer Design Basics

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1 Logic ad Computer Desig Fudametals Chapter 10 Computer Desig Basics Part 1 Datapaths Charles Kime & Thomas Kamiski 2004 Pearso Educatio, Ic. Terms of Use (Hyperliks are active i View Show mode)

2 Overview Part 1 Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio Cotrol Word Part 2 A Simple Computer Istructio Set Architecture (ISA) Sigle-Cycle Hardwired Cotrol Istructio Decoder Sample Istructios Sigle Cycle Computer Issues Multiple Cycle Hardwired Cotrol Sequetial Cotrol Desig Chapter 10 Part 1 2

3 Itroductio Computer Specificatio Istructio Set Architecture (ISA) -the specificatio of a computer's appearace to a programmer at its lowest level Computer Architecture - a high-level descriptio of the hardware implemetig the computer derived from the ISA The architecture usually icludes additioal specificatios such as speed, cost, ad reliability. Chapter 10 Part 1 3

4 Itroductio (cotiued) Simple computer architecture decomposed ito: Datapath for performig operatios Cotrol uit for cotrollig datapath operatios A datapath is specified by: A set of registers The microoperatios performed o the data stored i the registers A cotrol iterface Chapter 10 Part 1 4

5 Datapaths Guidig priciples for basic datapaths: The set of registers Collectio of idividual registers A set of registers with commo access resources called a register file A combiatio of the above Microoperatio implemetatio Oe or more shared resources for implemetig microoperatios Buses - shared trasfer paths Arithmetic-Logic Uit (ALU) - shared resource for implemetig arithmetic ad logic microoperatios Shifter - shared resource for implemetig shift microoperatios Chapter 10 Part 1 5

6 Datapath Example Four parallel-load registers Two mux-based register selectors Register destiatio decoder Mux B for exteral costat iput Buses A ad B with exteral address ad data outputs ALU ad Shifter with Mux F for output select Mux D for exteral data iput Logic for geeratig status bits V, C, N, Z Write D data Load eable Decoder D address 2 Costat i Destiatio select MB select V C N Z Load Load Load Load G select 4 Zero Detect MF select R0 R1 R2 R3 MD select 0 1 MUX D Bus D 0 1 MUX F F 2 2 A data 1 0 Bus A MUX B Bus B A B A B H select 2 B S 2:0 C i Arithmetic/logic uit (ALU) G A address A select 0 1 MUX 2 3 S 0 I R Shifter I L 0 H Fuctio uit B select B address 0 1 MUX 2 3 Chapter 10 Part 1 6 Register file B data Address Out Data Out Data I

7 Datapath Example: Performig a Microoperatio Microoperatio: R0 R1 + R2 Apply 01 to A select to place cotets of R1 oto Bus A Apply 10 to B select to place cotets of R2 oto B data ad apply 0 to MB select to place B data o Bus B Apply 0010 to G select to perform additio G = Bus A + Bus B Apply 0 to MF select ad 0 to MD select to place the value of G oto BUS D Apply 00 to Destiatio select to eable the Load iput to R0 Apply 1 to Load Eable to force the Load iput to R0 to 1 so that R0 is loaded o the clock pulse (ot show) The overall microoperatio requires 1 clock cycle Write D data Load eable Decoder D address 2 Costat i Destiatio select MB select V C N Z Load Load Load Load G select 4 Zero Detect MF select R0 R1 R2 R3 MD select 0 1 MUX D Bus D 0 1 MUX F F 2 2 A data 1 0 Bus A MUX B Bus B A B A B H select 2 B S 2:0 C i Arithmetic/logic uit (ALU) G A address A select 0 1 MUX 2 3 S 0 I R Shifter I L 0 H Fuctio uit B select B address 0 1 MUX 2 3 Chapter 10 Part 1 7 Register file B data Address Out Data Out Data I

8 Datapath Example: Key Cotrol Actios for Microoperatio Alteratives Perform a shift microoperatio apply 1 to MF select Use a costat i a microoperatio usig Bus B apply 1 to MB select Provide a address ad data for a memory or output write microoperatio apply 0 to Load eable to prevet register loadig Provide a address ad obtai data for a memory or output read microoperatio apply 1 to MD select For some of the above, other cotrol sigals become do't cares Write D data Load eable Decoder D address 2 Costat i Destiatio select MB select V C N Z Load Load Load Load G select 4 R0 R1 R2 R3 Zero Detect 0 1 MF select MUX F F MD select 0 1 MUX D Bus D 2 2 A data 1 0 Bus A MUX B Bus B A B A B H select 2 B S 2:0 C i Arithmetic/logic uit (ALU) G A address A select 0 1 MUX 2 3 S 0 I R Shifter I L 0 H Fuctio uit B select B address 0 1 MUX 2 3 Register file B data Address Out Data Out Chapter 10 Part 1 8 Data I

9 Arithmetic Logic Uit (ALU) I this ad the ext sectio, we deal with detailed desig of typical ALUs ad shifters Decompose the ALU ito: A arithmetic circuit A logic circuit A selector to pick betwee the two circuits Arithmetic circuit desig Decompose the arithmetic circuit ito: A -bit parallel adder A block of logic that selects four choices for the B iput to the adder See ext slide for diagram Chapter 10 Part 1 9

10 Arithmetic Circuit Desig (cotiued) There are oly four fuctios of B to select as Y i G = A + Y: C i = 0 C i = 1 0 B B 1 G = A G = A + B G = A + B G = A 1 G = A + 1 G = A + B + 1 G = A + B + 1 G = A What fuctios are implemeted with carry-i to the adder = 0? =1? Ci A X B B iput logic S0 Y -bit parallel adder G5 X1 Y1 Ci S1 Cout Chapter 10 Part 1 10

11 Adobe Systems Arithmetic Circuit Desig (cotiued) Addig selectio codes to the fuctios of B: TA BLE 10-1 Fuctio Table for A rithmetic Circuit Select Iput S 1 S 0 Y = = 0 0 all 0's (trasfer) (icremet) 0 1 B + (add) 1 0 (subtract) 1 1 all 1' The useful arithmetic fuctios are labeled i the table Note that all four fuctios of B produce at least oe useful fuctio Chapter 10 Part 1 11

12 Logic Circuit The text gives a circuit implemeted usig a multiplexer plus gates implemetig: AND, OR, XOR ad NOT Here we custom desig a circuit for bit G i by begiig with a truth table orgaized as a K-map ad assigig (S1, S0) codes to AND, OR, etc. G i = S 0 A i B i + S 1 A i B i S 1 S 0 + S 0 A i B i + S 1 S 0 A i Gate iput cout for MUX solutio > 29 Gate iput cout for above circuit < 20 Custom desig better AND OR XOR NOT A i B i Chapter 10 Part 1 12

13 Arithmetic Logic Uit (ALU) The custom circuit has iterchaged the (S 1,S 0 ) codes for XOR ad NOT compared to the MUX circuit. To preserve compatibility with the text, we use the MUX solutio. Next, use the arithmetic circuit, the logic circuit, ad a 2-way multiplexer to form the ALU. See the ext slide for the bit slice diagram. The iput coectios to the arithmetic circuit ad logic circuit have bee bee assiged to prepare for seamless additio of the shifter, keepig the selectio codes for the combied ALU ad the shifter at 4 bits: Carry-i C i ad Carry-out C i+1 go betwee bits A i ad B i are coected to both uits A ew sigal S 2 performs the arithmetic/logic selectio The select sigal eterig the LSB of the arithmetic circuit, C i, is coected to the least sigificat selectio iput for the logic circuit, S 0. Chapter 10 Part 1 13

14 Arithmetic Logic Uit (ALU) (cotiued) C i C i C i + 1 A i B i S 0 S 1 A i B i S 0 S 1 Oe stage of arithmetic circuit 0 2-to-1 MUX G i A i 1 S C i B i S 0 Oe stage of logic circuit S 1 S 2 The ext most sigificat select sigals, S0 for the arithmetic circuit ad S1 for the logic circuit, are wired together, completig the two select sigals for the logic circuit. The remaiig S1 completes the three select sigals for the arithmetic circuit. Chapter 10 Part 1 14

15 Combiatioal Shifter Parameters Directio: Left, Right Number of positios with examples: Sigle bit: 1 positio 0 ad 1 positios Multiple bit: 1 to 1 positios 0 to 1 positios Fillig of vacat positios May optios depedig o istructio set Here, will provide iput lies or zero fill Chapter 10 Part 1 15

16 4-Bit Basic Left/Right Shifter Serial output L B 3 B 2 B 1 B 0 I R Serial output R I L S M U X S M U X S 0 1 2M U X S M U X S 2 H 3 H 2 Serial Iputs: Shift Fuctios: I R for right shift (S 1, S 0 ) = 00 Pass B uchaged I L for left shift 01 Right shift Serial Outputs 10 Left shift R for right shift (Same as MSB iput) 11 Uused L for left shift (Same as LSB iput) H 1 H 0 Chapter 10 Part 1 16

17 Barrel Shifter D3 D2 D1 D0 S0 S S1 S S1 S S1 S S1 S0 M UX M UX M UX M UX Y3 A rotate is a shift i which the bits shifted out are iserted ito the positios vacated The circuit rotates its cotets left from 0 to 3 positios depedig o S: S = 00 positio uchaged S = 10 rotate left by 2 positios S = 01 rotate left by 1 positios S = 11 rotate left by 3 positios See Table 10-3 i text for details Y2 Y1 Y0 Chapter 10 Part 1 17

18 Barrel Shifter (cotiued) Large barrel shifters ca be costructed by usig: Layers of multiplexers - Example 64-bit: Layer 1 shifts by 0, 16, 32, 48 Layer 2 shifts by 0, 4, 8, 12 Layer 3 shifts by 0, 1, 2, 3 See example i sectio 12-2 of the text 2 - dimesioal array circuits desiged at the electroic level Chapter 10 Part 1 18

19 Datapath Represetatio Have looked at detailed desig of ALU ad shifter i the datapath i slide 8 Here we move up oe level i the hierarchy from that datapath The registers, ad the multiplexer, decoder, ad eable hardware for accessig them become a register file The ALU, shifter, Mux F ad status hardware become a fuctio uit The remaiig muxes ad buses which hadle data trasfers are at the ew level of the hierarchy Costat i MB select FS V C N Z m m 4 D data Write D address 2 m x Register file A address A data A Bus A B address B data Fuctio uit F 1 0 MUX B Bus B B m Address out Data out Data i MD select 0 1 MUX D Chapter 10 Part 1 19

20 Datapath Represetatio (cotiued) I the register file: Multiplexer select iputs become A address ad B address Decoder iput becomes D address Multiplexer outputs become A data ad B data Iput data to the registers becomes D data Load eable becomes write The register file ow appears like a memory based o clocked flipflops (the clock is ot show) The fuctio uit labelig is quite straightforward except for FS Costat i MB select FS V C N Z m m 4 D data Write D address 2 m x Register file A address A data A Bus A B address B data Fuctio uit F 1 0 MUX B Bus B B m Address out Data out Data i MD select 0 1 MUX D Chapter 10 Part 1 20

21 Defiitio of Fuctio Uit Select (FS) Codes G Select, H Select, ad MF i T of FS Codes FS(3:0) MF Select G Select(3:0) H Select(3:0) Microoperatio XX XX XX XX XX XX XX XX X00 XX X01 XX X10 XX X11 XX XXXX XXXX XXXX 10 F A F A + 1 F A + B F A + B + 1 F A + B F A + B + 1 F A 1 F A F A B F A B F A B F A F B F sr B F sl B Boolea Equatios: MFS = F 3 F 2 GS i = F i HS i = F i Chapter 10 Part 1 21

22 The Cotrol Word The datapath has may cotrol iputs The sigals drivig these iputs ca be defied ad orgaized ito a cotrol word To execute a microistructio, we apply cotrol word values for a clock cycle. For most microoperatios, the positive edge of the clock cycle is eeded to perform the register load The datapath cotrol word format ad the field defiitios are show o the ext slide Chapter 10 Part 1 22

23 The Cotrol Word Fields DA AA BA M B FS M D R W Fields DA D Address AA A Address BA B Address MB Mux B FS Fuctio Select MD Mux D RW Register Write Cotrol word The coectios to datapath are show i the ext slide Chapter 10 Part 1 23

24 Cotrol Word Block Diagram RW 0 Write D data DA D address 8 x Register file AA A address A data B address B data BA Costat i MB 6 Bus A 1 0 MUX B Bus B Address out Data out A B V C N Z Fuctio uit 4 FS Data i MD MUX D Bus D Chapter 10 Part 1 24

25 Cotrol Word Ecodig Ecodig of Cotrol W DA, AA, BA MB FS MD RW Fuctio Code Fuctio Code Fuctio Code Fuctio Code Fuctio Code R0 000 Register 0 F A 0000 Fuctio 0 No write 0 R1 001 Costat 1 F A Data I 1 Write 1 R2 010 F A + B 0010 R3 011 F A + B R4 100 F A + B 0100 R5 101 F A + B R6 110 F A R7 111 F A 0111 F A B 1000 F A B 1001 F A B 1010 F A 1011 F B 1100 F sr B 1101 F sl B 1110 Chapter 10 Part 1 25

26 Microoperatios for the Datapath - Symbolic Represetatio Microoperatio DA AA BA MB FS MD RW R1 R 2 R 3 R1 R2 R3 Register F = A + B + 1 Fuctio Write R4 sl R6 R4 R6 Register F = sl B Fuctio Write R7 R R7 R7 Re gister F = A + 1 Fuctio Write R1 R R1 R0 Co stat F = A + B Fuc tio Write Data out R 3 R3 Register No Write R4 Data i R4 Data i Write R5 0 R5 R0 R0 Register F = A B Fuctio Write Chapter 10 Part 1 26

27 Microoperatios for the Datapath - Biary Represetatio m Microoperatios from Ta Biary Co o Microoperatio DA AA BA MB FS MD RW R 1 R 2 R 3 R 4 sl R6 R 7 R R 1 R Data out R 3 R 4 Data i R XXX XXX XXX XXX XXX XXXX X XXX XXX X XXXX Results of simulatio of the above o the ext slide Chapter 10 Part 1 27

28 Datapath Simulatio clock DA AA BA FS Costat_i X 2 X MB Address_out Data_out Data_i MD RW reg0 0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 Status_bits X Chapter 10 Part 1 28

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