INSTITUTE OF BUSINESS ADMINISTRATION, KARACHI Digital Logic Design (CSE-241) Laboratory Manual LAB # 17 Synchronous Counters
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1 INSTITUTE OF BUSINESS ADMINISTRATION, KARACHI Digital Logic Design (CSE-241) Laboratory Manual LAB # 17 Synchronous Counters Objective: The aim of this experiment is to understand the working of Synchronous Counters using Flip-Flops Equipment: 1. One- Single Polarity Variable DC Power Supply 2. Digital Oscilloscope 3. Digital Function Generator 4. Logic Probe Components: 1. Two-74LS76 JK-Flip-Flop 2. One- Quadruple 2-input AND gate, 74LS08 3. Switches 4. One- Bread Board Note: Do consult the data sheets before connecting you ICs THEORY: SYNCHRONOUS COUNTERS: In a synchronous counter, also known as a parallel counter, all the flip-flops in the counter change state at the same time in synchronism with the input clock signal. The clock signal in this case is simultaneously applied to the clock inputs of all the flip-flops. The delay involved in this case is equal to the propagation delay of one flip-flop only, irrespective of the number of flip-flops used to construct the counter. In other words, the delay is independent of the size of the counter. Faculty of Computer Science Page 1
2 2-Bit Synchronous Binary Counter: A 2-bit synchronous binary counter is shown in the following figure. Notice that this 2-bit counter is different from the 2-bit Asynchronous counter as both the flip-flops are clocked by the external clock source. The basic working of the 2-bit synchronous counter can be easily understood by the following timing diagrams. Assume that the counter is initially in the binary 0 state: Notice that in the complete timing diagram for the counter, all the waveform transitions appear coincident; that is, the propagation delays are not indicated. Although the delays are an important factor in the synchronous counter operation, in an overall timing diagram they are normally omitted for simplicity. Major waveform relationships resulting from the normal operation of a circuit can be conveyed completely without showing small delay and timing differences. However, in high speed digital circuits, these small delays are an important consideration in design and troubleshooting. Faculty of Computer Science Page 2
3 3-Bit Synchronous Binary Counter: Paying close attention to the circuit and the timing diagram of the above counter tells us that the operation of the first two stages of the counter is similar to the 2-bit synchronous counter. Next, let s see how FF2 is made to change at the proper times according to the binary sequence. Notice that both times Q2 changes states, it is preceded by the unique condition in which both Q0 and Q1 are HIGH. This conditions is detected by the AND gate and applied to the J2 and K2 inputs of FF2. whenever both Q0 and Q1 are HIGH, the output of the AND gate makes the both the inputs of FF2 high which Faculty of Computer Science Page 3
4 makes FF2 toggle on the following clock pulse. During the remaining time the AND gate keeps both the inputs of FF2 low keeping it in no change condition. 4-Bit Synchronous Binary Counter: The first three states work same as the 3-Bit Synchronous counter. The fourth state, FF3, changes only twice in the sequence. Notice that both of these transitions occur following the time that Q0, Q1 and Q2 are all HIGH. This condition is decoded by AND gate G2 so that when a clock pulse occurs, FF3 will change state. For all the other times it will remain in no change state. Faculty of Computer Science Page 4
5 4-Bit Synchronous Decade Counter: A four-bit counter would have 16 states. By skipping any of the six states by using some kind of feedback or some kind of additional logic, we can convert a normal four-bit binary counter into a decade counter. A decade counter does not necessarily count from 0000 to It could even count as 0000, 0001, 0010, 0101, 0110, 1001, 1010, 1100, 1101, 1111, In this count sequence, we have skipped 0011, 0100, 0111, 1000, 1011 and Faculty of Computer Science Page 5
6 Task 1: Construct a 3-bit Synchronous counter (not on MultiSim) using the figure given in the above description. o Verify the correct operation using oscilloscope. Task 2: Construct a 4-bit Synchronous counter (in MultiSim) from the figure above. o Use the logic analyzer provided in MultiSim to observe all the outputs simultaneously, and verify correct operation. Task 3: Edit your circuit from Task2 making it an octal counter which terminates after 8 states (you could use the above decade counter description for your help). o Verify correct operation o Again use logic analyzer to observe all the outputs simultaneously. Faculty of Computer Science Page 6
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