EC1261 DIGITAL LOGIC CIRCUITS UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A 1. What do you mean by literal? 2. What is logic gate? 3.

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1 EC1261 DIGITAL LOGIC CIRCUITS UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A 1. What do you mean by literal? 2. What is logic gate? 3. What is demultiplexer? How does it differ from a decoder? 4. Find the dual of the expression xy +y = x+y. 5. Realize the function Y= m(1,4,6) using suitable decoder. 6. Give an application for XOR function. 7. Convert the binary [ ] 2 into its Gray code. 8. Show that A (A+B) = A. 9. Simplify (A +AB) where A and B are Boolean variables. 10. Draw a 2 to 1 multiplexer. 11. Express the function f(a,b,c) = a b+c as a canonical product of sum form 12. Implement Y = ABCD using two input Nand gates. 13. Implement 8:1 MUX using 4:1 MUX. 14. Simplify X+X Y 15. What is Decoder? 16. Why NAND and NOR gates are called as universal gates? 17. Define edge triggering. 18. Draw a circuit using the same type of logic gates to test for odd number of 1 s in a binary number. 19. Simplify ab+bc +cd+bd +bc. 20. Give the half adder circuit and its truth table. 21. Give an application of exclusive OR gate. 22. Give an application for 2 to 1 multiplexers. 23. Show the NOR implementation of the Logic function Y = AB + CD + E. 24. What are prime implicants? 25. Define multiplexer? 26. What is the significance of a master slave flip-flop? 27. Distinguish between Decoders and Encoders.

2 28. Define min terms with an example. 29. Specify the use of Multiplexers. 30. Implement Y = AB +A B using NOR Gate only. 31. Design half subtractor using NANO Gate only. 32. State and prove Demorgan s theorem. 33. Give the canonical product form of f = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x Simplify using k-map. Y = AC+BC+ABC+AB 35. Simplify using K map Y = (P+Q+R) (P+Q+R) (P+Q+R) (3) PART-B 1. Minimize F(A,B,C,D) = Σ(0,1,2,3,4,6,7,8,12,13) using K map. 2. Simplify Σ m(8,9,10,11,13,15,16,18,21,24,25,26,27,30,31) using tabulation method. 3. Design a logic circuit for BCD to XS Design a logic circuit for 4 bit magnitude comparator. 5. Minimize the following Boolean function using Quine-Mccluskey method F(x 1,x 2,x 3,x 4,x 5,x 6 )= Σm (0,2,4,6,7,8,10,11,12,13,14,16,18,19,29,30) 6. Minimize y(a,b,c,d)= π M(1,2,4,9,11) using k-map. (ii) State and prove Demorgan s Theorems. 7. Design a logic circuit to convert excess-3 to 8421 BCD 8. Design full subtractor using NAND gate only. 9. Design and realize full adder,1-4 MUX 10. Design a decoder circuit which display the output of a decade counter on 7 segment display. 11. Design a combinational circuit that converts a decimal digit from BCD to Excess 3 code. 12. Design a full Subractor with gates. 13. Simplify the following using K-map and realize the reduced function using NAND gates. m(0, 1, 3, 5, 6, 8, 9, 14, 26, 28, 31) + d(4, 13). 14. Simplify the following Quine MCcluskey method and realize the reduced function using NAND gates. m(1, 2, 4, 5, 7, 9, 12, 13) + d(3, 8). 15. Design the following circuits. (i) Full adder (ii) 1-4 demultiplexer. 16. Implement the following function using a multiplexer F(A,B,C) = (1,3,5,6).

3 17. Design a 3-to-8 decoder. UNIT II SYNCHRONOUS SEQUENTIAL CIRCUITS PART-A 1. Give the excitation table of a T flip-flop. 2. Distinguish between a Mealy and Moore finite state machine? 3. What is the number of states in a 4 bit Johnson counter? 4. How many flip-flops are needed to realize a mod-16 counter? 5. State the problem normally encountered in SR flip-flop. 6. State the difference between combinational and sequential circuits. 7. Realize a D flip-flop using SR flip-flop. 8. What does state diagram represent? 9. What is meant by triggering? 10. How will you build a D flip-flop from a given JK flip-flop? 11. When is a counter said to suffer from lockout? 12. Why state reduction in necessary in sequential circuits. 13. Compare Mealy and Moore synchronous sequential circuits. 14. What is stable and unstable states? 15. Explain race condition. 16. What is ring counter? 17. What is the other name for flip-flop? 18. Write the truth tables of D and T flip flops. 19. Give the logic diagram of D flip-flop using NAND gates. 20. Give the excitation table of a JK flip-flop. 21. Give the excitation table of a SR flip-flop. 22. Give the excitation table of a D flip-flop. 23. Define state of a Logic circuit. 24. What is state diagram? 25. Mention some application of shift register? 26. What is synchronous sequential circuit? 27. Compare Moore and Mealy models. 28. What is lockout? How it is avoided?

4 PART-B 1. Draw the state table, derive the characteristic equation and draw the circuit for the following state diagram using T flip flops. 2. Reduce the state diagram given below giving reduced state table and diagram. 3. Design a synchronous 3 bit up-down counter using D flip-flop. 4. A sequential circuit with two D flip-flops A and B, two inputs X and Y, one output Z is specified by the following next state and output equations. A(t+1) = x Y + xa, B(t+1) = x B + xa, Z = B i) Draw the logic diagram of the circuit. ii) Derive the state table. iii) Derive the state diagram. 5. Design a 3 bit Binary counter using T flip flop. 6. Explain the procedure for designing synchronous sequential circuits.

5 7. A sequential circuit has one input and one output, Minimize the following state table and then design the sequential circuit with T flip-flops. NS,Z PS X = 0 X=1 A A,0 D,1 B C,1 D,0 C B,0 A,1 D D,1 A,1 E D,1 A,1 F D,0 A,0 G D,1 A,1 H D,1 C,1 8. Implement JK-FF using NAND Gate only. 9. Design 4 bit ripple down counter and explain timing diagrams. 10. What are completely specified and incompletely specified sequential machines. 11. Explain design procedure for synchronous sequential circuit with an example. 12. A sequential circuit has four FFs ABCD and an input x is described by the following state equations. A(t+1) = (CD +C D)x+(CD+C D )x B(t+1) = A, B(t+1) = B, D(t+1) = C, Z = B a. Obtain the sequence of states when x=1 starting from state ABCD = b. Obtain the sequence of states when x=0 starting from state ABCD = Explain the working of JK flip-flop. What is race around condition and how is it overcome? Explain these concepts with relevant timing diagrams. 14. Derive the characteristic equation of a SR flip-flop. 15. Derive the input and output action of JK master/slave flip-flops. 16. Realize a JK flip-flop using only NOR gates. 17. Realize SR flip-flop using NOR gates and explain its operation. 18. Realize a SR flip-flop using NAND gates and explain its operation. 19. Explain the operation of JK master slave flip-flop with suitable diagrams. 20. Design a 3 bit synchronous gray code counter using T flip-flop. 21. Design a synchronous 3 bit gray code up counter with help of excitation table.

6 UNIT III ASYNCHRONOUS SEQUENCTIAL CIRCUIT PART-A 1. Sate the fundamental mode of operation in asynchronous sequential circuit? 2. Explain the pulse mode asynchronous sequential circuit? 3. What are the steps for the analysis of asynchronous sequential circuit? 4. What are the steps for the design of asynchronous sequential circuit? 5. What is the significance of the state assignment? 6. List the different techniques used for state assignment. 7. What are races and cycles? 8. Define critical and noncritical race. 9. Write a short note on Shared row state assignment. 10. Write a short note on Shared one hot state assignment. 11. Distinguish between a synchronous and asynchronous sequential circuit. 12. What is an asynchronous sequential circuit? 13. When does race condition arise in asynchronous sequential circuit? 14. What are fundamental mode circuits? 15. Why are asynchronous counters referred to as ripple counters? 16. List one advantage and one disadvantage of synthesizing asynchronous sequential circuits. 17. Define the purpose of Flow Table. 18. How does the operation of an asynchronous input differ from that of a synchronous input? 19. Define the Transition Table. 20. What is the difference between state table and transition table. PART-B 1. What are races and cycles in asynchronous sequential circuits. Explain a method for race free assignment with an example. 2. Design an asynchronous sequential circuit with 2 inputs x 1, x 2 and one output z. When x 1 = 0, z = 0, the first change in x 2 that occurs while x 1 =1 will cause output z = 1.output z will remain 1 until x1 returns to 0.

7 3. Develop the state diagram and primitive flow table for a logic system that has two inputs S and R and a single output Q. the device is to be an edge triggered SR flipflop but without a clock. The device changes state on the rising edges of the two inputs. Static input values are not to have any effect in changing the Q output. 4. Obtain the primitive flow table for an asynchronous circuit that has two inputs, x, y and one output z. An output z = 1 is to occur only during the input state xy = 01 and then if the only if the input state xy = 01 is preceded by the input sequence. Xy = 01, 00, 10, 00, 10, Design a T flip-flop from logic gates. 6. Obtain the primitive flow table for a circuit with two inputs x 1 and x 2 and two outputs z 1 and z 2 that satisfies the following four conditions. (i) When x 1 x 2 = 00, output z 1 z 2 = 00. (ii) When x 1 = 1 and x 2 changes from 0 to 1, the output z 1 z 2 = 01. (iii) When x 2 = 1 and x 1 changes from 0 to 1, the output z 1 z 2 = 10. (iv) Otherwise the output does not change. 7. An synchronous sequential circuit has two internal states and one output. The excitation and output function describing the circuit are as follows. 8. An synchronous sequential circuit is described by the following excitation and output function. 9. Design an asynchronous sequential circuit with 2 inputs x and y and with one output z. Whenever Y is 1, input s transferred to Z. When Y is 0, the output does not change for any change in x. 10. Design a pulse mode circuit having 2 input line x 1, x 2 and one output z. The circuit should product an output pulse to coincide with the last input pulse in the sequence x 1 x 2 x 2. No other input sequence should produce an output pulse.

8 UNTI IV PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC FAMILIES 2 PART-A 1. Distinguish between a PAL and PLA. 2. What is FPGA? 3. Whether PAL is same as PLA? Explain. 4. What is PLA? 5. How does the architecture of a PLA differ from a PROM? 6. Define memory cell. Give an example. 7. Define a memory location and a cell. 8. What is volatile memory? Give example. 9. Define rise time and fall time. 10. Write a short note on propagation delay. 11. Define the following parameters a) fan-in b) Fan-out. 12. What is noise margin? 13. What is Power dissipation? 14. Define speed power product. 15. State advantages and disadvantages of totem-pole output. 16. Describe the characteristics of TTL family. 17. Explain Wired-AND Connection. 18. Give the comparison between TTL, CMOS and ECL families. 19. List the advantages of ECL as compared to TTL logic family. 20. Draw the circuit of a CMOS two input NAND gate and explain its operation. 21. Distinguish between 7400 series and 5400 series. 22. Classify the basic families that belong to the families and to the MOs families. 23. What is the major difference between ECL and TTL? 24. Why does the propagation delay occur in logic circuits? 25. Differentiate: Source and sink current. 26. Give any two applications of open collector logic. 27. What is faster TTL or ECL? Which requires more power to operate?

9 28. What is the effect of increasing the supply voltage on the propagation delay of the CMOS gates? PART-B 1. Write a descriptive note on memories. 2. Discuss on the concept of working and applications o following memories: i) ROM ii) EPROM. Iii) PLA. 3. Explain the characteristics and implementation of the following digital logic families. i) CMOS. Ii) ECL. 4. Compare various logic families in detail 5. Explain about memory decoding. 6. Design 2 input TTL NAND Gate 7. Design 3 input CMOS NAND Gate. 8. With neat sketch explain about FPGA Architecture. 9. Name and explain the characteristics of TTL fami;y. 10. Draw and explain the circuit diagram of a CMOS NOR gate. 11. Draw the circuit of TTL NAND gate and explain its operation. 12. Draw the TTL inverter circuit. 13. Discuss about the TTL parameters. 14. Draw the circuit of a CMOS two input NAND gate and explain its operation. 15. A combinational logic circuit is defined by the following function, f 1 (a,b,c) = (0,1,6,7), f 2 (a,b,c) = (2,3,5,7). Implement the circuit with a PAL having three inputs, three product terms and two outputs. 16. A combinational circuit is defined by the following function, f 1 (a,b,c) = (3,5,6,7), f 2 (a,b,c) = (0,2,4,7). Implement the circuit with PLA. 17. Using ROM, design a combinational circuit with accepts 3 bit number and generates an output binary number equivalent to square of input number.

10 UNIT V VHDL PART-A 1. What are the logical and relational operation available in VHDL? 2. Differentiate between data flow modeling and structural modeling in VHDL. 3. Write the VHDL code for NAND gate. 4. What is HDL? 5. What is VHDL? 6. What is VHSIC? 7. Write the program for AND gate in VHDL? 8. What are the various operators in VHDL? 9. What are the data types available in VHDL? 10. What are the types of subprogram? 11. What is the use of actual? 12. Write the syntax of procedure body? 13. What is test bench? 14. What are the two methods to generate stimulus values? 15. What do you mean by concurrent statement? 16. Explain WITH SELECT statement with example. 17. Explain WHEN statement with example? 18. Write a note on: Implementation of logic function. 19. What do you mean by functional simulation and timing simulation? 20. What is package in VHDL? 21. What is package Body? Give Example. 22. Explain Process statement with example. 23. Explain CASE statement with example. 24. Explain IF statement with example. 25. What do you mean by variable in VHDL? PART-B 1. Explain about operators and data types in VHDL.

11 2. Write short notes on packages and subprograms. 3. Write VHDL program for encoder. 4. Write VHDL program for T flipflop. 5. Write VHDL program for Gray to Binary conversion. 6. Explain about test bench. 7. Write a VHDL code for a) 3:8 Decoder b)16 bit adder 8. Write a VHDL code for a) 8:1 Multiplexer b)2 bit comparator 9. Write VHDL behavioral and structural code that represents a D-Latch. 10. Write VHDL behavioral and structural code that represents a) a Postive-edge triggered D-flipflop with asynchronous reset b) a Postive-edge triggered D-flipflop with synchronous reset. 11. Write a VHDL code for a four-bit register. 12. Write a VHDL code for an n-bit register. 13. Write VHDL code for a serial adder using Moore-type FSM. 14. Write VHDL code for a serial adder using Mealy-type FSM. 15. Write behavioral VHDL code that represents an eight-bit Johnson counter. 16. Write behavioral VHDL code that represents an n-bit right counter. 17. Write VHDL code for a 4-bit parallel access left-to-right shift register.