Digital Systems Laboratory

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1 Eskişehir Osmangazi University Digital Systems Laboratory Rev 3.01 February 2011

2 LIST OF EXPERIMENTS 1. BINARY AND DECIMAL NUMBERS 2. DIGITAL LOGIC GATES 3. INTRODUCTION TO LOGICWORKS 4. BOOLEAN ALGEBRA 5. CODE CONVERSION 6. ADDERS/SUBTRACTORS 7. MULTIPLEXERS 8. FLIP-FLOPS 9. COUNTERS AND SEQUENTIAL LOGIC 10. LOGIC DESIGN USING VERILOG HDL AND XILINX ISE 11. COMBINATIONAL LOGIC DESIGN WITH GATE LEVEL MODELING IN HDL 12. CENTRAL PROCESSING UNIT There are no laboratory classes for the experiments 2, 3, 4 and 12. Experiment Date 1 28 February-4 March March March March-1 April April April April April

3 Digital Systems Laboratory 2011 LIST OF THE ITEMS REQUIRED FOR THE LAB. 1. Breadboard 2. Integrated Circuits IC Number Description Experiment # Quantity 7400 Quadruple 2-input NAND gates 5,6,8, Quadruple 2-input NOR gates Hex Inverter 5,6,7, Quadruple 2-input AND gates 6, Triple 3-input NAND gate Dual 4-input NAND gates 4 5, Quadruple 2-input OR gates BCD-to-seven segment decoder 5, Dual JK master-slave flip-flop 8, bit binary adder bit magnitude comparator Quadruple 2-input XOR gates 5, bit ripple counter x1 multiplexer Dual 4x1 multiplexer Display Seven-segment LED display, common anode 5,7 1 3

4 Digital Systems Laboratory 2011 LABORATORY REGULATIONS AND SAFETY RULES The following Regulations and Safety Rules must be observed in all concerned laboratory location. 1. It is the duty of all concerned who use any electrical laboratory to take all reasonable steps to safeguard the HEALTH and SAFETY of themselves and all other users and visitors. 2. Be sure that all equipment is properly working before using them for laboratory exercises. Any defective equipment must be reported immediately to the Lab. Instructors or Lab. Technical Staff. 3. Students are allowed to use only the equipment provided in the experiment manual. 4. Power supply terminals connected to any circuit are only energized with the presence of the Instructor or Lab. Staff. 5. Avoid any part of your body to be connected to the energized circuit and ground. 6. Switch off the equipment and disconnect the power supplies from the circuit before leaving the laboratory. 7. Observe cleanliness and proper laboratory house keeping of the equipment and other related accessories. 8. Make sure that the last connection to be made in your circuit is the power supply and first thing to be disconnected is also the power supply. 9. Equipment should not be removed, transferred to any location without permission from the laboratory staff. 10. Students are not allowed to use any equipment without proper orientation and actual hands on equipment operation. 11. Smoking and drinking in the laboratory are not permitted. All these rules and regulations are necessary precaution in Electronic Laboratory to safeguard the students, laboratory staff, the equipment and other laboratory users. 4

5 Digital gates in IC packages with identification numbers and pin assignments 5

6 IC Type 7493 Ripple Counter 6

7 Digital Systems Laboratory 2011 Lab 1: Binary and Decimal Numbers Objective To demonstrate the count sequence of binary number and the binary-coded decimal (BCD) representation. Apparatus bit ripple counter CADET trainer Dual-trace Oscilloscope Procedure Binary Count 1. Turn off the power switch. 2. Connect the IC type 7493 as shown in Fig Turn the power on and observe the four logic indicators/led. The 4-bit number in the out is incremented by one for every pulse generated by pushing the pushbutton. 4. Disconnect the input of the counter at pin 14 and connect it to the Function Generator (lead TTL). 5. Set frequency selector to time 1 (1 Hz). This will provide an automatic binary count. 6. Increase the frequency of the clock to 10 khz or higher and connect its output to an oscilloscope. Observe the clock output on the oscilloscope and sketch its waveform. BCD Count 1. Turn off the power switch. 2. Connect the IC type 7493 as shown in Fig Turn the power on and observe the four logic indicator lamps/leds. The 4-bit number in the indicators is incremented by one for every pulse generated by pushing the pushbutton following the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 1, 2, 3,. 4. Disconnect the input of the counter and connect it to TTL output of the function generator. Set frequency selector to time 1 (1 Hz). This will provide an automatic binary count. Fig. 1 Binary counter Fig. 2 BCD counter 7

8 Other Counts R1 and R2 are the reset inputs of the IC type By connecting one or two outputs to the reset inputs R1 and R2, the counter can count from 0 to a variety of final count. In Figure 2, if R1 is connected to QA instead of QB, the resulting count will be from 0000 to 1000, which is the one less than 1001 (QD=1 and QA=1). Count Binary Resets the counter (R1=QA, R2=QD) Utilizing your knowledge of how R1 and R2 affect the final count, find out which outputs should be connected to the resets inputs to count 0000 to the following counts: a b c Turn of the power switch. 2. Connect the 7493 IC to count from 0 to one of the final counts given above. 3. Verify the count by applying pulses from the pushbuttons and observing the output count in the logic indicators/leds. 8

9 Digital Systems Laboratory 2011 Lab 2 : Digital Logic Gates Objectives To study the basic logic gates: AND, OR, INVERT, NAND, and NOR. To study the representation of these functions by truth tables, logic diagrams and Boolean algebra. To observe the pulse response of logic gates. To measure the propagation delay of logic gates. Apparatus 7400 Quadruple 2-input NAND gates 7402 Quadruple 2-input NOR gates 7404 Hex Inverters (x2) 7408 Quadruple 2-input AND gates 7432 Quadruple 2-input OR gates 7486 Quadruple 2-input XOR gate CADET trainer Dual-trace oscilloscope Theory AND OR INVERT NAND A multi-input circuit in which the output is 1 only if all inputs are 1.The symbolic representation of the AND gate is shown in Fig. 3a. A multi-input circuit in which the output is 1 when any input is 1. The symbolic representation of the OR gate is shown in Fig. 3b. The output is 0 when the input is 1, and the output is 1 when the input is 0. The symbolic representation of an inverter is shown in Fig. 3c. AND followed by INVERT. The symbolic representation of the NAND gate is shown in Fig 3d. NOR OR followed by INVERT as shown in Fig. 3e. EX-OR Truth Table The output of the Exclusive OR gate, is 0 when it s two inputs are the same and it s output is 1 when its two inputs are different, Fig. 3f. Representation of the output logic levels of a logic circuit for every possible combination of levels of the inputs. This is best done by means of a systematic tabulation. a. Two input AND gate b. Two input OR gate c. Inverter 9

10 d. Two input NAND gate e. Two input XOR gate f. Two input NOR gate Part 1: Logic Functions I. AND, OR, NAND, and NOR gates. Fig. 3 Symbols for digital logic gates 1. Use one gate for each IC 7400 (NAND), 7402 (NOR), 7408 (AND), 7432 (OR), 7486 (XOR). Each has input pins, 1 and 2, and output pin Connect pin 1 to switch S1-1, pin 2 to switch S1-2, and pin 3 to LED-1 for every gate as shown in Fig. 4 as an example for the NAND gate. Fig. 4 Two input NAND gate 3. Using logic switches S1-1 and S-2, apply the logic levels 0 and 1 to gate inputs (pin 1, pin 2), in the sequence shown in table 1. Record the output logic levels (see LED-1) in Table 1. Repeat the recordings for each gate. Remember: LED ON = Logic 1, (High) LED OFF = Logic 0 (Low) Table 1 Pin 1 Pin 2 Pin 3 4. Use an inverter gate from IC 7404 whose input pin is pin 1 and whose output pin is pin 2. Fig. 5 Inverter gate 5. Using logic switches S1-1, apply the logic levels 0 and 1 in the sequence shown in Table 2. Record the output logic levels in Table 2. Table 2 Pin 1 Pin

11 Part-2: Response of Logic Gates: Connect the circuits of Fig. 6 and 7 and write the corresponding truth tables 3 and 4, respectively. Fig. 6 Fig. 7 Table 3 Table 4 A B C D E A B C D Part 3: Propagation Delay in Logic Gates: Connect all inverters inside two 7404 ICs in cascade. The output will be the same as the input except that it will be delayed by the time it takes the signal to propagate through all six inverters. Set S2 to 100 khz and apply clock pulses to the input of the first inverter (connect pin 1 to j14) record the wave forms and determine the time delay from the input to the sixth inverter. This is done with a dual trace oscilloscope by applying the input clock pulses to one of the channels and the output of the sixth inverter to the second channel and measuring the delay between the two signals as shown in Fig 8. By using measured delay between two signals calculate the propagation delay for each inverter gate. Fig. 8 Propagation delay 11

12 Part 4: Review Questions: 1. Write a truth table for each circuit. Derive Boolean expressions for all outputs. 2. A burglar alarm for a car has a normally low switch on each of four doors. If any door is opened the output of that switch goes HIGH. The alarm is set off with an active-low output signal. What type of gate will provide this logic? Support your answer with an explanation. 12

13 Digital Systems Laboratory 2011 Lab 3 : Introduction to LogicWorks LogicWorks Tutorial is available at the web page. 13

14 Digital Systems Laboratory 2011 Lab 4 : Boolean Algebra Objectives To verify the rules and regulations of Boolean Algebra To simplify and modify Boolean logic functions by means of Demorgan s theorem. To design and implement a logic circuit. Apparatus 7400 Quadruple 2 input NAND gates Quadruple 2 input NOR gates 7408 Quadruple 2 input AND gates 7432 Quadruple 2 input OR gates 7404 Hex inverters 7411 Triple 3-input AND gate CADET LogicWorks or Proteus can be used in the digital circuit simulations. Theory (See chapter 2 of the textbook) 1. A+0 = A 2. A+1 = 1 3. A.0 = 0 4. A.1 = A 5. A+A = A 6. A+A = 1 7. A.A = A 8. A.A = 0 9. (A ) = A 10. A+AB = A 11. A+A B = A+B 12. (A+B)(A+C) = A+BC 13. A. B = (A+B) 14. A +B = (A.B) Procedure 1 a. Prove rule 1 using LogicWorks. The procedure is: I. Open a new design window II. Choose ALL LIBRARY in the Parts Palette III. Put OR in the Filter window IV. Select and double click on OR-2 V. Move to the cursor back into the circuit window. The cursor on the screen will now be replaced by a moving image of an OR gate. VI. Position the OR gate near the center of the circuit window and click the mouse button. VII. Press the spacebar to return to point mode. VIII. Move again to the Parts Palette and type on the Filter switch or part of the word switch e.g. sw. IX. Select Binary switch and connect it to an input of the OR gate in the design window. (If you want to move the binary switch around, press the shift key while moving it). X. Move again to the Parts Palette and select ground to be connected to the other input of the OR gate. 14

15 XI. Using the same method get a Binary Probe and connect it to the output of the OR gate XII. Click on the binary switch to change it between 0 and 1 and notice how the rule A+0 = A is satisfied. In the lab connect the circuit as shown in the figure using the switch S1-1 and LED-1 to verify the rule. Fig.9 Verifying Rule 1 b. Connect the circuit of Fig.10 in LogicWorks. Which rule does this circuit illustrate? Fig.10 In the lab connect the circuit as shown in the figure using the switch S1-1 and LED-1 to verify the rule. c. Design a circuit that illustrates rule 10. Use clock generator of the CADET for A and one of the logic switches of S1 for B. Copy the circuit from LogicWorks and paste it in your lab report. d. Rule 6 illustrates that A+A could be replaced with a wire to Vcc. What does rule 8 illustrate? e. Rule 11 states that A+A B = A+B. Using LogicWorks design a circuit that illustrates each of these expressions. A+A B A+B Prove that these two circuits perform equivalent logic. (Connect two circuits and show that their outputs are the same). Procedure 2: Demorgan s Theorem Proof of equation (1) Using LogicWorks construct the two circuits given in Fig. 11 and 12 corresponding to the functions A. B and (A+B) respectively. Show that for all combinations of A and B, the two circuits give identical results. 15

16 Fig.11 Fig.12 Proof of equation (2) Using LogicWorks construct two circuits given in Figs. 13 and 14, corresponding to the functions A +B and (A.B) A.B, respectively. Show that, for all combinations of A and B, the two circuits give identical results. In the lab connect these circuits and verify their operations. II. Design of a Digital Circuit Consider the following problem: Fig. 13 Fig. 14 Four chairs A, B, C, and D are placed in a row. Each chair may be occupied ( 1 ) or empty ( 0 ). A Boolean function F is 1 if and only if there are two or more adjacent chairs that are empty. 1. Give the truth table defining the Boolean function F 2. Express F as a minterm expansion (standard sum of product) 3. Express F as a maxterm expansion (standard product of sum) 4. Using postulates and theorems of Boolean algebra, simplify the minterm expansion of F to a form with as few occurrences of each as possible. 5. Implement the simplified Boolean function with logic gates on LogicWorks and check the operation of the circuit. Notes: - In LogicWorks use Binary Switches to represent the four chairs and connect the output of the circuit to a Binary Probe. Check that the Probe is 1 if and only if there are two or more adjacent chairs that are empty. - For the hardware circuit in the lab, use logic switches S1-1, S1-2, S1-3, and S1-4 to represent the chairs and connect the output of the circuit to LED-1 16

17 Digital Systems Laboratory 2011 Lab 5 : Code Conversion Objectives Design and build gray code to binary converter. Design and build BCD-to-7 segment converter. Apparatus Seven segment display, common anode (CA) quad 2-input NAND gates 7410 triple 3-input NAND gates 7420 dual 4-input NAND gates 7404 HEX inverter 7486 EX-OR gate 7447 BCD-to-seven segment decoder. LogicWorks or Proteus can be used in the digital circuit simulations. Theory The conversion from one code to another is common in digital systems. Sometimes the output of a system is used as the input to the other system. A conversion circuit is necessary between two systems if each system uses different codes for the same information. In this experiment you will design and construct 3-combinational circuit converters. PreLab Questions 1. Gray code to Binary converter Design a combinational circuit with 4 inputs and 4 outputs that converts a four-bit gray code number (Table 2) into an equivalent four-bit Binary number. Use Karnaugh map technique for simplification. 2. BCD-to-seven Segment converter Design a combinational circuit which would simulate the BCD-to-seven Segment decoder function for only the segment a, of the display. This can be done in the following steps: a. Write down the truth table with 4 inputs and 7 outputs (Table 5) Table 5 Dec. BCD Outputs A B C D A b c d e f g

18 b. For only the output a, obtain a minimum logic function. Realize this function using NAND gates and inverters only. For example if decimal 9 is to be displayed a, b, c, d, f, g must be 0 and the others must be 1 (For common anode type display units), if decimal 5 is to be displayed then a, f, g, c, d must be 0 and the others must be 1. Procedure: 1. Gray code to Binary converter: Gray code is one of the codes used in digital systems. It has the advantage over binary numbers that only one bit in the code word changes when going from one number to the next. (See Table 2). Construct the circuit (PreLab Q.1) and verify its operations. Table 6 Fig. 15 XOR chip 7486 Decimal Gray Binary BCD-to-seven Segment converter: A light emitting Diode (LED) is a PN junction diode. When the diode is forward biased, a current flows through the junction and the light is emitted. See Fig.16. Fig. 16 A seven segment LED display contains 7 LEDs. Each LED is called a segment and they are identified as (a, b, c, d, e, f, g) segments Fig

19 Fig. 17 Decimal digits represented by the 7 segments The display has 7 inputs each connected to an LED segment. All anodes of LEDs are tied together and joined to 5 volts (this type is called common anode type). A current limiting resistance network must be used at the inputs to protect the 7-segment from overloading. BCD inputs are converted into 7 segment inputs (a, b, c, d, e, f, g) by using a decoder, as shown in Fig.18. Fig. 18 A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n output lines. The input to the decoder is a BCD code and the outputs of the systems are the seven segments a, b, c, d, e, f, and g. For further information and pin connections, consult the specification sheet for decoder and 7-segment units. The 7447 BCD-to-seven segment decoder is used to drive a seven-segment LED display. The outputs, a- g, drive the corresponding segments on the seven-segment display according to the binary number present at the inputs A-D, D being the most significant bit of the number. Three additional inputs, LAMP TEST, BI/RBO, and RBI are provided. The blanking input/ripple-blanking output (BI/RBO) blanks (turns off) the display when set LOW. Otherwise, when BI/RBO is set high, the outputs drive the display according to the inputs A-D. The ripple blanking input (RBI) must be HIGH if blanking of a decimal zero is not desired. This input is useful in blanking higher order zeroes when using several displays for a multidigit decimal number. Finally, LAMP TEST selects (turns on) all the segments when set LOW. It is used to test the segments on the display. a. Construct the combinational circuit (PreLab Q.2) which will simulate the decoder function for only the segment a, of the display. b. Connect the output a of your circuit to appropriate input of 7-segment display unit through a current limiting resistor, 330/470 Ω. By applying BCD codes verify the displayed decimal digits for that segment for a of the display. c. Replace your circuit by a decoder IC 7447 for all of the seven segments. Use current limiting resistors at the inputs of the seven-segment display. Observe the display and record the segments that will light up for invalid inputs sequence. d. Comment on the design if you don t want to see any digit for invalid input sequence. 19

20 BCD-to-Seven Segment Decoder and 7-segment display 20

21 Digital Systems Laboratory 2011 Lab 6 : Adders/Subtractors Objectives To construct and test various adders and subtractor circuits. To construct and test a magnitude comparator circuit. Apparatus 7486 quad 2-input XOR gates 7400 quad 2-input NAND gates 7404 Hex inverter 7408 Quadruple 2 input AND gates 7420 dual 4-input NAND gates bit binary adder bit magnitude comparator. LogicWorks or Proteus can be used in the digital circuit simulations. Addition IC type 7483 is a 4-bit binary adder with fast carry. The pin assignment is shown in Fig 19. The two 4-bit input binary numbers are A1 through A4 and B1 through B4. The 4-bit sum is obtained from S1 through S4. Ci is the input carry and Co is the out carry. This IC can be used as an adder-subtractor as a magnitude comparator. Fig. 19 IC type bit adder. 21

22 Subtraction The subtraction of two binary numbers can be done by taking the 2 s complement of the subtrahend and adding it to the minuend. The 2 s complement can be obtained by taking the 1 s complement and adding 1. To perform A - B, we complement the four bits of B, add them to the four bits of A, and add 1 to the input carry. This is done as shown in Fig 2. Four XOR gates complement the bits of B when the mode select M = 1 (because x.1=x ) and leave the bits of B unchanged when M = 0 (because x.0=x) thus, when the mode select M is equal to 1, the input carry Ci is equal to 1 and the sum output is A plus the 2 s complement of B. When M is equal to 0, the input carry is equal to 0 and the sum generates A + B. Magnitude comparison The comparison of two numbers is an operation that determines whether one number is greater than, equal to, or less than the other number. Fig bit adder/subtractor The IC 7485 is a 4 bit magnitude comparator. It compares two 4-Bit binary numbers (labeled as A and B) generates an output of 1 at one of three outputs labeled A > B, A < B, A = B. Three inputs are available for cascading comparators. See Fig.21. PreLab Questions: 1. a. Design using LogicWorks a half adder circuit using only XOR gates and NAND gates. Then during the Lab construct the circuit and verify its operation. b. Design using LogicWorks a full adder circuit using only XOR gates and NAND gates. Then during the Lab construct the circuit and verify its operation. 2. A magnitude comparator can be constructed by using a subtractor as in Fig 20. and an additional combinational circuit. This is done with a combinational circuit which has 5 inputs S1, S2, S3, S4, and Co, and three outputs X, Y, Z see Fig.22. X = 1 if A = B where S = 0000 Y = 1 if A < B where Co = 0 Z = 1 if A > B where Co = 1 S

23 Design this logic circuit with minimum number of gates. Procedure: a. Construct the circuit of PreLab 1(a) and verify its operation. b. Construct the circuit of PreLab 1(b) and verify its operation. c. Use IC 7483 to add the two 4-bit numbers A and B shown in Table 7. Table 7 A3 A2 A1 A0 B3 B2 B1 B0 Sum Carry Out Input carry Ci is taken as logic 0. Show that if the input carry is 1, it adds 1 to the output sum. In the Lab use the logic switches S1-1 to S1-8 for the two numbers and use the SPDT (Single-Pole Double Throw) switch S1 for the input carry Ci. For sum and carry out, use LED-1 to LED-5. d. Connect the adder-subtractor circuit as shown in Fig 20. Perform the following operations and record the values of the output sum and the output carry Co. Table 8 Decimal A B Sum Carry Out C0 Show that Co =1 when sum exceeds 15. Comment on sum and Co for the subtraction operations when A > B and A < B. e. Use IC7485 to compare the following two 4 bit numbers A and B. Record the outputs in Table 9. Table 9 A B Outputs

24 Fig bit magnitude comparator. f. Construct the magnitude comparator of Fig. 22. The design of the logic circuit is described in PreLab Q2. Check the comparator action using part (e). Fig. 22 A magnitude comparator using a subtractor. 24

25 Digital Systems Laboratory 2011 Lab 7 : Design with Multiplexers Objectives To design a combinational circuit and implement it with multiplexers. To use a demultiplexer to implement a multiple output combinational circuit from the same input variables. Apparatus 7404 HEX inverter x1 multiplexer dual 4x1 multiplexer (x2) 7447 BCD-to-Seven-Segment decoder Seven-Segment Display LogicWorks or Proteus can be used in the digital circuit simulations. PreLab Questions: Design the circuits described in Part 1 and Part 2. IC Description: is a 8 line-to-1 line multiplexer. It has the schematic representation shown in Fig 23. Selection lines S2, S1 and S0 select the particular input to be multiplexed and applied to the output. Strobe S acts as an enable signal. If strobe =1, the chip is disabled and output y = 0. If strobe = 0 then the chip is enabled and functions as a multiplexer. Table 10 shows the multiplex function of in terms of select lines. Table 10 Strobe Select Output Lines S S2 S1 S0 Y 1 X X X D D D D D D D D7 Fig. 23 IC type Multiplexer is a dual 4 line-to-1 line multiplexer. It has the schematic representation shown in Fig 24. Selection lines S1 and S0 select the particular input to be multiplexed and applied to the output IY{1 = 1, 2}. 25

26 Each of the strobe signals IG {I = 1, 2} acts as an enable signal for the corresponding multiplexer. Table 11 shows the multiplex function of in terms of select lines. Note that each of the on-chip multiplexers act independently from the other, while sharing the same select lines S1 and S0. Multiplexer 1 Strobe Select lines Output 1G S1 S0 1Y 1 X X D D D D3 Table 11 Multiplexer 2 Strobe Select lines Output 2G S1 S0 2Y 1 X X D D D D3 Fig. 24 Chip IC 7447 is a BCD to seven segment decoder driver. It is used to convert the combinational circuit outputs in BCD forms into 7 segment digits for the 7 segment LED display units. See Lab. 5. Procedure: Part I: Parity Generator: a. Design a parity generator by using a multiplexer. Parity is an extra bit attached to a code to check that the code has been received correctly. Odd parity bit means that the number of 1 s in the code including the parity bit is an odd number. Fill the output column of the truth table in Table 12 for a 5-bit code in which four of the bits (A, B, C, D) represents the information to be sent and fifth bit (x), represents the parity bit. The required parity is an odd parity. The inputs B, C and D correspond to the select inputs of Complete the truth table in Table 12 by filling in the last column with 0, 1, A or A. b. Simulate the circuit using LogicWorks, use multiplexer and Binary switches for inputs and binary Probes for outputs. The has one output for Y and another inverted output W. Use A and A for providing values for inputs 0-7. The internal values A, B, C are used for selection inputs B, C, and D. Simulate the circuit and test each input combination filling in the table shown below. 26

27 Table 12 Inputs Outputs Connect data to A B C D X In the Lab connect the circuit and verify the operations. Connect an LED to the multiplexer output so that it represents the parity bit which lights any time when the four bits input have even parity. Part 2: Vote Counter: A committee is composed of a chairman (C), a senior member (S), and a member (M). The rules of the committee state that: The vote of the member (M) will be counted as 2 votes The vote of the senior member will be counted as 3 votes. The vote of the chairman will be counted as 5 votes. Each of these persons has a switch to close ( l ) when voting yes and to open ( 0 ) when voting no. It is necessary to design a circuit that displays the total number of votes for each issue. Use a seven segment display and a decoder to display the required number. If all members vote no for an issue the display should be blank. (Recall from Experiment #4, that a binary input 15 into the 7447 blanks all seven segments). If all members vote yes for an issue, the display should be 0. Otherwise the display shows a decimal number equal to the number of 'yes' votes. Use two units, which include four multiplexers to design the combinational circuit that converts the inputs from the members switch to the BCD digit for the In LogicWorks use +5V for Logic 1 and ground for Logic 0 and use switches for C, S, and M. Use two chips and one decoder 7446 verify your design and get a copy of your circuit with the pin numbers to Lab so that you could connect the hardware in exactly the same way. 27

28 Digital Systems Laboratory 2011 Lab 8 : Flip-Flops Objectives: To become familiar with flip-flops. To implement and observe the operation of different flip-flops. Apparatus 7400 quad 2-input NAND gates (2) 7476 dual JK master-slave flip-flops. LogicWorks or Proteus can be used in the digital circuit simulations. Procedure 1. In the pre-lab using LogicWorks construct the circuit shown in Fig.25. Fig. 25 You can use generic NAND gates or and Binary Probes to simulate LEDs. Finally, we use SPDT for the bouncing switch. Using the simulated circuit fill in the truth table. 28

29 S R Q Q In the lab, build the RS latch shown in Fig.26. Use SPDT switch S as a bouncing switch. Q and Q outputs are connected to LED s of the CADET. Verify the truth table of SR latch experimentally. Fig Modify the basic RS latch into a D latch by adding the steering gates and the inverter shown in Fig.27 Connect the D input to the pulse generator of the CADET and set it at 1 Hz. Connect the enable input to a high through 1k resistor. Observe the output; obtain the truth table experimentally then change the enable to a low. Is the enable an active high or an active? Leave the enable low and place a momentary short to ground first on one output and then on the other. What happens? Fig The 7476 is a dual JK master-slave flip-flops with preset and clear inputs. The function table given in Table 13 defines the operation of the flip-flop. The positive transition of the CLOCK (CP) pulse changes the master flip-flop, and the negative transition changes the slave flip-flop as well as the output of the circuit. 29

30 Table 13 Fig. 28 In the lab, construct the circuit of Fig 28. Look at the data sheet for the 7476 and determine the inactive logic required at the PRE and CLR inputs. Connect the 7476 for the SET mode by connecting J = 1, K = 0. With CLOCK (CP) = 0; test the effect of PRE, CLR by putting a 0 on each, one at a time. Put CLR = 0, then pulse the clock (CP) by putting a HIGH then a LOW, on the clock. Does the CLR input override J input? Verify the operation of the JK flip flop by experimentally obtaining the characteristic. 30

31 Digital Systems Laboratory 2011 Lab 9 : Clocked Sequential Circuits and Counters Objectives To design, build and test synchronous sequential circuits To design, build, and test synchronous counters To design, build and test asynchronous counters Apparatus 7476 dual JK master-slave flip-flops (x2) 7400 quad 2-input NAND gates 7404 HEX inverter 7408 quad 2-input AND gate LogicWorks or Proteus can be used in the digital circuit simulations. Pre-Lab Questions 1. a. Design, construct and test a sequential circuit whose state is shown in Fig.29. Use JK flip-flops in the design. Fig. 29. The circuit has two flip-flops A, B, one input x and one output y. The circuit is to be designed by treating the unused states as don t care conditions. The final circuit must be analyzed to ensure that it is selfcorrecting. If not suggest a solution. 31

32 b. Complete the excitation table shown in Table 14. Table 14 c. Using Karnaugh maps obtain minimal expressions for the flip-flop input functions JA, KA,JB and KB. d. Simulate the circuit using LogicWorks. LogicWorks does not have the JK master-slave flip-flop IC Use instead the generic JK flip-flop as you did in Lab 8. In the Lab, build the circuit and check the output to verify the state table values. 2. a. In the pre-lab using LogicWorks and then in the lab using hardware ICs, design a 2-bit gray code counter using JK flip-flops. The required sequence is the binary equivalent of ( ). A state diagram for this counter is given in Fig. 30. Fig. 30 b. Complete the excitation table in Table 15 for the counter and obtain logic expression for the JK flip-flop input functions. 32

33 Table 15 Procedure: 1. Synchronous Sequential Circuits Build the sequential circuit that is designed in Pre-Lab Q1, and test the circuit by applying pulse from the CADET. Check that the output is the designed sequence. 2. Synchronous Counters Synchronous counters have all clock lines tied to a common clock causing all flip-flops to change at the same time. The count sequence of a counter can be analyzed by placing the counter into every possible number in the sequence and determining the next number in the sequence state diagram is developed as the analysis proceeds. (A state diagram is an illustration of the transitions that occur after each clock pulse). In the lab, build the 2-bit gray code counter circuit and test it by pulsing it from the CADET. Check that the output is the designed sequence. 3. A Synchronous Counters Asynchronous counters are a series of flip-flops each clocked by the previous state, one after the other. Since all the stages of the counter are not clocked together, a ripple effect propagates as various flip-flops are clocked. For this reason they are called ripple counters. The modulus of a counter is the number of different output states the counter may take (i.e. Mod 4 means the counter has four output states). In the pre-lab using LogicWorks construct a 4-bit asynchronous counter shown in Fig.31. (It is also called binary ripple counter). Use four generic JK flip-flops. Connect four Binary Probes to Q outputs. Connect all R and S inputs to Logic 1 and connect a switch to the CP input. Fig bit ripple counter. 33

34 In the lab use two 7476 ICs to implement 4-bit asynchronous counter as shown in Figure 3. Connect Q outputs of flip-flops to logic indicator lamps/leds of the CADET. Connect all clear (CLR) and preset (PRE) inputs to logic 1. Connect the CP input to the pulse output of the CADET and check the counter for proper operation. Write down the count sequence in Table 16. Identify this count sequence (up or down). Comment on what happens after the application of 15 pulses to CP input. Table 16 Count sequence for the 4-bit ripple counter. 34

35 Digital Systems Laboratory 2011 Lab 10 : Logic Design Using Verilog HDL and Xilinx ISE Laboratory Assignment #1 Objectives This lab is an introduction to logic design using Verilog-HDL with the Xilinx ISE 10.1i tools. No new logic design concepts are presented in this lab. The goals of this lab are for you to become familiar with the Xilinx s ISE Project Navigator tool for Verilog-HDL. Procedure: You will learn how to enter Verilog description of two inputs XOR gate and test your HDL definition in Xilinx ISE. You should do everything described below. In the lab, you are not going to implement the design in a programmable logic device, therefore the lab ends after testing the circuit using ModelSim. Project Navigator Overview The Project Navigator is divided into four main sub-windows, as seen in Figure 32. On the top left is the Sources in Project window which hierarchically displays the elements included in the project. Beneath the Sources in Project window is the Processes for Current Source window which displays available processes for the currently selected source. The third window at the bottom of the Project Navigator is the Console window which displays status messages, errors, and warnings, and which is updated during all project actions. The fourth window to the right is for viewing and editing text files. Each window may be 1 resized, undocked from Project Navigator or moved to a new location within the main Project Navigator window. The default layout can always be restored by selecting View Restore Default Layout. 1 The experiments 10 is adopted from San Jose State University Department of Electrical Engineering, EE178 and is updated with Xilinx ISE release 10.1i. 35

36 Figure 32: Typical Project Navigator Window The Sources in Project window consists of three tabs which provide information for the user. Each tab is discussed in further detail below: The Module View tab displays the project name, any user documents, the specified part type and design flow/synthesis tool, and design source files. Each file in the Module View has an associated icon. The icon indicates the file type (Verilog-HDL file or text file, for example). For a complete list of possible source types and their associated icons, see the Project Navigator online help. Select Help ISE Help Contents, select the Index tab and click Source / File types. If a file contains lower levels of hierarchy, the icon has a + to the left of the name. Verilog-HDL files have this + to show the modules within the file. You can expand the hierarchy by clicking the +. You can open a file for editing by double-clicking on the filename. The Snapshot View tab displays all snapshots associated with the project currently open in Project Navigator. A snapshot is a copy of the project including all files in the working directory, and synthesis and simulation subdirectories. A snapshot is stored with the project for which it was taken, and can be viewed in the Snapshot View. You can view the reports, user documents, and source files for all snapshots. All information displayed in the Snapshot View is read-only. Using snapshots provides an excellent version control system. 36

37 The Library View tab displays all libraries associated with the project open in Project Navigator. The Processes for Current Source window contains the Process View tab. The Process View tab is context sensitive and changes based upon the source type selected in the Sources for Project window. From the Process View tab, you can run the functions necessary to define, run and view your design. The Process View tab provides access to the following functions: Design Entry Utilities: Provides access to symbol generation, instantiation templates, HDL Converter, Command Line Log Files, Launch MTI, and simulation library compilation. User Constraints: Provides access to editing location and timing constraints. Synthesis: Provides access to Check Syntax, Synthesize, View RTL Schematic, and synthesis reports. This varies depending on the synthesis tools you use. Implement Design: Provides access to implementation tools and design flow reports. Generate Programming File: Provides access to the configuration tools and bitstream generation. The Processes for Current Source window incorporates automake technology. This enables the user to select any process in the flow and the software automatically runs the processes necessary to get to the desired step. For example, when you run the Implementation process, Project Navigator also runs the synthesis process, if necessary, because implementation is dependent on up-to-date synthesis results. The Console window displays errors, warnings, and informational messages. Errors are signified by a red box next to the message, while warnings have a yellow box. Warning and Error messages may also be viewed separately from other console text messages by selecting either the Warnings or Errors tab at the bottom of the console window. You can navigate from a synthesis error or warning message in the Console window to the location of the error in a source Verilog-HDL file. To do so, select the error or warning message, right-click the mouse, and from the menu select Goto Source. The Verilog-HDL source file opens and the cursor moves to the line with the error. You can also navigate from an error or warning message in the Console window to the relevant solution records on the Xilinx support website. These types of errors or warnings can be identified by the web icon to the left of the error. To navigate to the solution record, select the error or warning message, right-click the mouse, and from the menu select Goto Solution Record. The default web browser opens and displays all solution records applicable to this message. In the fourth window, you can access the ISE Text Editor, the ISE Language Templates, and HDL Bencher Text Editor. The ISE Text Editor enables you to edit source files and to access the ISE Language Templates, which is a catalog of Verilog-HDL and User Constraint File templates. You can use and modify these templates for your own design. Design Entry The design used in this tutorial is a simple two-input XOR. The design will be described in Verilog-HDL. Double-click the Project Navigator icon on your desktop or select Start Programs Xilinx ISE Project Navigator. From Project Navigator, select File New Project. The first of the New Project dialog boxes will appear, as shown in Figure

38 Figure 33: New Project Dialog 1 of 5 You are prompted to enter a project name, a project location, and a top level module type, as shown in Figure 33. You may change the project location to another folder if you wish. Do not use file or folder names that contain spaces. I advise all students to purchase a USB memory stick and store their work on removable media. Even if you are doing most of your work from home, you must have some means to transport your project to the lab if you need help debugging it. Never store your projects on the lab machines. When you are satisfied with the project name and location, click Next. The next dialog allows you to set additional project options. The first group of settings shown in Figure 34 represents the hardware target that is available to you on the Spartan-3 Starter Kit board. The second group of settings represents the design entry language, synthesis tool, and simulator preferences. Set the options as shown in Figure 34 and click Next. 38

39 Figure 34: New Project Dialog 2 of 5 The following dialog box of Figure 35 gives you the opportunity to create new source files as part of the new project process. Do not create new source files at this time, simply click Next to proceed. Figure 35: New Project Dialog 3 of 5 The following dialog box of Figure 36 gives you the opportunity to add existing source files as part of the new project process. Do not add existing source files at this time, simply click Next to proceed. 39

40 Figure 36: New Project Dialog 4 of 5 The final dialog box in the new project process, shown in Figure 37, provides a summary of the project that Project Navigator will create based on your settings. Review the summary to make sure it matches what is shown in Figure 37. If it does not, go Back and correct any errors. Otherwise, click Finish to complete this process. Figure 37: New Project Dialog 5 of 5 At this point, the project has been created but it does not contain any source files. Create a new source file for the two-input XOR. Either select Project New Source from the main menu or use the equivalent process in the Processes for Current Source window. The first of the New Source dialog boxes will appear, as shown in Figure

41 Figure 38: New Source Dialog 1 of 3 Select Verilog Module to indicate you are creating a Verilog-HDL design module. Then, provide a file name as shown in Figure 38. You should not need to change the specified location, which should be inside the project directory you created earlier. Click Next. The next dialog optionally allows you to specify the ports of the module. This may also be done in the text editor, when creating the module, so skip it at this stage. Simply confirm that the settings match those shown in Figure 39 and click Next. Figure 39: New Source Dialog 2 of 3 41

42 The final dialog box of Figure 40 provides a summary of the source that Project Navigator will create based on your settings. Review the summary to make sure it matches what is shown in Figure 40. If it does not, go Back and correct any errors. Otherwise, click Finish to complete this process. The new source file will be automatically opened in the text editor. Figure 40: New Source Dialog 3 of 3 In the text editor, some of the basic file structure is already in place. Keywords are displayed in blue, data types in red, comments in green, and values in black. This color-coding enhances readability and recognition of typographical errors. Now, enter the two-input XOR design. You may be able to simply copy and paste this from the lab handout, but if that doesn t work, transcribe the contents: // File: two_input_xor.v // Date: October 2006 // Name: // // This is the top level design for the Lab #1 assignment. // The `timescale directive specifies what the simulation time units are (1 ns here) // and what the simulator timestep should be (1 ps here). `timescale 1 ns / 1 ps module two_input_xor (in1, in2, out); // Declare the ports for this module. Keep in mind that all inputs are implied to be // of type wire. For inout ports (not used in this example) type wire is also implied. // The output is also implied to be of type wire, unless you add an explicit "reg out;" // statement. input in1, in2; output out; // Below is a description of what this module does. You could substitute other possible // descriptions, like those presented in the Verilog review presentation. assign out = in1 ^ in2; endmodule 42

43 At this point, you should end up with a window that looks somewhat like that shown in Figure 41. Once you are satisfied, save the file and close the window. It is a good idea to get in the habit of saving your project. There are options on the main menu to save individual files or the complete project. Figure 41: Completed Design Functional Simulation Functional simulation is done before the design is synthesized to verify that the logic you have created is correct. This allows a designer to find and fix any bugs in the design before spending time with subsequent steps. Project Navigator provides an integrated flow with the Modelsim simulator that allows simulations to be run from the Project Navigator. In order to simulate the design, a test bench is required to stimulate the design. Create a new source file for the test bench. Either select Project New Source from the main menu or use the equivalent process in the Processes for Current Source window. The first of the New Source dialog boxes will appear, as shown in Figure

44 Figure 42: New Source Dialog 1 of 3 Select Verilog Test Fixture to indicate you are creating a Verilog-HDL testbench module. Then, provide a file name as shown in Figure 42. You should not need to change the specified location, which should be inside the project directory you created earlier. Click Next. The second dialog, shown in Figure 43, asks you to identify a design module with which the test bench should be associated. Select the two-input XOR design as shown and click Next. Figure 43: New Source Dialog 2 of 3 The final dialog box of Figure 44 provides a summary of the source that Project Navigator will create based on your settings. Review the summary to make sure it matches what is shown in Figure 44. If it 44

45 does not, go Back and correct any errors. Otherwise, click Finish to complete this process. The new source file will be automatically opened in the text editor. Figure 44: New Source Dialog 3 of 3 In the text editor, some of the basic file structure is already in place. Keywords are displayed in blue, data types in red, comments in green, and values in black. This color-coding enhances readability and recognition of typographical errors. Now, enter the test bench for the two-input XOR design. You may be able to simply copy and paste this from the lab handout, but if that doesn t work, transcribe the contents: `timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 12:44:29 09/24/2006 // Design Name: two_input_xor // Module Name: testbench.v // Project Name: Lab1 // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: two_input_xor // // Dependencies: // // Revision: // Revision File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// 45

46 module testbench_v; // Outputs wire sig3; // Inputs reg sig1; reg sig2; // Instantiate the Unit Under Test (UUT) two_input_xor uut (.in1(sig1),.in2(sig2),.out(sig3) ); reg test_passed; initial begin // Let's start off assuming we are going // to pass the tests until we find a case // that contradicts! test_passed = 1'b1; // Test Case #0 sig1 = 1'b0; sig2 = 1'b0; #5; $display("at time %t, sig1 = %b, sig2 = %b, output = %b.", $time, sig1, sig2, sig3); if (sig3!= 1'b0) test_passed = 1'b0; // Test Case #1 sig1 = 1'b0; sig2 = 1'b1; #5; $display("at time %t, sig1 = %b, sig2 = %b, output = %b.", $time, sig1, sig2, sig3); if (sig3!= 1'b1) test_passed = 1'b0; // Test Case #2 sig1 = 1'b1; sig2 = 1'b0; #5; $display("at time %t, sig1 = %b, sig2 = %b, output = %b.", $time, sig1, sig2, sig3); if (sig3!= 1'b1) test_passed = 1'b0; // Test Case #3 sig1 = 1'b1; sig2 = 1'b1; #5; $display("at time %t, sig1 = %b, sig2 = %b, output = %b.", $time, sig1, sig2, sig3); if (sig3!= 1'b0) test_passed = 1'b0; // Now, print out a message with the test // results and then finish the simulation. if (test_passed) $display("result: PASS"); else $display("result: FAIL"); $stop; end 46

47 endmodule At this point, you should end up with a window that looks somewhat like that shown in Figure 45. Once you are satisfied, save the file and close the window. It is a good idea to get in the habit of saving your project. There are options on the main menu to save individual files or the complete project. Figure 45: Completed Test Bench Now that you have a test bench in your project, you can perform functional simulation on the design. The simulation processes enable you to run simulation on the design using Modelsim. To locate the Modelsim simulator processes, select the test bench in the Sources in Project window. Then, click the + next to the Modelsim Simulator entry in the Processes for Current Source window to expand the item, this is also shown in Figure 45. The following simulation processes are available: Simulate Behavioral Model. This process will start the design simulation. Simulate Post-Translate Verilog Model. Simulates the netlist after the NGDBuild stage. Simulate Post-Map Verilog Model. Simulates the netlist after the Map stage. Simulate Post-Place & Route Verilog Model. Simulates the netlist after Place & Route. At this point, you will perform a functional simulation using Simulate Behavioral Model but you must specify the simulation process properties first. Right click on Simulate Behavioral Model, and select Simulation Properties. The Process Properties dialog box appears, as shown in Figure

48 Figure 46: Simulation Process Properties If you do not have all the properties shown in Figure 46, you can make them visible by canceling the dialog box, then selecting Edit Preferences from the main menu. Select the Processes tab, set the Property Display Level to advanced, and then return to Simulation Properties. Make sure the properties are set as shown in Figure 46. The most interesting of these parameters is probably the simulation run time 1000 ns is more than sufficient for the test bench in the project. For test benches that require more simulation time, this property should be adjusted as needed. Click Ok. To start the simulation, double-click Simulate Behavioral Model. Modelsim creates a work directory, compiles the source files, loads the design, and performs simulation for the time specified. Four Modelsim windows will appear. The first, and most important, is the main Modelsim console, shown in Figure 47. This window displays messages from the simulator. These messages include notes, warnings, and errors, plus any output created by the design being simulated. You should see text output from the test bench. 48

49 Figure 47: Modelsim Console Window The second window is the structure window, shown in Figure 48. This window allows you to browse the hierarchy of the test bench and the design under test. In large hierarchical designs, it is very handy. Figure 48: Modelsim Structure Window The third window is the signals window, shown in Figure 49. This window shows the signals that are present in the portion of the design selected in the structure window. 49

50 Figure 49: Modelsim Signals Window The fourth and final window is the wave window, which is used to display simulated waveforms. Project Navigator automatically adds all top-level signals to the wave window, as shown in Figure 50. Additional signals are displayed in the signal window based upon the selected structure in the structure window. Figure 50: Simulated waveforms There are two basic methods for adding signals to the wave window. You can drag and drop them from the signals window, or highlight them in the signals window and then select Add Wave Selected Signals. If you use this second technique, you will see that there are additional options available. When you add new signals to the wave window, you will notice that waveforms do not automatically appear. This is because Modelsim did not record the simulation data for these signals. By default, Modelsim will only record data for the signals that have been added to the waveform window before or during the simulation. Therefore, when new signals are added to the waveform window, the simulation needs to be restarted and re-run for the desired amount of time. To restart and re-run the simulation, click the Restart Simulation button at the top of the console window. This button is shown in Figure 51. Figure 51: Restart Simulation Button 50

51 The Restart dialog box appears, as shown in Figure 52. Simply click Restart. At the Modelsim prompt, you will need to manually enter the run command. Enter run 1000 ns and hit enter. The simulation will run again, just like it did the first time. Figure 52: Restart Dialog The Modelsim simulator provides the capability of saving the signals list in the wave window. This can be important when additional signals or stimuli are added, and the simulation is restarted. In the wave window, select File Save Format. After restarting a simulation, you can select File Load Format in the wave window to restore. ============================ STOP HERE ====================================== Design Synthesis With a functionally correct design description in Verilog-HDL, the next step is to use a synthesis tool to transform your description into a netlist. A netlist is a machine-readable schematic. In this class, we will be using a tool called XST, which is integrated with Project Navigator and can only target Xilinx devices. Select two_input_xor in the Sources in Project window. Then, double click on the Synthesize XST process in the Processes for Current Source window. Project Navigator will synthesize the design and print information to the Console window in the process. As an informational note, it is possible to change the synthesis options before you synthesize by right clicking on Synthesize XST and then selecting Properties. For this tutorial, however, leave the options at their default settings. You should not see any errors in the Console window. However, you should always review the log file, which is available for viewing if you expand the Synthesize XST process item by clicking on the + next to it. Select View Synthesis Report. If you don t understand a particular message, you should not simply ignore it. Instead, search the Xilinx support web site or ask the instructor. For comparison purposes, here is a sample log file. Release 8.1i - xst I.24 Copyright (c) Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to./xst/projnav.tmp CPU : 0.00 / 0.39 s Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to./xst CPU : 0.00 / 0.39 s Elapsed : 0.00 / 0.00 s --> Reading design: two_input_xor.prj TABLE OF CONTENTS 51

52 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "two_input_xor.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name Output Format Target Device : "two_input_xor" : NGC : xc3s400-5-pq Source Options Top Module Name : two_input_xor Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 8 Register Duplication : YES Slice Packing : YES Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 52

53 Keep Hierarchy : NO RTL Output : Yes Global Optimization : AllClockNets Write Timing Constraints : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : Other Options lso : two_input_xor.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES safe_implementation : No Optimize Instantiated Primitives : NO use_clock_enable : Yes use_sync_set : Yes use_sync_reset : Yes ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "two_input_xor.v" in library work Module <two_input_xor> compiled No errors in compilation Analysis of file <"two_input_xor.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module <two_input_xor>. Module <two_input_xor> is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <two_input_xor>. Related source file is "two_input_xor.v". Found 1-bit xor2 for signal <out>. Unit <two_input_xor> synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Xors : 1 1-bit xor2 : 1 ========================================================================= 53

54 ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Xors : 1 1-bit xor2 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Loading device for application Rf_Device from file '3s400.nph' in environment D:\Xilinx. Optimizing unit <two_input_xor>... Mapping all equations... Building and optimizing final netlist... Found area constraint ratio of 100 (+ 5) on block two_input_xor, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : two_input_xor.ngr Top Level Output File Name : two_input_xor Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 3 Cell Usage : # BELS : 1 # LUT2 : 1 # IO Buffers : 3 # IBUF : 2 # OBUF : 1 ========================================================================= Device utilization summary: Selected Device : 3s400pq208-5 Number of Slices: 1 out of % Number of 4 input LUTs: 1 out of % Number of bonded IOBs: 3 out of 141 2% ========================================================================= 54

55 TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: No clock signals found in this design Timing Summary: Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 7.760ns Timing Detail: All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 2 / Delay: 7.760ns (Levels of Logic = 3) Source: in1 (PAD) Destination: out (PAD) Data Path: in1 to out Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) IBUF:I->O in1_ibuf (in1_ibuf) LUT2:I0->O Mxor_out_Result1 (out_obuf) OBUF:I->O out_obuf (out) Total 7.760ns (6.103ns logic, 1.657ns route) (78.6% logic, 21.4% route) ========================================================================= CPU : 6.69 / 7.16 s Elapsed : 7.00 / 7.00 s --> Total memory usage is kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) Reading the report is a good way to find out what types of (and how many) resources the synthesis tool used. You can also catch other problems this way. For example, if you found that this design description resulted in flip flops, in addition to a look-up table and I/O buffers, you had better go back and figure out what went wrong. This is why you must have an understanding of the hardware you are attempting to 55

56 create when you write your design description. At this point, you should have a green checkmark next to the Synthesize XST process. Design Implementation Design implementation is the sequence of events that translates your synthesized design netlist into a programming file for the FPGA device. Your design description, which you have now synthesized, has a number of ports at the top level. The implementation tools need to know how to assign the ports in your top level to physical pins on the FPGA, which are connected to various resources on the Spartan-3 Starter Kit board. If you do not make explicit assignments, the tools will randomly assign pins for you. However, this is generally a bad idea because random assignments will be wrong. The top-level design has two input ports, and a single output port. We will want to have two switches, SW0 and SW1, connected to the inputs. Additionally, we will want the output connected to an LED so that we can observe it indicator LD0 is appropriate for this purpose. If you inspect the top of the Spartan-3 Starter Kit board, you will notice that almost every resource has been thoughtfully annotated with text indicating which FPGA pins are connected to it. This information is also available in the Spartan-3 Starter Kit User Guide in tabular and schematic form. Try to identify which FPGA pins are used for SW0, SW1, and LD0, and then check your results with what is shown below. You will need to be able to do this on your own in future lab assignments: SW0 FPGA Pin F12 SW1 FPGA Pin G12 LD0 FPGA Pin K12 You now have enough information to create what is called a user constraint file, or UCF. This file contains design constraints that you did not specify in the Verilog-HDL description, such as pin location and design performance constraints. It is convenient to provide them in a UCF rather than in the Verilog-HDL description. For instance, if you make a mistake in the pin assignments, you do not need to go back and resynthesize your design. You can add a UCF to the project using the same process you used for adding the design and its test bench. Create a new source file; select Project New Source from the main menu or use the equivalent process in the Processes for Current Source window. The first of the New Source dialog boxes will appear, as shown in Figure

57 Figure 53: New Source Dialog 1 of 3 Select Implementation Constraints File to indicate you are creating a constraints file. Then, provide a file name as shown in Figure 53. You should not need to change the specified location, which should be inside the project directory you created earlier. Click Next. The second dialog, shown in Figure 54, asks you to identify a design module with which the constraints file should be associated. Select the two-input XOR design as shown and click Next. Figure 54: New Source Dialog 2 of 3 57

58 The final dialog box of Figure 55 provides a summary of the source that Project Navigator will create based on your settings. Review the summary to make sure it matches what is shown in Figure 55. If it does not, go Back and correct any errors. Otherwise, click Finish to complete this process. This time, however, you will notice that the new source file is not automatically opened in the text editor. Figure 55: New Source Dialog 3 of 3 If you select the constraint file in the Sources in Project Window, and then expand the Processes for Current Source window item for User Constraints by clicking on the + next to it, you will see that there are a number of ways to edit a user constraint file, including a text editor. The default user constraint editor is called PACE. Simply double click the constraint file in the Sources in Project window, and PACE will open, see Figure 56. PACE is a fairly powerful constraint editor but we will only be using a small portion of its capabilities in this tutorial. The PACE sub-windows shown in Figure 56 have been moved from their default positions in order to yield an improved screen capture. First click on I/O Pins in the Design Browser window. The Design Object List window will then show the names of the three top level ports and their signal directions. In this window, fill in the LOC fields based on the previously determined FPGA pin assignments. For the three IO STD fields select LVCMOS33, which is a common 3.3 volt signaling standard. After entering each pin assignment, you will notice that the corresponding package pin shown in the Package Pins window will be grayed out, indicating it is in use. This diagram represents the physical pins on the package that holds the FPGA die. You will also notice the highlighting of regions shown in the Device Architecture window. This diagram represents resources in use on the FPGA die related to your constraints in this case, the input and output buffers and I/O pads. When you are done, save your work and exit the PACE program. 58

59 Figure 56: Entering Pin Location Constraints using PACE Now that you have a constraint file in your project, you can implement the design. Select two_input_xor in the Sources in Project window. Then, double click on the Implement Design process in the Processes for Current Source window. Project Navigator will implement the design and print information to the Console window in the process. As an informational note, it is possible to change the implementation options before you implement by right clicking on Implement Design and then selecting Properties. For this tutorial, however, leave the options at their default settings. You should not see any errors in the Console window. However, you should always review the three log files, which are available for viewing if you expand the Implement Design process item by clicking on the + next to it. There are log files located under Translate, Map, and Place and Route. If you don t understand a particular message, you should not simply ignore it. Instead, search the Xilinx support web site or ask the instructor. At this point, you should have a green checkmark next to the Implement Design process. Timing Simulation After completing the implementation steps, you can simulate your design again this time, using a structural representation of your synthesized, placed, and routed design with worst-case delay information. The idea is to simulate your design, as physically implemented in the FPGA device. The simulation processes enable you to run simulation on the design using Modelsim. To locate the Modelsim simulator processes, select the test bench in the Sources in Project window. Then, click the + next to the Modelsim Simulator entry in the Processes for Source window to expand the item. You will perform a timing simulation using Simulate Post-Place & Route Verilog Model but you must specify the simulation process properties first, just like you did for functional simulation. Right click on Simulate Post-Place & Route Verilog Model, and select Simulation Properties. The Process Properties dialog box appears, as shown in Figure

60 Figure 57: Simulation Process Properties Make sure the properties are set as shown in Figure 57. The most interesting of these parameters is probably the simulation run time again, 1000 ns is more than sufficient for the test bench in the project. For test benches that require more simulation time, this property should be adjusted as needed. Click Ok. To start the simulation, double-click Simulate Post-Place & Route Verilog Model. Modelsim creates a work directory, compiles the source files, loads the design, and performs simulation for the time specified. The simulator will run, and you ll see results as before. Unless you are lucky, your simulation will fail. The testbench should report that your design has failed because it is checking the output of your design five nanoseconds after it has changed the inputs. If you look at the wave window, it appears that the FPGA implementation requires more than five nanoseconds for signals to propagate through the design more like ten to fifteen nanoseconds. The exact number depends on the device you are using, the placement, the routing, and your design. Close Modelsim, go back to your testbench, and change the delays to fifty nanoseconds (to be safe ) Then perform the simulation again. This time, it should pass. At this point, you are ready to program the FPGA with your design. The Spartan-3 Starter Kit board may be programmed by two different methods. One is to program the FPGA by download cable. The other is to program the PROM by download cable, and then have the PROM program the FPGA. Both are covered in the following sections. Programming the FPGA by Download Cable Programming the FPGA directly by the download cable is a convenient way to try out a design. This method is useful when you want to quickly test something, or are not certain your design is final. For example, at this point you are fairly confident your design is correct. However, you should realize by this point in your education that complex designs rarely ever work on the first try. One of the great advantages FPGAs have over ASICs is that the penalty for being wrong on the first try is minimal. The first order of business is to create a programming file for the FPGA. Select two_input_xor in the Sources in Project window. In the Processes for Current Source window, right click on Generate Programming File and then select Properties. The Process Properties dialog box appears. Select the Configuration Options tab, as shown in Figure

61 Figure 58: Generate Programming File Process Properties Change the Unused IOB Pins option to Float. The other settings should already be correct, but make sure they match what is shown in Figure 59. Figure 59: IOB pin settings Next, select the Startup Options tab, as shown in Figure

62 Figure 60: Generate Programming File Process Properties Change the FPGA Start-Up Clock option to JTAG Clock. The other settings should already be correct, but make sure they match what is shown in Figure 59. Click Ok to save the settings. Confirm that two_input_xor is selected in the Sources in Project window. Then, double click on the generate Programming File process in the Processes for Current Source window. Project Navigator will generate a programming file and print information to the Console window in the process. Before you continue, you must have the Spartan-3 Starter Kit board, power supply, and download cable available. Connect the download cable to the parallel port of the machine you are using. Plug the power supply into the wall. Loaok at the Spartan-3 Starter Kit board and identify the following. If you need help, ask the instructor to refer to the Spartan-3 Kit User Guide. PROM jumper, JP1, at top right Mode Jumper, J8, near Top Center 62

63 DC Power Jack, J4, at Left Center Download Cable Connector, J7, at Top Center Make sure that the PROM Jumper is set to Default and that the Mode Jumper has all three jumpers installed. You should have received the board in this state, but it is better to confirm. Then, insert the power plug into the DC Power Jack. Be aware that if a programming file was previously stored in the PROM, it will automatically load, and may result in board activity, like flashing LEDs, etc. This can be safely ignored. Finally, connect the download cable to its connector, as shown in Figure 60. Figure 60: Download Cable Connection To download your bitstream to the FPGA device, expand the Generate Programming File process by licking on the + next to it, and then double click on the Configure Device (impact) process. This will launch the impact program in another window. You will be immediately presented with several dialog boxes, the first of which is shown in Figure 61. Figure 61: Configuration Mode Selection There are actually a bewildering number of ways to configure an FPGA device. The board has an integrated JTAG programming function, which is also called Boundary-Scan mode. Select this option and proceed to the next dialog box. 63

64 Allow the program to automatically connect to the cable and identify the devices on the board. After you finish this sequence, the program will automatically detect the FPGA and PROM devices. and prompt you to specify a programming file for each device. You should see a message like that shown in Figure 62. Click Ok. Figure 62: Notification In the first file requestor, shown in Figure 63, select the two_input_xor.bit file you created with the implementation process. This is the FPGA programming file. Figure 63: Selecting the FPGA Programming File The next file requestor, shown in Figure 64, asks for a PROM programming file. We are not programming the PROM at this time, therefore select Bypass. 64

65 Figure 64: Placing the PROM in Bypass Mode At this point, you should be ready to program the FPGA. If you have made a mistake, you can correct your assignments by using the technique illustrated in Figure 65. Figure 65: Alternate File Assignment Method 65

66 To correct a file assignment, or to make initial assignments if impact does not automatically prompt you for programming files, select the FPGA icon in the impact window. Right click and select Assign New Configuration File. You will get a file requestor like that shown in Figure 63. You can repeat this process with the PROM icon, and you will get a file requestor like that shown in Figure 64. Finally, you will reach the point shown in Figure 66. impact is ready to program the FPGA. Select the FPGA icon in the window and then use the right mouse button to activate the menu as shown and select the Program option. Figure 66: Select Program Device You will be presented with a dialog box listing programming options. Most of these options are ghosted out for FPGA programming and are of no concern, see Figure 67. Disable the Verify option, if selected, and then click Ok to start the programming sequence. 66

67 Figure 67: Programming Options A progress indicator will appear. Once the programming is complete, the program will be sure to let you know if it was successful or if it failed. If the programming has failed, re-check your cable connections, the power connections, and the jumpers and then try again. If it still fails, ask the instructor for assistance. Now, you can test your design in hardware. Locate SW0 and SW1 on the board, and exercise your design by trying the four possible combinations of switch settings while observing LD0. Does the circuit behave as you expect? If it does not, seek assistance. If it does work properly, you are ready to try the other programming method. Exit impact (you do not need to save). Keep the board connected to power and the download cable. Programming the PROM by Download Cable The other method is to program the PROM by download cable, and then have the PROM program the FPGA. Typically you would program the PROM when you believe your design is completely done. After the PROM is programmed, each time the power is cycled, the FPGA will automatically load the programming file from the PROM. After the PROM is programmed, the need for the download cable is eliminated. Expand the Generate Programming File process by clicking on the + next to it, and then double click on the Generate PROM, ACE, or JTAG File process. This will launch the impact program again. You will be immediately presented with several dialog boxes, the first of which is shown in Figure 68. Select the PROM File option and proceed to the next dialog box, shown in Figure

68 Figure 68: PROM Property Selection In the dialog box of Figure 69, change the settings to match those shown. Do not forget to change the PROM File Name. Then proceed to the next dialog box. Figure 70: PROM Selection 68

69 In the dialog box of Figure 70, select the XCF XCF02S PROM type, and then click Add. You should see the PROM listed in the sub-window, at position zero. Then click Next. Figure 71: Summary Window Figure 71 shows a summary of what you have selected. If your results do not match that shown in Figure 71, go Back and correct your error. Otherwise, click Next to proceed. Figure 72: Add FPGA Programming Files 69

70 In the dialog box of Figure 72, click OK When the Add Device requestor dialog box appears, select the two_input_xor.bit file, which is the same one you used before. You will receive a warning that İMPACT needed to change the startup clock; dismiss the warning. You may recall, from a previous step, that we set the Startup Clock option to JTAG Clock when creating the programming file. This setting is required when programming the FPGA directly by the cable, but for programming the PROM the CCLK setting should be used. impact makes this change for you without requiring that you revisit the Generate Programming File process. After you add the two_input_xor.bit file, impact will ask you if you want to add another design file to the PROM data stream. Click No. You will see another dialog box that looks almost identical to Figure 73, which instructs you to click OK to start generating the PROM file. Click OK. impact will ask you if you want to create the file now. Click OK. You have now created the PROM programming file. You need to program the PROM. From the İMPACT main menu, select Mode Configuration Mode. Then, select File Initialize Chain. At this point, you will be prompted for programming files for the two devices in the chain, just like you were in the previous section. However, this time around, put the FPGA in Bypass mode and assign the lab1.mcs file to the PROM. Then, select the PROM icon, right click, and select Program. You will be presented with a dialog box listing programming options. Most of these options are ghosted out for PROM programming and are of no concern, see Figure 73. Verify the options are set as shown in Figure 73 and click Ok to start the programming sequence. 70

71 Figure 73: Programming Options A progress indicator will appear. Once the programming is complete, the program will be sure to let you know if it was successful or if it failed. If the programming has failed, re-check your cable connections, the power connections, and the jumpers and then try again. If it still fails, ask the instructor for assistance. Now, you can test your design again. Exit impact (you do not need to save). Unplug the download cable from the board. Unplug the power supply, wait three seconds, and then reapply power. The FPGA should load your design automatically from the PROM. To verify it worked properly, locate SW0 and SW1 on the board, and exercise your design by trying the four possible combinations of switch settings while observing LD0. Does the circuit behave as you expect? If it does not, seek assistance. If it does work properly, you are done with the lab. In order to receive credit, demonstrate your final result to the instructor. 71

72 Digital Systems Laboratory 2011 Laboratory 11 Assignment : Combinational #1 Logic Design with Gate Level Modeling in HDL Objectives: To get familiar with the gate-level modeling of combinational circuits in Verilog HDL To implement a simple combinational circuit on the FPGA board Background Gate-level modeling provides textual description of a schematic diagram. Verilog recognizes 12 basic gates as predefined primitives. Four primitive gates are of three-state type. They are declared with lowercase keywords: and, nand, or, nor, xor, xnor, not, buf. When the gates are simulated, the system assigns a four-valued logic set to each gate. Addition to the two logic values of 0 and 1, there are two other values: unknown and high impedance denoted by x and z, respectively. Figure 74: Simple combinational circuit The Verilog HDL description of the circuit of Figure 74 is shown below. // Description of simple model Figure 1 module circuit1(a,b,c,x,y) input A,B,C; output x,y; wire e; and g1(e,a,b); not g2(y,c); or g3(x,e,y); endmodule When HDL is used during simulation, it is sometimes necessary to specify the amount of delay from input to output of gates. In Verilog, the delay is specified in terms of time units and the symbol #. The association of a time unit with physical time is made using the timescale compiler directive. Such a directive specified before a module declaration. timescale 1ns/100ps The first number specifies the unit of measurement for time delays. The second number specifies the precision for which the delays are rounded off, in this case 0.1ns. If no time scale is specified, the simulator defaults to a certain time unit, usually 1ns. 72

73 In the following HDL description, delay for each gate is specified. module circuit_with_delay(a,b,c,x,y) input A,B,C; output x,y; wire e; and #(30) g1(e,a,b); not #(20) g2(y,c); or #(10) g3(x,e,y); endmodule In order to simulate a circuit with HDL, it is necessary to apply inputs to the circuits for the simulator to generate an output response. An HDL description that provides the stimulus to a design is called a test bench. The HDL description and the simulating module are given below. //Stimulus for the circuit of Figure 74 module stim_circut1; reg A,B,C; wire x,y; circuit_with_delay cwd(a,b,c,x,y); initial begin A=1 b0; B=1 b0; C=1 b0; #100 A=1 b1; B=1 b1; C=1 b1; #100 $finish; end endmodule module circuit_with_dly(a,b,c,x,y) input A,B,C; output x,y; wire e; and #(30) g1(e,a,b); not #(20) g2(y,c); or #(10) g3(x,e,y); endmodule The stimulus module stim_circuit1 has no ports. The inputs to the circuit are declared with reg keyword and output with wire keyword. The circuit_with_delay is instantiated with the name cwd. The initial statement specifies the inputs between the keywords begin and end. Initially, ABC=000. After 100 time unit, the inputs change to ABC=111. After 100 time unit, the simulation terminates. Preliminary work Write gate-level Verilog HDL description for the 2-to-4 line decoder with enable given in Figure

74 Figure 75: 2-to-4 line decoder with enable Experimental Work A. Simple Combinational Circuit 1. Enter gate-level Verilog HDL description of the circuit of Figure 74 in Xilinx ISE 10.1i. Using the HDL stimulus module, simulate the circuit and verify it. Use ISE simulator or ModelSim. 2. Specifiy the gates delays as 30,20,and 10 for the gates AND, NOT and OR respectively. Using the stimulus module simulate the circuit and verify it. B. 2-to-4 Decoder with Enable 1. Enter gate-level Verilog HDL description of the 2-to-4 decoder in the ISE 10.1i. Using the HDL stimulus module, simulate the circuit and verify it. Note: Attach the source codes ( HDL and stimulus module), and waveforms to the laboratory report. 74

75 Digital Systems Laboratory 2011 Lab 12 : Central Processing Unit (CPU) Objectives To learn how a simple CPU works using SimHYMN simulator To write and debug simple assembly programs 75

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