Unit 4 Session  15 FlipFlops


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1 Objectives Unit 4 Session  15 FlipFlops Usage of D flipflop IC Show the truth table for the edgetriggered D flipflop and edgetriggered JK flipflop Discuss some of the timing problems related to flipflops Draw a diagram of a JK masterslave flipflop and describe its operation D FlipFlop 7475 IC The 7475 is a TTL MSI circuit that contains four D latches. It is ideally suited for use as temporary storage for binary information between processing units and input / output or indicator units. The 7475 IC connection diagram is as shown below: Page 1
2 The 7475 logic diagram is as shown below: The 7475 stores 4bit data (nibble). If more than one 7475 is used, words of any length can be stored. Edgetriggered D FlipFlop The logic circuit of a positiveedge triggered D flipflop is as shown: On the leading edge of the clock (PT), the data bit is loaded into the flipflop and Q takes on the value of D. The truth table is as shown below: C D Q n+1 0 X Q n Preset and Clear Functions When power is first applied, flipflops will have their outputs in random states. We can make the flipflop to have the desired starting state. Additional PRESET and CLEAR inputs are used. The PRESET and CLEAR inputs are called asynchronous inputs because they activate the flipflop independently of the clock. The D input is a synchronouss input because it has an effect only with the positive transitions of the clock. Page 2
3 D FlipFlop with PRESET and CLEAR functions The SR flipflop can be converted into a D flipflop with additional PRESET and CLEAR inputs as shown below: Pressing the RESET button will set Q to 1 on the first PT of the clock. Q will remain highh as long as the button is pressed and the first PT of the clock after releasing the button will set Q according to the D input. A high PRESET forces Q to 1, and a high CLEAR resets Q to 0. D FlipFlop Symbols The different D flipflop symbols are as shown below: Edgetriggered JK FlipFlops Setting R = S = 1 with an RS flipflopp forces both Q and Q to the same logic level. This is an illegal condition. The JK flipflop accounts for this illegal input and is therefore a more versatile circuit. Page 3
4 PositiveEdge Triggered JK FlipFlopp The crosscoupling from outputs to inputs changes the RS flipflop into a JK flipflop as shown: JK FlipFlop Operation Consider J = K = 1. If Q = 1, the lower AND gate passes a RESET pulse on the next PT and Q changes to 0 as illustrated in the figure below: Consider J = K = 1. If Q = 0, the upper AND gate passes a SET pulse on the next PT and Q changes to 1 as illustrated in the figure below: Therefore, J = K = 1 means the flipflop will toggle (switch to the opposite state) on the next positive clock edge. Page 4
5 The truth table of the JK flipflop is shown below: J K Q n+1 Action 0 Q n No Change 1 0 RESET 0 1 SET 1 Q n TOGGLE Racing Problem When J = K = 1, the output can continue to toggle as long as the clock is high. This condition is called the racearound condition. Propagation delay prevents the JK flipflop from racing. The JK flipflop output changes after the PT of the clock. The new Q and Q values are too late to coincide with the PTs driving the AND gate. If PTs are narrower than the propagation delay of the flipflop, the returning Q and Q arrive too late to cause false triggering. Avoiding Racing Problem A better method to avoid race around condition is to use a masterslave circuit. FlipFlop Timing Switching time of transistors in the flipflop circuit is the main cause of propagation delay t p. Stray capacitance of the D input and other factors makes it necessary for data bit D to be at the input before the clock edge arrives. Setup Time The setup time t setup is the minimum amount of time that the data bit must be present before the clock edge appears. The setup time ensures that the stray capacitance present at the D input (shown in figure below) will get charged to the logic 1 voltage level. Page 5
6 Hold Time Data bit D has to be held long enough for the internal transistors to switch states. Only after the transition is assured, we can allow data bit D to change. Hold time t hold is the minimum amount of time that the data bit D must be present after the PT of the clock. Setup and Hold Times Example: A D flipflop has the following data time = 15 ns. a. How far ahead of the triggering clock edge must the data be applied? Solution: 5 ns (set up time has be satisfied) b. How long after the clock edge must the data be present to ensure correct storage? Solution: 10 ns (hold time has be satisfied) c. How long after the clock edge, the output changes? Solution: 15 ns (propagation delay) sheet information: Setup time = 5 ns, Hold time = 10 ns, Propagation Page 6
7 JK MasterSlave FlipFlop The JK masterslave flipflop configuration is as shown below: The J and K data is processed by the flipflop after a complete clock pulse. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. On the negative transition of the clock, the data from the master is transferred to the slave. The flipflop is referred to as pulsetriggered. JK MasterSlave FlipFlop Construction using NAND gates Step 1 Step 2 Page 7
8 Step 3 The 7476 IC The 7476 is a TTL dual JK master slave flipflop with preset and clear inputs. The connection diagram and the function table is as shown below: Page 8
9 Function Table 10CS 33 LOGIC DESIGN UNIT 4 Clocks, FlipFlops Note 1: This configuration is nonstable; i. e., it will not persist when the preset and/or clear inputs return to their inactive (high) level. Toggle FlipFlop The toggle flipflop is realized using JK flipflop as shown below: The truth table of toggle flipflop is shown below: C T Q n+1 _ _ 0 Q n _ _ 1 Q n 0 X Q n Applications of FlipFlops D flipflops are used as registers. T flipflops are used as counters. Page 9
10 Questions 1. With the help of a block diagram, explain the working of a JK Master  Slave flip  flop. 2. Explain the different types of flipflops along with their truth table. Also explain the racearound condition in a flipflop. Page 10
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