Unit 4 Session - 15 Flip-Flops

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1 Objectives Unit 4 Session - 15 Flip-Flops Usage of D flip-flop IC Show the truth table for the edge-triggered D flip-flop and edge-triggered JK flip-flop Discuss some of the timing problems related to flip-flops Draw a diagram of a JK master-slave flip-flop and describe its operation D Flip-Flop 7475 IC The 7475 is a TTL MSI circuit that contains four D latches. It is ideally suited for use as temporary storage for binary information between processing units and input / output or indicator units. The 7475 IC connection diagram is as shown below: Page 1

2 The 7475 logic diagram is as shown below: The 7475 stores 4-bit data (nibble). If more than one 7475 is used, words of any length can be stored. Edge-triggered D Flip-Flop The logic circuit of a positive-edge triggered D flip-flop is as shown: On the leading edge of the clock (PT), the data bit is loaded into the flip-flop and Q takes on the value of D. The truth table is as shown below: C D Q n+1 0 X Q n Preset and Clear Functions When power is first applied, flip-flops will have their outputs in random states. We can make the flipflop to have the desired starting state. Additional PRESET and CLEAR inputs are used. The PRESET and CLEAR inputs are called asynchronous inputs because they activate the flip-flop independently of the clock. The D input is a synchronouss input because it has an effect only with the positive transitions of the clock. Page 2

3 D Flip-Flop with PRESET and CLEAR functions The SR flip-flop can be converted into a D flip-flop with additional PRESET and CLEAR inputs as shown below: Pressing the RESET button will set Q to 1 on the first PT of the clock. Q will remain highh as long as the button is pressed and the first PT of the clock after releasing the button will set Q according to the D input. A high PRESET forces Q to 1, and a high CLEAR resets Q to 0. D Flip-Flop Symbols The different D flip-flop symbols are as shown below: Edge-triggered JK Flip-Flops Setting R = S = 1 with an RS flip-flopp forces both Q and Q to the same logic level. This is an illegal condition. The JK flip-flop accounts for this illegal input and is therefore a more versatile circuit. Page 3

4 Positive-Edge Triggered JK Flip-Flopp The cross-coupling from outputs to inputs changes the RS flip-flop into a JK flip-flop as shown: JK Flip-Flop Operation Consider J = K = 1. If Q = 1, the lower AND gate passes a RESET pulse on the next PT and Q changes to 0 as illustrated in the figure below: Consider J = K = 1. If Q = 0, the upper AND gate passes a SET pulse on the next PT and Q changes to 1 as illustrated in the figure below: Therefore, J = K = 1 means the flip-flop will toggle (switch to the opposite state) on the next positive clock edge. Page 4

5 The truth table of the JK flip-flop is shown below: J K Q n+1 Action 0 Q n No Change 1 0 RESET 0 1 SET 1 Q n TOGGLE Racing Problem When J = K = 1, the output can continue to toggle as long as the clock is high. This condition is called the race-around condition. Propagation delay prevents the JK flip-flop from racing. The JK flip-flop output changes after the PT of the clock. The new Q and Q values are too late to coincide with the PTs driving the AND gate. If PTs are narrower than the propagation delay of the flip-flop, the returning Q and Q arrive too late to cause false triggering. Avoiding Racing Problem A better method to avoid race around condition is to use a master-slave circuit. Flip-Flop Timing Switching time of transistors in the flip-flop circuit is the main cause of propagation delay t p. Stray capacitance of the D input and other factors makes it necessary for data bit D to be at the input before the clock edge arrives. Setup Time The setup time t setup is the minimum amount of time that the data bit must be present before the clock edge appears. The setup time ensures that the stray capacitance present at the D input (shown in figure below) will get charged to the logic 1 voltage level. Page 5

6 Hold Time Data bit D has to be held long enough for the internal transistors to switch states. Only after the transition is assured, we can allow data bit D to change. Hold time t hold is the minimum amount of time that the data bit D must be present after the PT of the clock. Setup and Hold Times Example: A D flip-flop has the following data time = 15 ns. a. How far ahead of the triggering clock edge must the data be applied? Solution: 5 ns (set up time has be satisfied) b. How long after the clock edge must the data be present to ensure correct storage? Solution: 10 ns (hold time has be satisfied) c. How long after the clock edge, the output changes? Solution: 15 ns (propagation delay) sheet information: Setup time = 5 ns, Hold time = 10 ns, Propagation Page 6

7 JK Master-Slave Flip-Flop The JK master-slave flip-flop configuration is as shown below: The J and K data is processed by the flip-flop after a complete clock pulse. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. On the negative transition of the clock, the data from the master is transferred to the slave. The flip-flop is referred to as pulse-triggered. JK Master-Slave Flip-Flop Construction using NAND gates Step 1 Step 2 Page 7

8 Step 3 The 7476 IC The 7476 is a TTL dual JK master slave flip-flop with preset and clear inputs. The connection diagram and the function table is as shown below: Page 8

9 Function Table 10CS 33 LOGIC DESIGN UNIT 4 Clocks, Flip-Flops Note 1: This configuration is nonstable; i. e., it will not persist when the preset and/or clear inputs return to their inactive (high) level. Toggle Flip-Flop The toggle flip-flop is realized using JK flip-flop as shown below: The truth table of toggle flip-flop is shown below: C T Q n+1 _ _ 0 Q n _ _ 1 Q n 0 X Q n Applications of Flip-Flops D flip-flops are used as registers. T flip-flops are used as counters. Page 9

10 Questions 1. With the help of a block diagram, explain the working of a JK Master - Slave flip - flop. 2. Explain the different types of flip-flops along with their truth table. Also explain the race-around condition in a flip-flop. Page 10

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