INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic Package Outlines 74C/CT to-16 line decoder/demultiplexer with File under Integrated Circuits, IC6 September 93

2 74C/CT4515 FEATURES Inverting outputs Output capability: standard I CC category: MSI GENERA DESCRIPTION The 74C/CT4515 are high-speed Si-gate CMOS devices and are pin compatible with 4515 of the 4B series. They are specified in compliance with JEDEC standard no. 7A. The 74C/CT4515 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A to A 3 ) with latches, a latch enable input (E), and an active OW enable input (E). The 16 inverting outputs (Q to Q 15 ) are mutually exclusive active OW. When E is IG, the selected output is determined by the data on A n. When E goes OW, the last data present at A n are stored in the latches and the outputs remain stable. When E is OW, the selected output, determined by the contents of the latch, is OW. When E is IG, all outputs are IG. The enable input (E) does not affect the state of the latch. When the 4515 is used as a demultiplexer, E is the data input and A to A 3 are the address inputs. QUICK REFERENCE DATA GND = V; T amb =25 C; t r =t f = 6 ns SYMBO PARAMETER CONDITIONS C TYPICA CT UNIT t P / t P propagation delay A n to Q n C = 15 pf; V CC =5 V ns C I input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. September 93 2

3 74C/CT4515 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1 E latch enable input (active IG) 2, 3, 21, 22 A to A 3 address inputs 11, 9, 1, 8, 7, 6, 5, 4,18, 17, 2,, 14, 13, 16, 15 Q to Q 15 multiplexer outputs (active OW) 12 GND ground ( V) 23 E enable input (active OW) 24 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. September 93 3

4 September 93 4 Philips Semiconductors 74C/CT4515 Fig.4 Functional diagram. APPICATIONS Digital multiplexing Address decoding exadecimal/bcd decoding FUNCTION TABE Notes 1. E = IG = IG voltage level = OW voltage level X = don t care INPUTS OUTPUTS E A A 1 A 2 A 3 Q Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Q 9 Q 1 Q 11 Q 12 Q 13 Q 14 Q 15 X X X X

5 74C/CT4515 Fig.5 ogic diagram. September 93 5

6 74C/CT4515 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR 74C GND = V; t r =t f = 6 ns; C = 5 pf SYMBO t P / t P t P / t P t P / t P PARAMETER propagation delay 8 A n to Q n propagation delay 66 E to Q n 24 propagation delay 5 E to Q n t T / t T output transition time 7 6 t W t su t h latch enable pulse width IG set-up time A n to E hold time A n to E T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) ns ns ns ns ns ns ns WAVEFORMS Fig.7 Fig.7 Fig.7 September 93 6

7 74C/CT4515 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT A n E E UNIT OAD COEFFICIENT AC CARACTERISTICS FOR 74CT GND = V; t r =t f = 6 ns; C = 5 pf T amb ( C) TEST CONDITIONS ns ns ns 74CT SYMBO PARAMETER UNIT V WAVEFORMS to+85 4 to +125 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay A n to Q n t P / t P propagation delay E to Q n t P / t P propagation delay E to Q n t T / t T output transition time ns t W t su t h latch enable pulse width IG set-up time A n to E hold time A n to E ns Fig ns Fig ns Fig.7 September 93 7

8 74C/CT4515 AC WAVEFORMS (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Waveforms showing the input (A n, E, E) to output (Q n ) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 5%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the minimum pulse width of the latch enable input (E) and the set-up and hold times for E to A n. Set-up and hold times are shown as positive values but may be specified as negative values. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. September 93 8