Lecture 6. Digital Electronics 2. Memory elements: D-FlipFlop, SR-Latch, D-Latch combibatorial logic vs sequential logic

Transcription

1 Lecture 6 Memory elements: D-FlipFlop, SR-Latch, D-Latch combibatorial logic vs sequential logic BTF Apr. 17, 2015 Bern University of Applied Sciences

2 Agenda Rev e 6.2

3 What is the difference Combinational Logic Combinational Logic is always concurrent This type of logic can never be synchronouse The output depends on its inputs coupled over a logic function F (<INPUTS>) Rev e 6.3

4 What is the difference Combinational Logic Combinational Logic Combinational Logic is always concurrent This type of logic can never be synchronouse The output depends on its inputs coupled over a logic function F (<INPUTS>) Storage Elements To obtain sequential logic, sequential code must be employed It is also possible to build combinational circuits with sequential statements It is used for synchronous logic design Rev e 6.3

5 Two structures of sequential code Combinational Logic Storage Elements A typical block-schematic of a state-machine It has a storage element therefore outputs depends on past inputs Rev e 6.4

6 Two structures of sequential code Combinational Logic Combinational Logic Storage Elements Storage Elements A typical block-schematic of a state-machine It has a storage element therefore outputs depends on past inputs It is used to realize storage elements Simple storage elements are FlipFlops here we see a RAM which is a bunch of FlipFlops Rev e 6.4

7 The simplest Which other basic elements in terms of memories apart of the to you know? Rev e 6.5

8 The simplest Which other basic elements in terms of memories apart of the to you know? SR-Latch, D-Latch and D-FlipFlop Rev e 6.5

9 The simplest Which other basic elements in terms of memories apart of the to you know? SR-Latch, D-Latch and D-FlipFlop What is the difference between those elements? Rev e 6.5

10 The simplest Which other basic elements in terms of memories apart of the to you know? SR-Latch, D-Latch and D-FlipFlop What is the difference between those elements? How would you describe them by using VHDL in terms of sequential or combinatorial logic? Rev e 6.5

11 The SR-Latch The Functional Description S and R both low With both the S and R inputs at logic 0 level, the Q output will be latched at whatever value it was at. When at logic 0, the S and R inputs do not influence the output of the latch. R goes high and low When R goes high, the latch is reset meaning that Q goes low. This assumes that S is low. If R goes low again, the output of the latch will remain latched low. In other words, a positive pulse on R resets Q when S is low. S goes high and low With R low, when the S input goes high, the output of the latch will go high. If S is taken low after this, the Q output will remain latched high. In other words, a positive pulse on S sets Q when R is low. R and S both high R and S must never be allowed to go high at the same time. This is an undefined state for this type of latch. Rev e 6.6

12 The SR-Latch RxSI 1 QxSO 1 QxSLO SxSI Rev e 6.7

13 The SR-Latch RxSI SxSI 1 1 QxSO QxSLO Solution : SR-Latch 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity SrLatch is 5 port( 6 SxSI, RxSI : in std_logic; 7 QxSO, QxSLO : out std_logic 8 ); 9 end entity SrLatch; architecture dataflow of SrLatch is 12 signal Q2SxD, Qnot2RxD : std_logic; 13 begin 14 Q2SxD <= RxSI nor Qnot2RxD; 15 Qnot2RxD <= SxSI nor Q2SxD; 16 QxSO <= Q2SxD; 17 QxSLO <= Qnot2RxD; 18 end architecture dataflow; Rev e 6.7

14 The D-Latch The Functional Description G is low G is high The memorizing mode. This means the output Q remains whether or not D changes. The transparent mode. The input values are directly propagated to the output Q. Rev e 6.8

15 The D-Latch The Functional Description G is low The memorizing mode. This means the output Q remains whether or not D changes. G is high Solution : data-flow (arch) 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity DLatch is 5 port( 6 DxDI, GxDI : in std_logic; 7 QxDO : out std_logic); 8 end entity DLatch; 9 10 architecture dataflow of DLatch is signal StorexD : std_logic; begin StorexD <= DxDI when (GxDI = 1 ) else StorexD; 17 QxDO <= StorexD; end architecture dataflow; The transparent mode. The input values are directly propagated to the output Q. Rev e 6.8

16 The D-Latch The Functional Description G is low The memorizing mode. This means the output Q remains whether or not D changes. G is high Solution : data-flow (arch) The transparent mode. The input values are directly propagated to the output Q. Solution : behavioral (arch) 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity DLatch is 5 port( 6 DxDI, GxDI : in std_logic; 7 QxDO : out std_logic); 8 end entity DLatch; 9 10 architecture dataflow of DLatch is signal StorexD : std_logic; begin StorexD <= DxDI when (GxDI = 1 ) else StorexD; 17 QxDO <= StorexD; end architecture dataflow; 1 library ieee; 2 use ieee.std_logic_1164.all; 3 entity DLatch is 4 port( 5 DxDI, GxDI : in std_logic; 6 QxDO : out std_logic); 7 end entity DLatch; 8 architecture behavioral of DLatch is 9 signal StorexD : std_logic; 10 begin 11 DL_proc: process(gxdi) is 12 begin 13 if (GxDI = 1 ) then 14 StorexD <= DxDI 15 else 16 StorexD <= StorexD; 17 end if; 18 end process DL_proc; 19 QxDO <= StorexD; 20 end architecture behavioral; Rev e 6.8

17 The The behavioral based design method allow us to describe circuits that store bits This is realized typically by the help of FliFlops There are two new input signals clock and reset among others We remember, FliFlops are edge-sensitive and synchronous elements Rev e 6.9

18 The The behavioral based design method allow us to describe circuits that store bits This is realized typically by the help of FliFlops There are two new input signals clock and reset among others We remember, FliFlops are edge-sensitive and synchronous elements Example : IF 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity Dff is 5 port( 6 DxDI : in std_logic; 7 ClkxCI : in std_logic; 8 RstxRI : in std_logic; 9 QxDO : out std_logic 10 ); 11 end entity Dff; Rev e 6.9

19 The The behavioral based design method allow us to describe circuits that store bits This is realized typically by the help of FliFlops There are two new input signals clock and reset among others We remember, FliFlops are edge-sensitive and synchronous elements Example : IF Example : behavioral 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity Dff is 5 port( 6 DxDI : in std_logic; 7 ClkxCI : in std_logic; 8 RstxRI : in std_logic; 9 QxDO : out std_logic 10 ); 11 end entity Dff; 1 architecture synchrst of Dff is 2 3 begin 4 5 dff: process(clkxci, RstxRI) is 6 begin 7 if rising_edge(clkxci) then 8 -- synchronous reset 9 if RstxRI = 1 then 10 QxDO <= 0 ; 11 else 12 QxDO <= DxDI; 13 end if; 14 end if; Rev e 6.9

20 A Register How can we realize a register? Example : behavioral 1 architecture synchrst of Dff is 2 3 begin 4 5 dff: process(clkxci, RstxRI) is 6 begin 7 if rising_edge(clkxci) then 8 -- synchronous reset 9 if RstxRI = 1 then 10 QxDO <= 0 ; 11 else 12 QxDO <= DxDI; 13 end if; 14 end if; We use the FliFlop designed previously Rev e 6.10

21 A Register How can we realize a register? Example : Hierarchical Register 1 architecture structural of Reg4Bit is 2 component Dff is 3 port( 4 DxDI : IN std_logic; 5 ClkxCI : IN std_logic; 6 RstxRI : IN std_logic; 7 QxDO : OUT std_logic 8 ); 9 end component; begin RegBit0 : Dff port map(dxdi(0), ClkxCI, RstxRI, QxDO(0)); 14 RegBit1 : Dff port map(dxdi(1), ClkxCI, RstxRI, QxDO(1)); 15 RegBit2 : Dff port map(dxdi(2), ClkxCI, RstxRI, QxDO(2)); 16 RegBit3 : Dff port map(dxdi(3), ClkxCI, RstxRI, QxDO(3)); 17 end architecture structural; We use the FliFlop designed previously The FlipFlop component will be instantiated four times 4 4 Reg 4 Bit Rev e 6.10

22 A Register How can we realize a register? Example : Behavioral Register 1 architecture behavioral of Reg4Bit is 2 begin 3 reg_proc: process(clkxci, RstxRI) is 4 begin 5 if rising_edge(clkxci) then 6 if (RstxRI = 1 ) then 7 QxDO <= (others => 0 ); 8 else 9 QxDO <= DxDI; 10 end if; 11 end if; 12 end process reg_proc; 13 end architecture behavioral; We use the FliFlop designed previously The FlipFlop component will be instantiated four times There is an other method - the behavioral approach 4 Reg 4 Bit 4 Rev e 6.10

23 Realize a Shif-Register Realize a shift-register with four stages Which method is the best What are pros and cons of possible methods Rev e 6.11