EE 560 SEQUENTIAL MOS LOGIC CIRCUITS. Kenneth R. Laker, University of Pennsylvania

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1 1 EE 560 EUENTIAL MO LOGIC CICUIT

2 2 LOGIC CICUIT COMBINATIONAL (non-regenerative) EUENTIAL (regenerative) BITABLE MONOTABLE ATABLE

3 3 V 1 V out1 V 2 V 3 M COMBINATIONAL LOGIC CICUIT M V out2 MEMOY

4 4 V o1 V i2 V o /V in < 1 INV1 VTC V o /V in >> 1 V i1 1 V o1 INV2 VTC V o2 2 Vi2 ENEGY V o /V in < 1 V i1 V o2 BITABLE BEHAVIO

5 5 V V G G B V OH B V o1 B G V i1 V i2 G V o2 V th V o1 B V OL V o2 t

6 MALL IGNAL ANALYI 6 i g1 v g1 1 v o1 i d1 C g i d2 v g2 i g2 v o2 2 AUME: C g >> C d v o1 (0) = v o2 (0) = V th C g i g1 = i d2 = g m v g2 i g2 = i d1 = g m v g1 where where and v o1 = v g2 and v o2 = v g1 => for i = 1, 2

7 for i = 1, for t >> τ 0 0 for t >> τ 0 ΝΟΤΕ ΤΗΑΤ v o2 V OH v o1 : V th -> V OH or V OL v o2 : V th -> V OL or V OH V th V OL V OL V th V OH v o1

8 As BITABLE circuit settles from UNTABLE Op-Pt to TABLE Op-Pt, signal travels around 2 INV loop n times 8 1 v o1 loop v o2 2 If during interval t = T, signal travels around the loop n times V OH loop 1 loop 2 loop n A 1 A 2 A n V th v o1 e t/τ v o2 V OL T t

9 FULL CMO LATCH V V 9 M1 M2 M3 M4 TATE OF LATCH can be EXTENALLY WITCHE between the 2 TABLE TATE ET TATE: = 1, = 0 => = 1, = 0 EET TATE: = 0, = 1 => = 0, = 1 HOL: = 0, = 0 (like two cross-coupled Inverters) NOT ALLOWE: = 1, = 1

10 10 NO-based Latch n +1 n+1 Operation n 0 0 n hold set reset NOT allowed

11 V V 11 M1 M2 M3 M4 n +1 n+1 Operation V OH V OL V OH V OL M1, M2 ON, M3, M4 OFF V OL V OH V OL V OH M1, M2 OFF, M3, M4 ON V OL V OL V OH V OL M1, M4 OFF, M2 ON or V OL V OL V OL V OH M1, M4 OFF, M3 ON

12 V V 12 M6 M8 M5 M7 M1 M2 C M3 M4 C C = C gb2 + C gb5 + C db3 + C db4 + C db7 + C sb7 + C db8 C = C gb3 + C gb7 + C db1 + C db2 + C db5 + C sb5 + C db6 Estimate time to simultaneously switch coupled differential equations. Pessimistic Estimate: Assume & & : solution of two switch in sequence τ rise, ( latch) = τ rise, ( NO2) + τ fall, ( NO 2) For = 1, = 0

13 NAN BAE LATCH 13 V V M2 M4 M1 M3 n +1 n+1 Operation NOT allowed set reset 1 1 n hold n

14 14 NAN-based Latch n +1 n+1 Operation NOT allowed set reset 1 1 n hold n NOTE:, (NAN2) =, (NO2) active low, active high,

15 CLOE LATCH AN FLIP-FLOP CICUIT 15 CLOE LATCH: LATCH WHEN = 0,, HAVE NO INFLUENCE OF, ET TATE: = 1, = 1, = 0 EET TATE: = 1, = 0, = 1 NOT ALLOWE: = 1, = 1, = 1 => HOL ACTIVE HIGH

16 HOL TATE: = 0, = X, = X ET TATE: = 1, = 1, = 0 EET TATE: = 1, = 0, = 1 NOT ALLOWE: = 1, = 1, = 1 16 GLITCH WHEN GLITCH ON (O ) OCCU UING = 1, I ET (O EET) LEVEL ENITIVE: WHEN = 1, ANY CHANGE IN, WILL EFFECT.

17 CMO IMPLEMENTATION OF CLOE NO BAE LATCH 17 V V M1 M2 M3 M4

18 18 LATCH WHEN = 1,, HAVE NO INFLUENCE OF, => HOL ET TATE: = 0, = 0, = 1 EET TATE: = 0, = 1, = 0 NOT ALLOWE: = 0, = 0, = 0 ACTIVE LOW

19 CMO IMPLEMENTATION OF CLOE NAN BAE LATCH 19 V V M2 M4 M1 M3

20 CLOE JK LATCH: 20 NAN BAE CLOE JK LATCH J K NAN NO NOT ALLOWE INPUT COMBINATION J K JK LATCH

21 21 = 0 => hold J = 1=> active K LATCH = 1 J K n n n+1 n +1 Operation hold hold reset reset set set toggle toggle OC

22 22 TO PEVENT OICLLATION WHEN J = K = 1: T 1 τ JKP > T 1 τ JKP = INPUT-OUTPUT POP ELAY OF JK LATCH NO BAE CLOE JK LATCH K J LATCH

23 CMO AOI IMPLEMENTATION NO BAE CLOE JK LATCH 23 V V K J

24 24 JK TOGGLE WIITCH J = K = 1 J = 1 K = 1 JK LATCH T 1 IFF τ JKP > T 1 OUTPUT CHANGE ONLY ONCE PE CLO PEIO

25 MATE-LAVE FLIP-FLOP 25 J K NAN m m NAN s s UING NAN-BAE JK LATCHE J K m m s s

26 J K M M 26 J K M M GLITCH one s catching M n+1 = 1 M n = 0 n = 0 n+1 = 0 J K n n n+1 Operation n hold hold reset reset set set toggle toggle This Latch is Level ensitive!

27 CMO -LATCH AN EGE-TIGGEE FLIP-FLOP LATCH If = 1: n+1 = If = 0: n+1 = n - LATCH 27 V V -Latch Version 1

28 28 = 1 = 0

29 cycle time T 29 data stable t setup t hold t clock-to- t setup - time before the negative- edge the -input has to be stable. t hold - time after negative- edge that the -input has to remain stable. t clock-to- - elay from the negative- edge to new value of output.

30 METATABILITY AN YNCONIZATION FAILUE If data and clock do not satisfy the setup & hold time constaints of a register, then syncronization failure may occur. This due to inherent analog nature of storage elements. METATABLE TATE - indeterminate state between "1" & "0", i.e. latch is perfectly balanced between making decision for "1" or "0". In practice noise will eventually arbitrarily push latch output to "0" or "1". 30 Example: register entering metastable state (shown for negative edge trigger case) delay = 2.2 ns delay = 2.3 ns delay = 2.4 ns 4ns delay 2 ns = data time time metastable point time metastable point time

31 Negative - Latch 31 = 0 = 1 Positive - Latch = 1 = 0

32 32 V V V -Latch Version 2

33 POITIVE EGE - TIGGEE MATE-LAVE FLIP-FLOP 33 master slave m m s s FO = 0 m s 1. = 0: master m tracks current ; slave s = previous sample ( s is transparent to variations in ). FO = 1 m s 2. = 0 -> 1: master stores m = (new sample). 3. = 1: master passes m = to slave output s ( m and s are transparent to variations in ). 4. = 1 -> 0: slave locks in new, and master m begins tracking.

34 LEVEL/EGE-ENITIVE LATCH/EGITE TIMING 34 Negative Latch stored and available when low Positive Latch stored and available when high

35 35 m s master slave m s s stored when high and available when high and low