LTC Channel Analog Multiplexer with Serial Interface U DESCRIPTIO

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1 FEATRES -Wire Serial Digital Interface Data Retransmission Allows Series Connection with Serial A/D Converters Single V to ±V Supply Operation Analog Inputs May Extend to Supply Rails Low Charge Injection Low R ON : Ω Max Low Leakage: ±na Max Guaranteed Break-Before-Make TTL/CMOS Compatible for All Digital Inputs Cascadable to Allow Additional Channels Can Be sed as a Demultiplexer APPLICATI O S Data Acquisition Systems Communication Systems Signal Multiplexing/Demultiplexing DESCRIPTIO LTC -Channel Analog Multiplexer with Serial Interface The LTC is a high performance CMOS -to- analog multiplexer. It features a -wire digital interface with a bidirectional data retransmission feature, allowing it to be wired in series with a serial A/D converter while using only one serial port. The interface also allows several LTCs to be wired in series or parallel, increasing the number of MX channels available using only a single digital port. All the above features are also valid when LTC operates as a demultiplexer such as with a D/A converter. The LTC features a typical R ON of Ω, typical switch leakage of pa, and guaranteed break-before-make operation. Charge injection is ±pc maximum. All digital inputs are TTL and CMOS compatible when operated from single or dual supplies. The inputs can withstand ma fault currents. The LTC is available in -pin PDIP and narrow SO packages., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATI O V EE ON-Resistance vs Analog Input Voltage -WIRE SERIAL INTERFACE TO MX AND ADC S S S S S S S DATA LTC DATA OPTIONAL A/D INPT FILTER +IN LTC IN D OT V REF k LTC TA ON-RESISTANCE (Ω) T A = C V + = V = V V + = V = V INPT VOLTAGE, V S (V) LTC TA sn fs

2 LTC ABSOLTE AXI RATI GS W W W (Note ) Total Supply Voltage (V + to )... V Input Voltage Analog Inputs....V to V + +.V Digital Inputs....V to V Digital Outputs....V to V + +.V Power Dissipation... mw Operating Temperature Range... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR S S S S S S S N PACKAGE -LEAD PDIP TOP VIEW V + D DATA S PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = C/ W (N) T JMAX = C, θ JA = C/ W (S) W ATIO ORDER PART NMBER LTCCN LTC Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTI V + = V, = V, = V, T A = operating temperature unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Switch V Analog Signal Range (Note ) V R ON On Resistance V S = ±.V, I D = ma T MIN Ω C Ω T MAX Ω R ON vs V S % R ON vs Temperature. %/ C I S(OFF) Off Input Leakage V S = V, V D = V; V S = V, V D = V. ± na Channel Off ± na I D(OFF) Off Output Leakage V S = V, V D = V; V S = V, V D = V. ± na Channel Off ± na I D(ON) On Channel Leakage V S = V D = ±V. ± na Channel On ± na Input V INH High Level Input Voltage V + =.V. V V INL Low Level Input Voltage V + =.V. V I INL, I INH Low or High Level Current V IN = V, V IN = V ± µa V OH High Level Output Voltage V + =.V, I O = µa. V V + =.V, I O = µa.. V V OL Low Level Output Voltage V + =.V, I O =.ma.. V sn fs

3 LTC ELECTRICAL CHARACTERISTI V + = V, = V, = V, T A = operating temperature unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Dynamic f Clock Frequency MHz t ON Enable Turn-On Time V S =.V, R L = k, C L = pf ns t OFF Enable Turn-Off Time V S =.V, R L = k, C L = pf ns t OPEN Break-Before-Make Interval ns OIRR Off Isolation V S = V P-P, R L = k, f = khz db O INJ Charge Injection R S =, C L = pf, V S = V (Note ) ± ± pc C S(OFF) Source Off Capacitance pf C D(OFF) Drain Off Capacitance pf Supply I + Positive Supply Current All Logic Inputs Tied Together, V IN = V or V IN = V µa I Negative Supply Current All Logic Inputs Tied Together, V IN = V or V IN = V µa V + = V, = = V, T A = operating temperature unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Switch V Analog Signal Range (Note ) V R ON On Resistance V S =.V, I D = ma T MIN Ω C Ω T MAX Ω R ON vs V S % R ON vs Temperature. %/ C I S(OFF) Off Input Leakage V S =.V, V D =.V; V S =.V, V D =.V (Note ) ±. ± na Channel Off ± na I D(OFF) Off Output Leakage V S =.V, V D =.V; V S =.V, V D =.V (Note ) ±. ± na Channel Off ± na I D(ON) On Channel Leakage V S = V D =.V, V S = V D =.V (Note ) ±. ± na Channel On ± na Input V INH High Level Input Voltage V + =.V. V V INL Low Level Input Voltage V + =.V. V I INL, I INH Low or High Level Current V IN = V, V IN = V ± µa V OH High Level Output Voltage V + =.V, I O = µa. V V + =.V, I O = µa. V V OL Low Level Output Voltage V + =.V, I O = µa. V V + =.V, I O = µa.. V sn fs

4 LTC ELECTRICAL CHARACTERISTI V + = V, = = V, T A = operating temperature unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Dynamic f Clock Frequency MHz t ON Enable Turn-On Time V S =.V, R L = k, C L = pf (Note ) ns t OFF Enable Turn-Off Time V S =.V, R L = k, C L = pf (Note ) ns t OPEN Break-Before-Make Interval (Note ) ns OIRR Off Isolation V S = V P-P, R L = k, f = khz db O INJ Charge Injection R S =, C L = pf, V S = V (Note ) ± ± pc C S(OFF) Source Off Capacitance pf C D(OFF) Drain Off Capacitance pf Supply I + Positive Supply Current All Logic Inputs Tied Together, V IN = V or V IN = V. µa The denotes specifications which apply over the full operating temperature range. Note : Absolute maximum ratings are those beyond which the safety of the device may be impaired. Note : Guaranteed by design. Note : Leakage current with a single V supply is guaranteed by correlation with the leakage current of the ±V supply. Note : Timing specifications with a single V supply is guaranteed by correlation with the timing specifications of the ±V supply. TYPICAL PERFORMANCE CHARACTERISTI W ON-RESISTANCE (Ω) ON-Resistance vs Temperature V + = V = V V S =.V V + = V = V V S = V OTPT CRRENT (ma) Driver Output Low Voltage vs Output Current T A = C V + = V = V DATA OTPT CRRENT (ma) Driver Output High Voltage vs Output Current T A = C V + = V = V DATA TEMPERATRE ( C) OTPT VOLTAGE (V) OTPT VOLTAGE (V) LTC G LTC G LTC G PIN FNCTIONS to S (Pins to ): Analog Multiplexer Inputs/Analog Demultiplexer Outputs. (Pin ): Digital Ground. Connect to system ground. (Pin ): System Clock (TTL/CMOS Compatible). The clock synchronizes the channel selection bits and the serial data transfer from Data to Data. sn fs

5 LTC PIN FNCTIONS (Pin ): Chip Select Input (TTL/CMOS Compatible). A logic high on this input enables LTC to read in the channel selection bits and allow data transfer from Data to Data. A logic low enables the desired channel for analog signal transmission and allows data transfer from Data to Data. Data (Pin ): Bidirectional Digital Input/Output (TTL/ CMOS Compatible). Input for the channel selection bits. Data (Pin ): Bidirectional Digital Input/Output (TTL/ CMOS Compatible). (Pin ): Negative Supply. For ±V dual supply applications, should not exceed V + by more than % for proper channel selection. D (Pin ): Analog Multiplexer Output/Analog Demultiplexer Input. V + (Pin ): Positive Supply. W APPLICATIO S I FOR ATIO Multiplexer Operation Figure shows the block diagram of the components within the LTC required for MX operation. The LTC uses Data to select its channels and a chip select input to switch on the selected channel as shown in Figure. CONTROL LOGIC INPT -BIT SHIFT REGISTER MX BLOCK LTC F OTPT Figure : Simplified Block Diagram of the MX Operation When is high, the input data on the Data pin is latched into the -bit shift register on each rising clock edge. The input data consists of an EN bit and a string of three bits for channel selection. If EN bit is logic high as illustrated in the first input data sequence, it enables the selected channel. To ensure correct operation, the must be pulled low before the next rising clock edge. Once the is pulled low, all channels are simultaneously switched off to ensure a break-before-make interval. After a delay of t ON, the selected channel is switched on allowing signal transmission. The selected channel remains on until the next falling edge of, and after a delay of t OFF, it terminates the analog signal transmission and subsequently allows the selection of the next channel. If EN bit is logic low, as illustrated in the second data sequence, it disables all channels and there will be no analog signal EN = HIGH EN = LOW B B B B B B ANY D t ON t OFF LTC F Figure : Multiplexer Operation sn fs

6 LTC W APPLICATIO S I FOR ATIO transmission. Table shows the various bit combinations for channel selection. Table. Logic Table for Channel Selection CHANNEL STATS EN B B B All Off X X X S S S S S S S Digital Data Transfer Operation The block diagram of Figure shows the components contained within the LTC required for digital data transfer. Digital data transfer operation can be performed from Data to Data and vice versa as shown in Figure. When is high, Buffer is enabled and Buffer is disabled. The digital input data is fed into the -bit shift register and then shifted to the MX switches for channel DATA Hi-Z -BIT SHIFT REGISTER DATA OT DATA IN BFFER BFFER DATA IN MX SWITCHES Figure. Simplified Block Diagram of the Digital Data Transfer Operation Figure. Digital Data Transfer Operation DATA LTC F DATA OT LTC F selection or to Data via Buffer for data transfer. Data appears at Data after the fourth rising edge of the clock. When is low, Buffer is enabled and Buffer is disabled, thus digital input data is directly transferred from Data to Data without any clock delay. Multiplexer Expansion Several LTCs can be daisy-chained to expand the number of multiplexer inputs. No additional interface ports are required for the expansion. Figure shows two LTCs connected at their analog outputs to form a - to- multiplexer at the input to an LTC A/D converter. S S S S S S S S S S S S S S LTC A LTC B V + D DATA V + D DATA V EE Figure. Daisy-Chaining Two LTCs for Expansion To ensure that only one channel is switched on at any one time, two sets of channel selection bits are needed for Data as shown in Figure. The first data sequence is used to switch off one MX and the second data sequence is used to select one channel from the other MX, or vice versa. In other words, if bit ENA is high and bit ENB is low, one channel of MX A is switched on and all channels of MX B are switched off. If bit ENA is low and bit ENB is high, all channels of MX A are switched off and one channel of MX B is switched on. V REF +IN LTC IN D OT DATA k LTC F sn fs

7 LTC W APPLICATIO S I FOR ATIO DATA ENA NLL A A A ENB B B B BIT D D D D D D D D D D D D Hi-Z t SMPL t CONV t DATA DIGITAL INPT FROM LTC DIGITAL OTPT FROM LTC LTC F Figure. Timing Diagram for Figure TYPICAL APPLICATIONS N BYPASS CAPACITOR FROM V + TO AND TO REQIRED FOR EACH LTC Daisy-Chaining Five LTCs S S S S S S S LTC A DATA V EE V REF +IN LTC IN D OT k S S S S S S S S S S S S S S LTC B LTC C DATA DATA S S S S S S S S S S S S S S LTC D LTC E DATA DATA V EE DATA* * REQIRES FIVE -BIT CHANNEL SELECTION DATA BYTES Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. LTC TA sn fs

8 LTC TYPICAL APPLICATIONS N Interfacing LTC with LTC for Demultiplex Operation V EE OPTIONAL D/A OTPT FILTER OTPTS S S S S S S S LTC DATA k LTC D IN V OT LOAD D OT V REF DATA LTC F PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted... (..). ±. (. ±.) N Package -Lead Plastic DIP.. (..).* (.) MAX.. (..) ( ). (.) MIN. (.) MIN. ±. (. ±.). ±. (. ±.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm).. (.) TYP. ±. (. ±.). ±.* (. ±.).. (..).. (..) TYP.. (..) S Package -Lead Plastic SOIC.. (..)..* (..) (..). (.) TYP.. (..)..* (..) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTCA/LTC/LTC Micropower, Low Charge Injection, Quad CMOS Analog Switches Each Channel is Independently Controlled LTC/LTC Micropower, Low Charge Injection, Quad CMOS Analog Switches Parallel Controlled with Data Latches with Data Latches LTCx/LTCx Serial A/Ds with Integral MXs Linear Technology Corporation McCarthy Blvd., Milpitas, CA - () - FAX: () - TELEX: - sn fs LT/GP K PRINTED IN THE SA LINEAR TECHNOLOGY CORPORATION

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