Chapter 9 Semiconductor Memories. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Transcription

1 Chapter 9 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Outline Introduction Random Access Memories Content Addressable Memories Flash Memories

3 Overview of Memory Types Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Semiconductor Memories Read/Write Memory or Random Access Memory (RAM) Read Only Memory (ROM) Random Access Memory (RAM) Static RAM (SRAM) Dynamic RAM (DRAM) Register File Non-Random Access Memory (RAM) FIFO/LIFO Shift Register Content Addressable Memory (CAM) Mask (Fuse) ROM Programmable ROM (PROM) Erasable PROM (EPROM) Electrically EPROM (EEPROM) Flash Memory Ferroelectric RAM (FRAM) Magnetic RAM (MRAM)

4 Memory Elements Memory Architecture Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 Memory elements may be divided into the following categories Random access memory Serial access memory Content addressable memory Memory architecture row decoder row decoder row decoder row decoder 2 m+k bits 2 n-k words k column decoder n-bit address m-bit data I/Os column mux, sense amp, write buffers

5 1-D Memory Architecture Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 S 0 S 1 Word 0 Word 1 S 0 S 1 Word 0 Word 1 S 2 S 3 Word 2 A 0 A 1 A k-1 Decoder S 2 S 3 Word 2 S n-2 Word n-2 Storage element S n-2 Word n-2 S n-1 Word n-1 S n-1 Word n-1 m-bit Input/Output m-bit Input/Output n select signals: S 0 -S n-1 n select signals are reduced to k address signals: A 0 -A k-1

6 2-D Memory Architecture Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 S 0 Word 0 Word i-1 S 1 A 0 A 1 A k-1 Row Decoder S n-1 Word ni-1 A 0 A j-1 Column Decoder Sense Amplifier Read/Write Circuit m-bit Input/Output

7 Row Column Block 3-D Memory Architecture Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 Input/Output

8 Conceptual 2-D Memory Organization Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8 Address Row Decoder Memory Cell Column decoder Data I/Os

9 Memory Elements RAM Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9 Generic RAM circuit Bit line conditioning Clocks RAM Cell n-1:k k-1:0 Sense Amp, Column Mux, Write Buffers Write Clocks Address write data read data

10 RAM SRAM Cells Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10 6-T SRAM cell word line 4-T SRAM cell bit - bit word line bit - bit

11 RAM DRAM Cells Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11 4-T dynamic RAM (DRAM) cell word line 3-T DRAM cell Read Write bit - bit Write data Read data

12 RAM DRAM Cells Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12 1-T DRAM cell word line word line Vdd or Vdd/2 bit bit Layout of 1-T DRAM (right) Vdd word line bit

13 RAM DRAM Retention Time Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13 Write and hold operations in a DRAM cell WL=1 WL=0 Input Vdd + - on C s + - V s off C s + - V s Write Operation Hold V Q s = max V max = C s = V ( V DD DD V V tn tn )

14 RAM DRAM Retention Time Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14 Charge leakage in a DRAM Cell WL=0 V max V s (t) off I L C s + - V s (t) V 1 t h Minimum logic 1 voltage t I I I t L L L h dq s = ( ) dt dv s = C s ( ) dt V s C s ( ) t C s = t ( ) V I L s

15 RAM DRAM Refresh Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the hold time is t h = 1 = 0.5µs Memory units must be able to hold data so long as the power is applied. To overcome the charge leakage problem, DRAM arrays employ a refresh operation where the data is periodically read from every cell, amplified, and rewritten. The refresh cycle must be performed on every cell in the array with a minimum refresh frequency of about f refresh 1 2t h

16 RAM DRAM Read Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16 WL=1 C bit + - V bit on V f I L C s + - V s V f Q Q V s s f = = = C C s s ( C V V s s f C + + C s C bit bit V ) V s f This shows that V f <V s for a store logic 1. In practice, V f is usually reduced to a few tenths of a volt, so that the design of the sense amplifier becomes a critical factor

17 RAM SRAM Read Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17 Vdd precharge precharge precharge bit, -bit word line word data -bit bit data

18 RAM SRAM Read Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18 Vdd-Vtn precharge precharge Vdd precharge bit, -bit word line word data -bit bit data

19 RAM SRAM Read Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19 bit, -bit word data -bit bit load V 2 sense + sense - pass sense common V 1 pulldown

20 RAM Differential Amplifier Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20 Vdd d se Mp1 f I d1 I d1 I d2 d Mn1 Mn2 I SS Mn Mp2 I I d2 I d1 I SS I d2 0 d d I SS =I d1 +I d2

21 RAM Write Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21 N 5 N 6 word write data write N 3 N 4 word -bit bit bit, -bit write N 1 N 2 write data cell, -cell

22 RAM Write Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22 P bit -bit bit 5V -cell cell 0V N bit -write write N D P D write-data

23 RAM Row Decoder Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23 word<3> word<0> word<2> word<1> word<1> word<2> word<0> word<3> a<1> a<0> a<1> a<0>

24 RAM Row Decoder Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24 word a1 a0 a0 a1 a2 a3 Complementary AND gate Pseudo-nMOS gate

25 RAM Row Decoder Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25 Symbolic layout of row decoder Vss Vdd output Vss

26 RAM Row Decoder Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26 Symbolic layout of row decoder Vdd output Vss a3 -a3 a2 -a2 a1 -a1 a0

27 RAM Row Decoder Predecode circuit word<7> word<6> word<5> word<4> word<3> word<2> word<1> word<0> a2 a1 a0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

28 RAM Row Decoder Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28 Actual implementation a0 a4 a3 a2 a1 word -a0 clk Pseudo-nMOS example a0 word a1 a2 en

29 RAM Column Decoder Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29 bit<7> bit<6> bit<5> bit<4> selected-data bit<3> bit<2> bit<1> bit<0> -bit<7> -bit<6> -bit<5> -bit<4> -bit<3> -bit<2> -bit<1> -bit<0> to sense amps and write ckts -selected-data a0 -a0 a1 -a1 a2 -a2

30 RAM Multi-port RAM Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30 write read0 read1 -rbit1 -rbit0 -rwr_data rwr_data rbit0 rbit1 write read0 read1 -rbit1 -rwr_data rwr_data rbit0

31 RAM Expandable Reg. File Cell wr-b addr<3:0> rd-a addr<3:0> rd-b addr<3:0> write-data write-data read-data 0 read-data 1 write-enable(row) read0 read1 Write-enable (column) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

32 Specific Memory FIFO Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32 Two port RAM Write-Data Read-Data Write-Address Read-Address Write-Clock Full Read-Clock Empty FIFO read address control design WP Read rst clk incrementer

33 Specific Memory FIFO Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33 FIFO address control design decrementer Read rst clk 1 incrementer Read Write Empty Full

34 Specific Memory LIFO Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34 LIFO (Stack) Require: Single port RAM One address counter Empty/Full detector Address Algorithm: Write: write current address Address=Address+1 Read: Address=Address-1 read current address Empty: Address=0 Full : Address=FFF

35 Specific Memory SIPO Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35 SIPO cell design Read Parallel-data Sh-In Sh-Out Clk -Clk SIPO Read Sh-In Clk

36 Specific Memory Tapped Delay Line Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36 delay<5> delay<4> delay<3> delay<2> delay<1> delay<0> din dout Clk 32-stage SR 16-stage SR 8-stage SR 4-stage SR 2-stage SR 1-stage SR

37 Non-volatile Memory ROM Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37 4x4 NOR-type ROM V dd WL0 WL1 GND WL2 GND WL3 BL0 BL1 BL2 BL3

38 Non-volatile Memory ROM Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38 4x4 NAND-type ROM V dd WL0 BL0 BL1 BL2 BL3 WL1 WL2 WL3

39 Specific Memory CAM Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39 Content addressable memories (CAMs) play an important role in digital systems and applications such as communication, networking, data compression, etc. Each storage element of a CAM has the hardware capability to store and compare its contents with the data broadcasted by the control unit CAM types dynamic or static binary or ternary The binary static CAM is discussed

40 Difference Between RAM and CAM Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40 Address RAM Data R/W Data Cmd CAM Hit Address

41 CAM Applications CAM architecture Data CAM Memory Array NxM-bit words Match Cache architecture Data In CAM CAM Memory Array NxM-bit words Match 0 Match 1 Match 2 Match 3 Match 4 Match 5 RAM Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Data I/Os Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41

42 CAM Architecture Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42 Comparand Register Mask Register ddress Input Address Decoder Memory Array Valid Bit Responder Hit Address Output I/O Register

43 CAM Basic Components Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43 Comparand Register It contains the data to be compared with the content of the memory array Mask Register It is used to mask off portions of the data word(s) which do not participate in the operations Memory Array It provides storage and search (compare) medium for data Responder It indicates success or failure of a compare operation

44 CAM Binary Cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44 CAM cell -bit bit WL -d d M2 M1 Match M3

45 CAM Word Structure Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45 bit[0] bit[0] bit[w-1] bit[w-1] i 1 0 Vdd P M i comparison logic 10 10

46 CAM Organization Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46 CAM circuit Match Data In Read Data (Test) Normal RAM Read/Write Circuitry Hit Match0 Match1 Match2 precharge Match3

47 Non-volatile Memory Flash Memory Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47 Flash memory A nonvolatile, in-system-updateable, high-density memory technology that is per-bit programmable and per-block or per-chip erasable In-system updateable A memory whose contents can be easily modified by the system processor Block size The number of cells that are erased at the same time Cycling The process of programming and erasing a flash memory cell

48 Flash Memory Definition Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48 Erase To change a flash memory cell value from 0 to 1 Program To change a flash memory cell value from 1 to 0 Endurance The capability of maintaining the stored information after erase/program/read cycling Retention The capability of keeping the stored information in time

49 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49 Basics How can a memory cell commute from one state to the others independently of external condition? One solution is to have a transistor with a threshold voltage that can change repetitively from a high to a low state The high state corresponding to the binary value 1 The low state corresponding to the binary value 0 Threshold voltage of a MOS transistor V T = K Q' / C ox K is a constant depending on the gate and substrate material, doping, and gate oxide thickness Q is the charge in the gate oxide C ox is the gate oxide capacitance

50 Floating Gate Transistor Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50 Floating gate (FG) transistor Control Gate C FC Floating Gate Source C FS C FB Substrate Drain C FD Energy band diagram of an FG transistor Substrate Floating Gate Control Gate

51 Flash Memory Threshold Voltage Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51 When the voltages (V CG & V D ) are applied to the control gate and the drain, the voltage at the floating gate (V FG ) by capacitive coupling is expressed as QFG C FC C FD V FG = + VCG + VD Ctotal Ctotal Ctotal C total = CFC + CFS + CFB + CFD The minimum control gate voltage required to turn on the control gate is Ctotal QFG CFD VT ( CG) = VT ( FG) VD CFC CFC CFC where V T (FG) is the threshold voltage to turn on the floating gate transistor The difference of threshold voltages between two memory data states ( 0 and 1 ) can be expressed as Q FG VT ( CG) = C FC

52 Flash Memory Structures Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 52 Two major flash memory structures NOR & NAND NOR structure Simplest Dual power supply Large block size NAND structure Intermediate block size High-speed and high density For storage applications

53 Flash Memory Structures Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 53 WL 1 Bit line Basic unit Select gate (drain) Bit line Basic unit WL 2 WL 3 WL 1 WL 2 WL 3 WL 4 WL N Source line NOR structure WL N Select gate (source) NAND structure

54 Flash Memory Program Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 54 Program operation of the Intel s ETOX flash cells (NOR structure) Apply 6V between drain and source Generates hot electrons that are swept across the channel from source to drain Apply 12 V between source and control gate The high voltage on the control gate overcomes the oxide energy barrier, and attracts the electrons across the thin oxide, where they accumulate on the floating gate Called channel hot-electron injection (HEI) +12V Control Gate GND Floating Gate +6V Source Substrate Drain

55 Flash Memory Erase Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 55 Erase operation of the Intel s ETOX flash cells (NOR structure) Floating the drain, grounding the control gate, and applying 12V to the source A high electric field pulls electrons off the floating gate Called Fowler-Nordheim (FN) tunneling GND +12V Control Gate Floating Gate Source Drain Substrate

56 Flash Memory Erase Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 56 Threshold voltage depends on oxide thickness Flash memory cells in the array may have slightly different gate oxide thickness, and the erase mechanism is not self-limiting After an erase pulse we may have typical bits and fast erasing bits V T typical bit fast erasing bit 0 log t

57 Flash Memory Read Operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 57 Read operation of the Intel s ETOX flash cells (NOR structure) Apply 5V on the control gate and drain, and source is grounded In an erased cell, the V C >V T The drain to source current is detected by the sense amplifier In a programmed cell, the V C <V T The applied voltage on the control gate is not sufficient to turn it on. The absence of current results in a 0 at the corresponding flash memory output +5V GND Source Control Gate Floating Gate +5V Drain Substrate