Digital Logic Design: Sequential Logic Page 304. CLOCK Input. Output. F 1 Output. F 2 Output. F 3 Output. t 2. t 7. t 9. t 6. t 1. t 8. t 5. t 10.

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1 Timing diagram of a Synchronous Decade Counter The output of the first flip-flop is seen to toggle between states 0 and 1 at each negative clock transition. Therefore, the timing diagram confirms that the inputs J-K of the first flip-flip have to be permanently connected to logic 1. The output of the second flip-flop F 1 changes its state at interval t 2, t 4, t 6 and t 8 when F 0 output is logic 1 and F 3 output is logic 0. The timing diagram confirms that the inputs of the second flip-flop have to be connected to a logic circuit having an output determined by the Boolean expression F. The output F 2 of the third flip-flop changes its state during intervals t 4 and t 8 when 0 F 3 F 0 and F 1 outputs are at logic 1. The timing diagram confirms the logic circuit implemented using an AND gate having inputs F 0 and F 1, the output of which is connected to the J-K inputs of the third flip-flop. Finally, the output F 3 of the fourth flipflop changes its state at interval t 8 when the outputs F 0, F 1 and F 2 are all at logic 1. The output F 3 also changes its state at interval t 10 when F 0 and F 3 are at logic 1. The circuit using a combination of AND gates and OR gates implements the Boolean function F 0 F1 F2 + F0F3. CLOCK Input F 0 Output F 1 Output F 2 Output F 3 Output t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 Figure 28.1 Timing diagram of a Synchronous Decade Counter Mod-n Synchronous Counter A Mod-n Synchronous can be implemented using appropriate number of J-K flipflops connected together with their clocks triggered simultaneously. A synchronous counter which counts a truncated sequence of n unique states can be similarly implemented. The Modulus number represents the unique number of states which the Digital Logic Design: Sequential Logic Page 304

2 counter counts in a sequence. The Modulus number determines the number of flip-flops required based on the relation n = 2 m where m is the number of flip-flops. Integrated Circuit Synchronous Counters Instead of connecting a large number of flip-flops together to form large Synchronous counters, counter circuits available in Integrated Circuit form can be quickly connected to form large counters. The 74HC163 is a 4-bit Synchronous Counter. Figure The counter has the following pins. 1. Parallel data inputs D 0, D 1, D 2 and D 3 2. Data outputs Q 0, Q 1, Q 2 and Q 3 3. Positive edge-triggered CLOCK signal 4. Active-low input which resets the Counter output to Active-low input which loads the 4-bit data applied at the counter inputs 6. Active-high ENT and ENP enable inputs. For the counter to operate both the enable inputs have to be high 7. The Ripple Clock Output RCO goes high when the Counter reaches the terminal count The RCO output along with ENT and ENP enable input pins are used to cascade multiple counter ICs for implementing larger counters D 0 D 1 D 2 D 3 ENT ENP CLK 74HC163 RCO Q 0 Q 1 Q 2 Q 3 Figure 28.2a 74HC163 4-bit Synchronous Counter Referring to the timing diagram, the signal is activated between interval t 0 and t 1. The counter output is reset synchronously at interval t 1 as the signal is active at interval t 1. If the signal is deactivated before interval t 1 then the counter output is not reset. The signal is activated between interval t 1 and t 2. At the clock transition at t 2, the counter is loaded with the 4-bit data applied at the inputs D 0, D 1, D 2 and D 3. The ENP and ENT enable signals are activated before interval t 3 and the counter increments to the higher count at clock transition at intervals t 3 and t 4. When the counter reaches the count 15 at interval t 4, the RCO (Ripple Clock Output) is set to high Digital Logic Design: Sequential Logic Page 305

3 indicating that terminal count has been reached. At intervals t 5, t 6, t 7 and t 8 the counter successively counts to 0, 1, 2 and 3. The counter enable signal ENP is deactivated after interval t 8, which inhibits the counter from counting any further. Figure 28.2b Timing diagram of the 74HC163 Synchronous counter The 74HC160 is a 4-bit Synchronous Decade counter with the same input and output pins as the 74HC163. The RCO output of the decade counter is activated when the counter reaches its terminal count Digital Logic Design: Sequential Logic Page 306

4 Cascading Counters It is very convenient to cascade Integrated Circuit counters together to form larger counters instead of connecting together flip-flops to implement a large counter. The enable inputs and Ripple Clock Outputs of the Integrated Circuit counters allow cascading of multiple counters together. Two, 74HC160 decade counters are shown connected together to divide the input frequency by 10 and 100. Figure The 74HC163 can also be similarly cascaded together. Figure 28.3a Cascaded Decade Counters Figure 28.3b Timing diagram of a Cascaded Decade Counter Digital Logic Design: Sequential Logic Page 307

5 In the timing diagram, at interval t 9 the first decade counter reaches the terminal count The RCO output of the counter is set to logic 1. The RCO of the first counter is connected to the ENP and ENT enable pins of the second counter, therefore the counter is enabled. At interval t 10 on a positive clock transition the first counter increments to count Since the second counter is also enabled, it is incremented to As soon as the first counter is incremented to 0000, the ECO signal is deactivated which in-turn also inhibits the second counter. The first counter counts from 0001 to 1000 in the intervals t 11 to t 19. At interval t 19 the first counter again reaches its terminal count 1001, the RCO output of counter once again becomes active thereby activating the second counter. At interval t 20 on a positive clock transition the first and second counters increment to count 0000 and 0010 respectively. The RCO signal is again deactivated inhibiting the second counter from counting. This sequence continues after the first counter reaches its terminal count. Integrated Circuit Counters with Truncated Sequences Earlier, a decade counter was implemented by truncating the counting sequence of a MOD-16 counter. The Integrated Circuit Counters can also be configured as MOD-n counters where n represents the truncated sequence and is less than 16. Figure 28.4 shows the circuit diagram of the 74HC163 counter configured as Mod-7 counter. The counter is preset with the count value 1001 by setting the /NORMAL input to logic 1 at the NOR gate input. At the positive clock transition t 1, the count value is loaded. The counter increments and at interval t 7 it reaches the terminal count. The RCO output is set to logic 1 which sets the input to logic 0. At the positive clock transition at interval t 8 the preset value 1001 is reloaded and the counter continues its counting sequence. /NORMAL 1/0 D 0 D 1 D 2 D V CLK ENT ENP 74HC163 RCO Q 0 Q 1 Q 2 Q 3 Figure 28.4a 74HC163 configured as Mod-7 counter Digital Logic Design: Sequential Logic Page 308

6 Figure 28.4b The timing diagram of a truncated Mod-7 Counter Another method to configure an Integrated Circuit counter is to reset the counter when it reaches the maximum count value of its truncated sequence. This requires extra logic in the form of logic gates that determine the terminating state and reset the counter. The circuit diagram of the counter is shown. Figure 28.5 /NORMAL 1/0 D 0 D 1 D 2 D 3 +V ENT ENP 74HC161 RCO CLK Q 0 Q 1 Q 2 Q 3 Figure 28.5a 74HC161 configured as Mod-9 counter Digital Logic Design: Sequential Logic Page 309

7 Figure 28.5b Timing diagram of a 74HC161 configured as Mod-9 counter The counter used is 74HC161 instead of 74HC163. The 74HC161 has an Asynchronous Clear input, where as the 74HC163 counter has a synchronous Clear input. At time interval t 9 the counter increments to 1001 which sets the output of the AND gate to logic 1. The NOR gate output is set to logic low which activates the clear input and resets the counter to The 74HC163 counter which has a synchronous clear input, will reset counter resets at interval t 10 when there is a transition at the clock input. It is clear from the timing diagram that to implement a Mod-9 counter the 74HC161 instead of 74HC163 counter has to be used. Cascaded Counters with Truncated Sequences Cascaded counters can also be configured to count in a truncated sequence. The circuit diagram of three cascaded 74HC163 is shown. Figure The 12-bit cascaded counter is loaded with initial count value When the counter counts to , the RCO output set to logic 1 by the third counter reloads the initial count values 0000, 0000 and 1000 in all the three counters respectively. The 12-bit counter can be configured for maximum count sequence as Modulus 4096 counter. The counter has been configured to count from to that is 2048 states or Modulus 2048 counter. Digital Logic Design: Sequential Logic Page 310

8 Figure HC163 counters connected for cascaded truncated count sequence Up-Down Counter An up-down counter can increment its output count value at each clock transition or decrement its count value at each clock transition, depending upon the count mode it is configured in. The counter can be reconfigured to count in the opposite direction during its count sequence. The circuit of an up-down 3-bit counter can be developed by studying the up-down count sequence of the counter. Table Clock Pulse Q 2 Q 1 Q Table 28.1a Up-counting sequence of a 3-bit Synchronous Counter Clock Pulse Q 2 Q 1 Q Table 28.1b Down-counting sequence of a 3-bit Synchronous Counter Digital Logic Design: Sequential Logic Page 311

9 A 3-bit Synchronous up-counter has been discussed earlier. Consider the implementation of down-counter, the up and down counter can be combined to form a single configurable up-down counter. For the down-counting sequence the output Q 0 of the first flip-flop toggles between 0 and 1, therefore the J-K inputs are connected to logic 1. The output Q 1 of the second flip-flop toggles between logic 0 and 1 when the Q 0 output is logic 0 orq0 is logic 1. The output Q 2 of the third flip-flop toggles when Q 0 and Q 1 outputs are both logic 0 or Q0 and Q1 are both logic 1. Digital Logic Design: Sequential Logic Page 312