4/26/2011. Digital Logic and Design (EEE-241) Lecture 14. Previous lecture. Triggering of Flip-Flop

Transcription

1 //0 Digital Logic and Design (EEE-) Lecture Dr. M. G. Abbas Malik Picture ource: Previous lecture Introduction to equential Circuits Types of equential Circuits Asynchronous equential Circuits ynchronous equential Circuits Memory Elements (flip-flops) flops) Basic flip-flop Clocker flip-flop D flip-flop JK flip-flop T flip-flop (self study) The state of a flop-flop is switched by a momentary change in the input signal. The momentary change is called a trigger and the transition it causes is said to trigger the flipflop. Asynchronous flip-flops, the basic flip-flops, require an input trigger defined by a change of signal level. ( in the NO and 0 in the NAND to acquire et-state) This level must be returned to its initial value (0 in the NO and in the NAND) before the next trigger is applied.

2 //0 Clocked flip-flop are triggered by pulses. A pulse starts from an initial value of 0, goes momentarily to and after short time, returns to its initial value 0. 0 The time interval from the application of the pulse until the output transition occurs is a critical factor. A sequential circuit has a feed-back path between the combinational circuit and the memory element. This path can produce instability, if the outputs of memory element are changing while the outputs t of the combinational circuit it that t go to flipflop inputs are being sampled by the clock pulse. Inputs Combination Circuit Memory Element outputs equential Circuit This timing problem can be prevented if the output of flip-flop do not start changing until the pulse input has returned to 0. To ensure such an operation, a flip-flop must have a signal propagation delay from the input to output in excess of the pulse duration. Inputs Combination Circuit Memory Element outputs equential Circuit

3 //0 This delay is usually very difficult to control, if the designer depends entirely on the propagation delay of logic gates. One way to ensure the proper delay is to include within the flip-flop flop circuit a physical delay unit having a delay equal to or greater than the pulse duration. A better way to solve the feed-back timing problem is to make the flip-flop sensitive to the pulse transition rather than the pulse duration. 7 8 Clock Pulse A Clock Pulse may be either Positive or Negative Positive Pulse A positive clock source remains Positive Pulse at 0 during the interval between pulses and goes to during the occurrence of a pulse Pulse goes through two signal transitions: 0 to positive transition 0 to 0 negative transition Positive transition is defined as Positive Edge. Negative transition is defined as Negative Edge. Positive Edge Negative Edge Clock Pulse A Clock Pulse may be either Positive or Negative Negative Pulse A negative clock source Negative Pulse remains at during the interval between pulses and goes to 0 during the occurrence of a pulse 0 Negative Edge Positive Edge 9

4 //0 The clocked flip-flops, studied so far, are triggered during the positive edge of the pulse, and the state transition starts as soon as the pulse reaches the logic level. The new state of the flip-flop flop may appear at the output terminal while the input pulse is still. If the other inputs of the flip-flop change while the clock pulse is still, the flip-flop will start responding to these new values and new output state may occur. 0 When this happens, the output of one flip-flop cannot be applied to the inputs of another flip-flop when both are triggered by the same clock pulse. However, if we can make the flip-flop respond to the positive (or negative) edge transition only, instead of the entire pulse duration, then the multiple-transition problem can be eliminated. One way to make the flip-flop respond only to a pulse transition is to use capacitive coupling. In this configuration, an C (resistor-capacitor) circuit is inserted in the clock pulse input of the flipflop. This circuit generates a spike in response to a momentary change of input signal. A positive edge emerges from such a circuit with a positive spike, and a negative edge emerges with a negative spike. Edge triggering is achieved by designing the flip-flop to neglect one spike and trigger on the occurrence of the other spike.

5 //0 The other way to achieve edge triggering is to use a master-slave or edge triggered flip-flop. A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a master and the other as a slave. Master lave Master-lave Flip-Flop The logic diagram shows an Master-lave flip-flop. It consists of a master flip-flop, a slave flip-flop and an inverter. When CP is 0, the output of inverter is. ince the clock input of the slave is, the flip-flop flop is enabled and output is equal to. Master lave Master-lave Flip-Flop The Master flip-flop is disables because CP=0. When CP becomes, the information at the external and inputs is transmitted to the master flip-flop and it produces the outputs and according to the input values. The slave flip-flop is disabled as long as CP=. Master lave Master-lave Flip-Flop

6 //0 As soon as the CP returns to 0, the master flipflop is disabled that prevents the external inputs from affecting the outputs of master and lave flip-flop is now enabled and master s outputs and are transmitted to external outputs and respectively. Master lave Master-lave Flip-Flop The triggering of Master-lave flip-flop (shown below) coincide with the negative edge transition. A positive edge transition triggering flip-flop can be made by introducing another inverter between the CP and Master flip-flop flop. 7 Master lave Master-lave Flip-Flop Master-lave combination can be constructed for any type of flip-flop by adding a clocked flipflop with an inverted clock to form the slave. Example: Master-lave JP flip-flop with NAND J 7 K 8 9 8

7 //0 Consider a digital system with many master-slave flipflops with the outputs of some going to the inputs of others. Assume that clock pulse inputs to all flip-flops are synchronized. At the beginning of each pulse, some of the master elements change state, but all flip-flop outputs remain at their previous values. After the clock pulse returns to 0, some of the outputs change state, but non of these new states have an effect on any of the master elements until the next clock pulse. 9 It is possible that the state of flip-flops in the system can be changed simultaneously during the same clock pulse, even through outputs of flip-flops are connected to inputs of other flip-flops. It is possible because the new state appears at the output terminals only after clock pulse has returned to 0. Therefore the binary contents of one flip-flop can be transferred to a second flip-flop and vice versa; Both transfer can occur during the same clock pulse. 0 Another type of flip-flop that synchronizes the state changes during a clock pulse transition is the Edge- Triggered flip-flop. In this type of flip-flop, output transitions occur at a specific level of the clock pulse. When the pulse input level exceeds this threshhold level, the inputs are locked out and the flip-flop is therefore unresponsive to further changes in inputs until the clock pulse returns to 0 and another pulse occurs. Edge Triggered flip-flops cause a transition on either the positive edge or negative edge of the pulse. 7

8 //0 D-type positive edge triggered flip-flop D D-type positive edge triggered flip-flop With CP=0 and D=0 = =0 = D=0 D-type positive edge triggered flip-flop With CP=0 and D= = =0 = D= 8

9 //0 D-type positive edge triggered flip-flop With CP= and D=0 = = =0 D=0 D-type positive edge triggered flip-flop With CP= and D= =0 = = D= Direct Inputs Flip-flops available in IC packages sometimes provide special inputs for setting or clearing the flip-flop asynchronously. These inputs are called Direct preset and Direct clear. They affect the flip-flop on a positive (or negative) value of the input signal without the need for a clock pulse. These inputs are useful for bringing all flip-flops to an initial state prior to their clocked operation. 7 9

10 //0 Direct Inputs JK flip-flop with direct clear Clear K J Inputs Outputs Clear Clock J K 0 X X X No Change Toggle 8 0