Chapter 3 Lecture 3 The Digital Logic Level

Transcription

1 Chapter 3 Lecture 3 The Digital Logic Level Level 0: The basic building blocks and foundation of the computer: 3.1 Gates And Boolean Algebra 3.2 Basic Digital Logic Circuits 3.3 Memory 3.4 CPU Chips And Buses 3.5 Example CPU Chips 3.6 Example Buses 3.7 Interfacing Basic Digital Logic Circuits (and Functions) Combinational Circuits Decoders Multiplexers Comparators Programmable Logic Arrays Arithmetic Circuits Adders Shifters Arithmetic Logic Units (ALU) Multipliers Latches, Flip-Flops and the Clock Glitch Generator Set-Reset Latch Gated SR Latch Gated D Latch The clock glitch (pulse) generator (only to be used by experts) D Flip Flop Synchronous Register Writing 1 of 22 ECE 357

2 Latches, Flip-Flops and the Clock Glitch Generator Set-Reset Latch Set-Reset Latch Gated SR Latch Gated SR Latch Note: The text calls this a clocked SR latch. It is not!!! It is a Gated SR Latch!!! (You must know the difference as I will grade accordingly!) The gate is an enable signal that allows the latch to arrive at a value based on R and S during the gate time. After that, it is latched until the gate opens again. The final value of the circuit is directly related to the gate width and propagation delays of the signals. RACE CONDITION DEPENDENT DESIGNS ARE BAD DESIGNS. 2 of 22 ECE 357

3 Gated D Latch Gated D Latch Note: The text calls this a clocked D latch. I strongly disagree!!! (and I will grade accordingly!) The gate is an enable signal that allows the latch to arrive at a value based on D during the gate time. After that, it is latched until the gate opens again. The final value of the circuit is directly related to the gate width and propagation delays of the signals. Repeat: RACE CONDITION DEPENDENT DESIGNS ARE BAD DESIGNS. Gating Functions Gating functions are great for capturing or sampling and then holding real world events. All high speed analog-to-digital converters use sample and hold devices prior to conversion. Use them when a gate period in time can be readily defined and created in the circuit. Yes, a clock half cycle can be used for gating purposes. When using a gated device, there is a chance the signal being sampled will change very close the end of the gate. If this can happen, it is likely that it will happen! The rest of the circuit design must be prepared to accept this possibility and also expect a higher probability that metastability will occur the circuit. Metastability produces unexpected (not designed) circuit output behavior and may cause the circuit to be damaged or destroyed. 3 of 22 ECE 357

4 The clock glitch generator (only to be used by experts, all others should be fired!) Generating a glitch in a circuit based on silicon and operating condition dependent delay signals You will always get a glitch, but how big is it? And, can it be used? The idea can work based on the gates and technology, but the implementation is only done by those (1) with no experience (clueless and dangerous) and (2) that are expert designers who have worked out every possible failure. You are not expert designers; therefore, this approach is wrong and should NEVER BE USED. Two phase clocking (when a predictable delay is available). Phase 1 Phase 2 The concept of creating reliable periodic signals. 4 of 22 ECE 357

5 D Flip Flops and Latches Symbolic: Gated D-Latches versus Clocked D-FF (a) Gated D-FF, (b) Inverted Gate D-FF, (c) Positive-Edge Clocked D-FF, and (d) Negative-Edge Clocked D-FF Typical 7474 Dual D-Flip Flop Symbol and Pin-Out Ancient 7474 Logic Diagram and Function Table 5 of 22 ECE 357

6 Timing Considerations Critical Timing Considerations: Clock to Output, Setup and Hold Clock-to-output Setup Time Hold Time The use of a multiplexed, clocked D flip-flop A Mux D Q Q Din B Sel D-FF Select Clock Please use this as Bit/Byte Registers in your computer designs!!! (Think full credit versus partial or no credit like glitch-based clocking) Note: Select and Din add to the setup-time of the D-FF and reduce the hold-time. 6 of 22 ECE 357

7 Super-Synchronous Design All digital signals are output by clock driven synchronous devices and are received (after combinatorial logic) by clock driven synchronous devices. DataIn D D-FF Q Combinatorial Logi D D-FF Q DataOut DataOutN ClockIn The challenge of design then focuses on clock distribution. If done right, the circuit will function as designed. Circuit delays will be predictable. Circuit Timing Specifications can be easily defined, derived, and tested. For pipelined digital designs, input and output timings can be easily derived and balanced. I have designed a number of ASICs for digital signal processing that employed the following concept to insure on-chip and off-chip timing, internal signal integrity and bounded delay propagation. DataIn A Mux B Sel D Q D-FF Combinatorial Logi A Mux B Sel D Q D-FF DataOut DataOutN ClockIn Super Synchronous Module Start with the fundamentals. As you become an expert use riskier techniques. 7 of 22 ECE 357

8 Writing to a Register File (Synchronous, decoded data select, write select, common Din Bus) A Mux D Q Q DinBus B Sel D-FF A Mux D Q Q B Sel D-FF A Mux D Q Q B Sel D-FF Write AddSel Decoder Clock Note: Do not gate clocks! This causes additional clock skew, changes set-up and hold times, and can result in race conditions that cause circuit failures. Clock all registers at the same timing level with exactly the same clock! (Use clock trees to eliminate clock skew when clock buffers are needed.) 8 of 22 ECE 357

9 Reading from a Register File (Synchronous, decoded data select, read select, common Dout Bus) Data1 Tri-State Tri-State Data Bus Data2 Tri-State Data3 Read AddSel Decoder Introducing one of the most important logic gate in computer design The Tri-State Output They must be used whenever multiple signal sources connect to the same signal line! 9 of 22 ECE 357

10 Tri-State Gates Without tri-state output gates, high speed buses would not exist. A switch of a different sort the signal passes or the output is high-impedance. A simple buffer or inverter with an output enable control line. They must be used whenever multiple signal sources connect to the same signal line! From the text: Figure (a) A non-inverting tri-state buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) An inverting tri-state buffer. Note: Buffers and Tri-States are two different types of gates; the author doesn t differentiate between them. Buffers drive significant loads, while Tri-states allow three output states. A Tri-state Buffer has three output states and drives high loads. 10 of 22 ECE 357

11 11 of 22 ECE 357

12 Memory Organization Conceptually, a giant register file that can be read and written. Note: THIS IS CONCEPTUAL. DO NOT USE THIS DESIGN, see notes below. Note 1: For a correct synchronous design use the CK inputs as a select line for a multiplexed clocked D flip flop and then clock all the registers simultaneously. Note 2: For a more realistic memory design, replace all the clocked D-FF with gated D- Latches. But be careful, address line switching can cause glitches and false writes if the address is not setup before CS or RD# occur (timing considerations)! Note 3: I would not give any credit for this control logic design, it is glitch based and should not be used. If you did this on the job for your first design, you should be either trained or fired for incompetence. 12 of 22 ECE 357

13 Memory Devices For most memories, the Input and Output are connected together. This results in the following symbol level representations: Typical Memory Symbols and Pin Outs (a) SRAM and (b) DRAM Memories can operate with or without a defined clock. Those above operate without a clock and are defined as asynchronous memories with specific timing related to and required of the control signals Memories that input a clock are called synchronous memories and have timing related to clock edges and control signals and outputs that are defined with respect to the clock and clock cycles. 13 of 22 ECE 357

14 Asynchronous SRAM Memory Timing CS# Address Address Out Address Out RD# WR# Data(7:0) Data Out Data In Simple Asynchronous Memory Operation (Memory Perspective) Note: X# indicates Not(X), the inverse of X (1) Chip select required to turn the memory on (1) Address is required to select word or bit (before write, preferably before a read) (2) Read (RD#) and Write (WR#) gates specifically defined or a single (RD/WR#) (2 or 3) Data bus is bi-directional both input and output (using internal tri-state output enables) Note: Output Enable is not shown on this timing (assume OE# = RD#). Timing that must be known: CS to output Address to output RD/OE to output RD/OE to tri-state (time to valid outputs vs. timing to High-Z is usually different) CS to write Address to Write Write period Write recovery 14 of 22 ECE 357

15 Synchronous Memory Timing CLKOUT CS# Address Address Out Address Out RD# WR# Data(7:0) Data Out Data In Same operations may be asynchronous, but internal control signals are registered for application on clock edges. Control changes after clock edges (change caused by clocking, positive or negative edge) Operations typically occur one clock cycle after control is clocked When outputting, the output may tri-state asynchronously (when RE# is removed) to avoid multiple devices simultaneously driving the bus. Wait states for read/write may be need due to speed of CPU vs. memory? Typically: Writes can be done more quickly than reads. As shown above: write 1 or 2 clock periods, read 2 periods. Reads require the talked-to device to drive the data bus, writes do not. 15 of 22 ECE 357

16 Types of Memories 16 of 22 ECE 357

17 Memory Buses Address Bus: Binary addressing of memory unit to be selected Data Bus: Binary data that is being input or output from memory Control Bus: All control signals required to operate the memory typically CS, RD/WR#, OE but maybe RAS, CAS, RD# and WR# CPU Device Buses Memory and I/O Addressing address, data, bus control Bus master/slave control bus arbitration Interrupts and Status Special signals coprocessor interfaces or miscellaneous (JTAG, IIC, debug, etc.) 17 of 22 ECE 357

18 CPU Buses in Time Pentium II (a) 8088 generation 20A, (b) generation 24A, (c) 8036 generation 32A ##A-##D Bus Description of Address and Data bits Pentium II Symbol Note: Pentium II s started the use of PCI and DRAM bridge ICs. 18 of 22 ECE 357

19 Computer Buses Computers use numerous buses at multiple levels. On-chip buses for registers, execution unit operands, instructions, etc. Off-chip buses for memory, peripherals, interrupts, status, etc. Typical buses in a simple microcontroller/microprocessor application 19 of 22 ECE 357

20 Synchronous CPU Bus Timing with an Asynchronous Memory Synchronous Bus Read Cycle Timing Considerations: Address Access Time:T1+T2+T3/2 TAD TDS = =46.5 RD Access Time: T1/2+T2+T3/2 TRL TDS = 37 MREQ Access Time (1): T1+T2+T3/2 TAD-TML TDS = 40.5 MREQ Access Time (2): T1/2+T2+T3/2 TM TDS = 37 Worst case (memory requirement): min(46.5, 37, 40.5, 37) = 37 nsec Timing Notes: Minimum vs. maximums are important. Relationships to various elements must be considered. Clock duty cycles could change the above results. Be methodical and check all possibilities. Doing detailed timing is painful tedious but critical. 20 of 22 ECE 357

21 Asynchronous CPU Bus Timing Asynchronous Bus Read Cycle with hardware handshaking Memory Timing Considerations: Address Read Write Handshaking Handshaking at the asynchronous memory level. Request Release Request Complete MSYN SSYN MSYN SSYN Response Ready Response Complete 21 of 22 ECE 357

22 Higher order messaging (generalized for communication protocols) Request-Response with message handshaking. (Ack acknowledge) Request Req Req Ack Rec Res Complete End Ack Res Ack Done Ack Acknowledge Response Res Ack Message Done Positive Response Messaging: Acknowledge All Communications 22 of 22 ECE 357