Combinational Logic Building Blocks and Bus Structure. ECE 152A Winter 2012
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1 Combinational Logic Building Blocks and Bus Structure ECE 5A Winter 0
2 Reading Assignment Bron and Vranesic Implementation Technology.8 Practical Aspects.8.7 Passing s and 0s Through Transistor Sitches.8.8 Fan-In and Fan-Out in Logic Gates Tri-State Buffers (only this section of Transmission Gates.9. Multiplexer Circuit March 4, 0 ECE 5A - Digital Design Principles
3 Reading Assignment Bron and Vranesic (cont 6 Combinational-Circuit Building Blocks 6. Multiplexers 6.. Synthesis of Logic Functions Using Multiplexers 6.. Multiplexer Synthesis Using Shannon s Expansion 6. Decoders 6.. Demultiplexers 6. Encoders 6.. Binary Encoders 6.. Priority Encoders 6.4 Code Converters March 4, 0 ECE 5A - Digital Design Principles
4 Reading Assignment Roth 9 Multiplexers, Decoders and Programmable Logic 9. Introduction 9. Multiplexers 9. Three State Buffers 9.4 Decoders and Encoders March 4, 0 ECE 5A - Digital Design Principles 4
5 Multiplexer Passes one of several data inputs to output Generally n data inputs and alays a single data output n control lines determine hich input is steered to the output Allos logical (not tri-state or electrical implementation of buses Buses and register transfer operations fundamental to digital system design March 4, 0 ECE 5A - Digital Design Principles 5
6 Multiplexer Also possible to implement arbitrary combinational logic ith multiplexers Universal, combinational logic element Also knon as Data Selector and Mux In sequential operation, provides parallel to serial conversion March 4, 0 ECE 5A - Digital Design Principles 6
7 To-to-One Multiplexer F = Select x 0 + Select x x = 0 X = March 4, 0 ECE 5A - Digital Design Principles 7
8 Four-to-One Multiplexer i th data input ANDed ith minterm m i Embedded circuit generating minterms ill become knon as a decoder m 0 0 m m m March 4, 0 ECE 5A - Digital Design Principles 8
9 Building Larger Multiplexers 4-to- (4: Mux using -to- (: Muxes Simple and modular Adds levels of gate (propagation delay March 4, 0 ECE 5A - Digital Design Principles 9
10 Building Larger Multiplexers 6: Mux constructed from 4: Muxes Expandable to : and 64: ith additional : and/or 4: Muxes With additional levels of propagation delay March 4, 0 ECE 5A - Digital Design Principles 0
11 Multiplexer Application Crossbar Sitch In general, n-inputs by n- outputs Connectivity is any input to any output Important component of netorking hardare The bigger, the faster, the better March 4, 0 ECE 5A - Digital Design Principles
12 Combinational Design Using Multiplexers Input variables applied to Mux select lines Steer (constant value of function to output Allos implementation of n-variable function ith n -to- multiplexer Steer derived function (a variable, its complement, the constant or the constant 0 to the output Allos implementation of n-variable function ith n- -to- multiplexer March 4, 0 ECE 5A - Digital Design Principles
13 Combinational Design Using Multiplexers Example : XOR Function Using a 4: Mux The modified Truth Table Possibilities are x, x, 0, The -input XOR using a : Mux March 4, 0 ECE 5A - Digital Design Principles
14 Combinational Design Using Multiplexers Example : Three input majority function Three input function ith ( n- -to- 4: Mux March 4, 0 ECE 5A - Digital Design Principles 4
15 Combinational Design Using Multiplexers Multiplexer Synthesis Using Shannon s Expansion By adding gate level circuitry to Mux inputs, an arbitrary combinational function can be realized ith a -to- Mux Externally generating a function of one of the variables March 4, 0 ECE 5A - Digital Design Principles 5
16 March 4, 0 ECE 5A - Digital Design Principles 6 Combinational Design Using Multiplexers Example : Three input majority function ith : Mux Algebraic expansion ( '( ( 0 '(0 ( '( ' ( (,, ( (,, ( f f from Shannon...and f f f
17 Combinational Design Using Multiplexers Example : Three input majority function ith : Mux Truth Table and circuit implementation March 4, 0 ECE 5A - Digital Design Principles 7
18 March 4, 0 ECE 5A - Digital Design Principles 8 Combinational Design Using Multiplexers Shannon s Expansion ith 4: Mux Three input majority function Expansion in terms of and Verifies earlier (heuristic solution ( '( ( ' '(0 ' ( 0 (0 ' 0 (0 ' 0 0 '(00 ' (,, ( f f f
19 Multiplexers and Buses Bus allos data transfers beteen multiple sources and single or multiple destinations over a shared path (ires Bus includes multiple bits Parallel data bus Only one source on the bus at any time Bus contention March 4, 0 ECE 5A - Digital Design Principles 9
20 Multiplexers and Buses Example belo illustrates to, four-bit ords (X and Y multiplexed onto the Z bus Register transfer operations A : Z X, A : Z Y March 4, 0 ECE 5A - Digital Design Principles 0
21 Tri-State Outputs Utilizes third, high impedance output state In Hi-Z state, output appears as an open circuit to bus connection Mux disconnects from bus logically, tri-state output device disconnects electrically March 4, 0 ECE 5A - Digital Design Principles
22 Tri-State Outputs (cont Flavors of tri-state outputs and control Bus implementation March 4, 0 ECE 5A - Digital Design Principles
23 NMOS and PMOS Transistors Recall static CMOS circuits Logic high output passed to output through PMOS transistor(s PMOS transistor passes good and bad 0 Logic lo output passed to output through NMOS transistor(s NMOS transistor passes good 0 and bad Good 0s and s are GND and V DD Bad 0s and s have degraded DC voltage (logic levels March 4, 0 ECE 5A - Digital Design Principles
24 NMOS and PMOS Transistors Degradation of DC signal levels is a result of the threshold voltage (V T of transistor and the body effect To turn on the transistor, the gate to source voltage (V GS must exceed the transistor s threshold voltage (V T An NMOS transistor has a positive V T A PMOS transistor has a negative V T The threshold voltage itself is increased by the body effect by a factor of ~.5 March 4, 0 ECE 5A - Digital Design Principles 4
25 NMOS and PMOS Transistors For the inverter belo, assume the NMOS device has a V T of V (V GS > V and the PMOS device has a V T of -V (V GS < -V and V DD = 5V Input = 5V, V GS (T = 5V (off, V GS (T = 5V (on Output = 0V (GND Input = 0V, V GS (T = -5V (on, V GS (T = 0V (off, Output = 5V (V DD March 4, 0 ECE 5A - Digital Design Principles 5
26 NMOS and PMOS Transistors Bad s (NMOS and Bad 0s (PMOS V A = V DD V T (NMOS Input going high; turns off at V GS = V T V B = -V T (PMOS Input going lo; turns off at V GS = V T March 4, 0 ECE 5A - Digital Design Principles 6
27 CMOS AND Gate Note degradation in DC signal (logic levels AND Gates are never built this ay in CMOS March 4, 0 ECE 5A - Digital Design Principles 7
28 The CMOS Transmission Gate When enabled, the CMOS Transmission Gate: Passes good s (through the PMOS transistor Passes good 0s (through the NMOS transistors When disabled, the CMOS Transmission gate acts like a Tri-State Buffer March 4, 0 ECE 5A - Digital Design Principles 8
29 CMOS Transmission Gate MUX : Multiplexer implementation ith transmission gates March 4, 0 ECE 5A - Digital Design Principles 9
30 Decoders -to-4 Decoder shon -to- n in general Enable input allos construction of decoder tree and demultiplexer Generates all minterms hen enabled Multiple output circuits One hot decoding March 4, 0 ECE 5A - Digital Design Principles 0
31 Decoder Tree One-bit expansion (-to-8 by adding external decoding circuitry March 4, 0 ECE 5A - Digital Design Principles
32 Decoder Tree To-bit expansion (4-to-6 by adding another -to-4 decoder March 4, 0 ECE 5A - Digital Design Principles
33 Decoder Applications Multiplexer from decoder Recall embedded decoder March 4, 0 ECE 5A - Digital Design Principles
34 Decoder Applications Multiple Output Circuits Full Adder using X 8 Decoder Sum = m + m + m4 + m7 = x y z + x yz + xy z + xyz Carry = m + m5 + m6 + m7 = x yz + xy z + xyz + xyz March 4, 0 ECE 5A - Digital Design Principles 4
35 Decoder Applications Decoder Bus Control/Multiplexer March 4, 0 ECE 5A - Digital Design Principles 5
36 Demultiplexers Serial to parallel conversion Send a single data bit to a specific address A -to- n demultiplexer is implemented using an n-to- n decoder The (value of the data is applied via the enable input Valuable circuit in sequential circuits Not so much in combinational circuits Also referred to as Dmux s March 4, 0 ECE 5A - Digital Design Principles 6
37 Encoders Binary Encoders One hot input, binary (or other code representation output Reverse of decoder March 4, 0 ECE 5A - Digital Design Principles 7
38 Encoders Priority Encoders Used in prioritizing interrupts (or other events Least significant Binary encoding Most significant Output valid March 4, 0 ECE 5A - Digital Design Principles 8
39 Code Converters BCD to 7-Segment Display Code Converter March 4, 0 ECE 5A - Digital Design Principles 9
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Copyright Peter R. Rony 2009. All rights reserved.
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