# Pass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches).

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1 Pass Gate Logic n alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Switch Network Regeneration is performed via a buffer. We have already observed a series connection of two switches implements ND while a parallel connection implements OR. is not redundant, it ensures a low impedance path exists when is low. 1

2 Pass Gate Logic dvantage: fast and simple. Complex gates can be implemented using minimum number of transistors, which also reduces parasitics. Static and dynamic performance depends on a switch with low parasitic resistance and capacitance. C C C Transmission gate C Therefore, pass gate networks are often constructed from bi-directional transmission gates. 2

3 Pass Gate Logic oth transistors are important: =5V C=5V M n C L M 1 M 2 Here, M n turns off when V reaches (5 - V Tn ) or approximately 3.5V! Note, the V Tn is increased due to the body effect. This reduces the noise margin and increases static power dissipation. lso, the resistance of the switch increases dramatically when the output voltage reaches V in -V Tn (linear mode). The combination of both an PMOS and NMOS avoids this problem but requires that the control and its complement be available. 3

4 Pass Gate Logic Transmission gates can implement complex gates very efficiently S Design Issues Resistance S S 2-to-1 MUX requires 6 transistors F = (*S + *S) XOR XOR requires 6 transistors C=0 Parallel connection of resistances R n and R p =5 C L R n = (V DD - V out )/I n R p = (V DD - V out )/I p C=5 Currents are dependent on V out and operation region 4

5 Pass Gate Logic Design Issues Resistance (cont). During the low-to-high transition, the pass transistors pass through several operation modes. s V GS is always equal to V DS, the NMOS is either in saturation or off. The V GS of the PMOS is V DD, and the device changes from saturation to linear. V out < V Tn : NMOS and PMOS saturated. V Tp < V out < V DD - V Tn : NMOS saturated, PMOS linear. V DD -V Tn < V out : NMOS cutoff, PMOS linear. It is important to incorporate the body effect when computing I p and I n. The expression for the resistance of a pass gate without the body effect. 1 R eq k n ( V DD V Tn ) + k p ( V DD V Tp ) 5

6 Pass Gate Logic Design Issues Resistance (cont). Simulated values of : 30 R eq = R p R n R n 20 R p 5V 0V V out 10 R eq 5V R eq is relatively constant at 10 kω so a constant resistance switch model is reasonable. 6

7 Pass Gate Logic Design Issues Delay 0 0 V 1 V i-1 V i V i+1 V n-1 V n C C C In order to analyze the response, let's replace the pass gates with R eq s. R eq R V 1 V eq R i-1 V eq R i V i+1 V eq n-1 V n C C C C C C Delay is found by solving a set of differential equations of the form: V i 1 = ( V t R eq C i+ 1 + V 2V i 1 i ) 7

8 Pass Gate Logic Design Issues Delay (cont). n estimate of the dominant time constant at the output of n pass gates: nn ( + 1) τ( V n ) = CR eq k = CR eq k = 0 Propagation delay is proportional to n 2! n For large n, it is better to break the chain every m switches and insert buffers: m m R eq R eq C C C C C C V n Total delay assuming buffer delay is t buf is: t p 0.69 n m --- mm ( + 1) CR eq n 1 nm ( + 1) = + tbuf = 0.69 CR 2 m eq n 1 m tbuf 8

9 Pass Gate Logic Design Issues Delay (cont). Here, delay exhibits only a linear dependence on the # of switches n. The optimal number of switches, m opt, between buffers is found: t p = 0 m m opt 1.7 t pbuf = s t buf increases, the number of switches grows. CR eq In current technologies, m opt is typically 3 or 4. For example, assume R eq = 10kΩ, C = 10fF, and t pbuf = 500ps. This yields an optimal value of m equal to 3.8. Therefore, a buffer every 4 transmission gates is suggested. 9

10 Pass Gate Logic Design Issues Transistor sizing Pass gate logic family is a member of the ratioless logic class. The dc characteristics are not affected by the sizes. Performance, to the first order, is not impacted by changing the W/L. Increasing the size reduces the resistance, but this is offset by the increase in diffusion capacitance. Therefore, minimum sized devices should LWYS be used, unless the chain drives a significant external load capacitance. In this case, ordering transistors from largest to smallest in the pass gate chain will help reduce delay. This is analogous to the argument given earlier for logic gate transistors close to the output. 10

11 NMOS-Only Transmission Gate Disadvantages of pass gate: Requires both NMOS and PMOS, in different wells. oth true and complemented polarities of the control signal needed. Parallel connection of both transistors increases node capacitance. Therefore, an NMOS-only version is advantageous. Problems: Reduced noise margins due to the threshold voltage drop. Static power consumption. =5V C=5V M n C L M 1 M 2 11

12 NMOS-Only Transmission Gate One solution is to add a PMOS device, called a level restorer. Level restorer 5V M 4 M 3 M r M 2 X M n M 1 The output of the inverter is "feedback" as a control signal. It turns on when the inverter output goes low (V out < V DD - V tp ) and restores node X to V DD. This eliminates the static power consumed. However, the size of the PMOS transistor is important, since a conflict is created during switching. For example, assume node =0, storage node X=V DD and =0->1. conducting path exists from V DD -M r -M n -M 3 -GND. 12

13 NMOS-Only Transmission Gate Let R r, R n and R 3 represent the resistances of transistors M r, M n and M 3. If R r is too small, it will be impossible to bring node X below V M. This is called the writability problem, used in reference to feedback circuits. Let's simplify the analysis of finding the switching point by grounding M r 's input (open the feedback loop). ssume M r is in linear mode, M n is in saturation and V is close to GND. I = k 3 ( V DD V Tn )V (linear) k n I = ( V 2 V V Tn ) 2 (for V X = V M ) ( V DD V M ) 2 I = k r ( V DD V Tp ) ( V DD V M ) (1) (2) (3) I is set by (3), which allows V to be found via (1) and then V as a function of the k- parameters (the objective). 13

14 NMOS-Only Transmission Gate Let's set the condition that V < V DD -- in other words, some value of V less than V DD will set V X < V M (which allows the inverter to switch). ssume the sizes of M 3 and M n are identical and V DD =5V, V Tn = V Tp =0.75V and V M =2.5V: V 3.87 k r k r = V The boundry condition for this constraint to be valid is m = k n /k p > Smaller values do not allow the inverter to switch. Using a value of 3 is reasonable, which amounts to making the NMOS pass gate transistor equal to PMOS restoring device. What about performance? dding the level restorer increases the capacitance at V X. lso, the rise time of the inverter is slowed due to the fight. k n k n 14

15 NMOS-Only Transmission Gate However, the fall time is improved slightly V out (V) Without With V V out (V) With Without t (nsec) t (nsec) 6 second method of implementing NMOS-only pass gate networks is to change V T (if your manufacturer supports it). zero V T transistor for M n (a natural device) is one possibility. This logic style is called Complementary Pass-Transistor Logic (CPL). 15

16 CPL Examples: F= F=+ F=+ G= G=+ G=+ Properties: They are differential circuits. Eliminates inverters and allows minimal implementations, e.g., XOR. CPL is static (low impedance connection to V DD and GND). V T (including body effect) is reduced to below V Tp, eliminating static power in successor gates. The design is modular -- all gates use exactly the same topology. 16

17 CPL The main disadvantages is that turning off a zero-v T device is hard (plus it has a reduced noise margin). 0V 5V 5V 0V Note that a 4-input NND requires three 2-input NNDs + buffer for 14 transistors, which is > 8 for the full complementary version! The applicability of CPL is strongly dependent on the logic function to be implemented, e.g. 2-transistor XOR good for multipliers and adders. CPL is extremely fast and efficient. Routing overhead is significant however. 17

18 Dynamic Logic Dynamic logic reduces the fan-in, similar to pseudo-nmos, without the static power consumption. In 1 In 2 In 3 M p PDN Out M p Out C = + C M e n network M e Precharge When =0, the output node Out is precharged to V DD by M p. Evaluation: When =1, M e is on and node Out discharges conditionally, depending on the value of the input signals. 18

19 Dynamic Logic If no path exists during evaluate, then Out remains high via C L (diffusion, wiring and gate capacitance). Note that once Out is discharged, it cannot be recharged. Therefore, the inputs can make at most one transition during evaluation. Properties: The logic function is implemented in the NMOS pull-down network. The # of transistors is N+2 instead of 2N It is non-ratioed (noise margin does not depend on transistor ratios). It only consumes dynamic power. Faster switching due to reduced internal and downsteam capacitance. Steady-state behavior V OL and V OH are GND and V DD. Our standard definitions of noise margins and switching thresholds do not include time, which is required in this case. 19

20 Dynamic Logic Steady-state behavior (cont): For example, noise margins depend on the length of the evaluate. If clk is too long, leakage affects the high output level significantly. Since the pull down network starts to conduct when the input signal exceeds V Tn, it is reasonable to set V M, V IH, V IL = V Tn. Therefore, NM L is very low. Note that this is a conservative estimate since subthreshold leakage occurs for inputs below V Tn. lso note that the high output level is sensitive to noise and coupling disturbances because of its high output impedance. The high value of NM H compensates for this increased sensitivity. 20

21 Dynamic Logic Dynamic behavior lso, after precharge, the output is high. Therefore, t plh = 0! This is somewhat unfair since it ignores the precharge time. The designer is free to choose the size of the PMOS device, smaller is faster but increases load and t phl. The t phl is proportional to C L and current-sinking capabilities of PDN. M e slows down the gate a little. V out (V) Capacitive coupling Evaluate Precharge t (nsec) 21

22 Dynamic Logic There are three sources of noise Charge Leakage Precharge Evaluate Sets the minimum clock to 250Hz to 1kHz (testing difficulties) Charge Sharing t t Via reversed-biased diffusion diodes and subthreshold leakage M p Out If V out > V Tn then V out and V x reach the same value. =0 M a M b M e X C b C a C a C a C L C out V out = V DD Target is to keep V out < V Tp since output may drive a static gate. C a /C L <

23 Dynamic Logic One way to combat both of these: M p M bl M a M b M e Out bleeder Out M p M bl M a M b M e Static bleeder Precharge Internal nodes Pseudo-static: M bl is a highly resistive (long and narrow) PMOS transistor. lternatively, precharge internal nodes using a clock driven PMOS. Clock Feedthrough The clock is coupled to the storage node via C gs and gate-overlap caps. May forward bias the junction and inject electrons into substrate. 23

24 DOMINO Logic Cascading Dynamic gates In M p M p Out 2 Out 1 In Evaluate M e M e Fix is to restrict the inputs to making only a 0->1 transition during eval. M p Out 1 Out 1 Out 2 V Level restorer. M p M r Out 2 t In 1 In 2 In 3 PDN M e In 4 Fanout also driven by static inverter. PDN M e 24

25 DOMINO Logic During evaluation, either the output of the first DOMINO stays at 0 (no delay!) or makes a 0->1 transition. The transition may ripple all the way down the chain. Properties: Only non-inverting logic can be implemented. ppropriate for complex, large fan-out circuits such as LUs or control circuits. Very high speeds can be achieved, t phl = 0. In the past, DOMINO was used in the design of a number of high speed ICs. The first 32-bit microprocessor (ellmc 32) used it. Recently, pure DOMINO circuits are rare, mainly due to the non-inverting logic property. 25

26 np-cmos Logic PUN networks replace the static inverters. In 1 In 2 In 3 M p PDN M e Out 1 In 4 n block M e PUN M p p block Out 2 lso called ZIPPER logic Conditionally charged Note that the p blocks are driven with the Clk_bar so that the precharge and evaluate periods coincide. np-cmos logic style is 20% faster than DOMINO, despite the slower PMOS pull-up devices. The DEC alpha-processor (first at 250MHz) used this logic extensively. Disadv: NM L = V Tn and NM H = V Tp. 26

27 Power Consumption We've already discussed sources of power consumption in CMOS inverter. P dyn = 2 C L V DD f 0->1 We now discuss the effects of switching activity, glitching and direct-path current. Note that the factor f 0->1 complicates the analysis for complex gates. Factors affecting the switching activity include the statistics of the input signals, the circuit style (dynamic/static), the function, and network topology. These are incorporated by: P dyn = 2 C L V DD P 0->1 f where f is the average event rate, and P 0->1 is the probability an input transition results in a 0->1 power-consuming event. 27

28 Complex Static Gate Power Consumption Consider a 2-input NOR gate, assume the input signals have a uniform distribution of high and low values. e.g., the 4 input combinations, = 00, 01, 10, 11, are equally likely. Therefore, the probability the output is low or high is 3/4 and 1/4, respectively. The probability of an energy consuming transition is the probability that the output is initially low, 3/4, times the probability it will become high, 1/4. 3 P 0->1 P 0 P 1 ( 1 P 1 )P = = = -- = /4 X 3/4 = 9/16 3/4 X 1/4 = 3/ /16 1/4 X 1/4 = 1/16 28

29 Complex Static Gate Power Consumption Note that the output probabilities are no longer uniform. This suggests that the input signals are not uniform, since gates are typically cascaded. The probability that the output is 1 (P 1 ) is a function of the input distributions, P and P (the probabilities the inputs are 1). P 1 = ( 1 P )( 1 P ) for the NOR gate. The transition probability is then: P 0->1 = ( 1 P 1 )P 1 = [ 1 ( 1 P )( 1 P )][( 1 P )( 1 P )] 3-D graph shown in text. Derive these expressions for ND, OR and XOR. 29

30 Complex Static Gate Power Consumption For example: C X Z No reconvergent fan-out With no reconvergent fan-out, the probability that X undergoes a power consuming transistion is 3/16. X = 1, 3 out of 4 times. Therefore, X has an uneven distribution yielding a transition probability on Z as: 3 1 Z ( 1 P X P C )P X P C = = = The orderly calculations from input to output is not possible for Circuits with feedback (sequential circuits). Circuits with reconvergent fanout. 30

31 Complex Static Gate Power Consumption In the latter case, the input signals are not independent. X Z Reconvergent fan-out The procedure above yeilds 15/64 for the transition probability. However, reduction yields Z =, and the P 0->1 transition probability on Z is (1/2 X 1/ 2) = 1/4. Conditional probabilities take signal inter-dependencies into account. For example, Z = 1 iff and X = 1. P Z = PZ=1 ( ) = P=1 (, X=1) This expresses the probability that and X are 1 simultaneously. If a dependency exists, a conditional probability is required for expansion: P Z = PX=1 ( =1) P=1 ( X=1) = PX=1 ( =1) P=1 ( ) 31

32 Dynamic Gate Power Consumption What about dynamic circuits? During precharge, the output node is charged to 1. Therefore, power is consumed every time the PDN is on (output is 0), independent of the preceding or following values! Power consumption is determined solely by signal value probabilities, and not by transition probabilities. These is always larger than the transition probability, since the latter is the product of two signal probabilities both of which is smaller than 1. For example, the 0-probability of a 2-input NOR is P 0 = ( P + P P P ) If the inputs are equally probably, there is a 75% chance of a 1->0. P NOR = C L V DD f clk Note C L is smaller than a static gate but the clock load must be considered. 32

33 Glitches in Static CMOS Circuits The finite propagation delay through gates in a network can cause spurious transitions called glitches, critical races or dynamic hazards. These are multiple transitions during a single clock cycle. X C Z ssume a unit delay and all inputs arrive at the same time. The second NOR evaluates twice, the first one with the previous value of X. This consumes unnecessary power. C Unit delay Redesign can eliminate glitches by matching delays along signal paths. 33

34 Summary Choosing a logic style depends on Ease of design, Robustness, System clocking requirements, Fan-out, Functionality and Testing. Static is robust and easy to design (ameanable to design automation). Complementary complex gates are expensive in area and performance. Pseudo-NMOS is simple and fast but reduces noise margins and increases power consumption. Pass-transistor logic is good for certain classes of circuits (MUX/adders). Dynamic logic gives fast and small circuits but complicates the design process and restricts the minimum clock rate. For a 4-input NND gate: Style Ratioed Static power # of trans. rea (um 2 ) delay (ns) Complementary No No Pseudo-NMOS Yes Yes CPL No No Dynamic (np) No No

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