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2 Whenever body comes in contact with plastic or other insulating material, static charge is generated. It can be a very small charge, as low as nano Coulombs, but it can cause potential damage to MOS devices, as voltages are pretty high. We know that Q = CV V = Q/C V = It/C Let us consider a modest 1pF capacitor, in which, this 1nC charge is put (can be through a 100uA current for a millisec). This results in SiO 2 breakdown voltage is 10 9 volts/meter. If gate oxide is about 0.1um thick, say; Maximum allowable voltage is. This can easily be generated by walking across a carpet!! A human touch can produce instanteous voltages of 20,000 volts! A typical solution of the ESD protection problem is to use clamping diodes implemented using MOS transistors with gates tied up to either GND for nmos transistors, or to VDD for pmos transistors as shown in Figure For normal range of input voltages these transistors are in the OFF state. If the input voltage builds up above (or below) a certain level, one of the transistors starts to conduct clamping the input voltage at the same level. Fig 33.21: Clamping Transistors

4 Design method is same as we have already discussed in previous lectures. Optimum number of stages are found for a load capacitance assumed a-priori. Logical effort method can be used to decide sizing. Second, the voltage across any oxide at any time should not be greater than the supply voltage, which ensures oxide reliability; most process design engineers will not guarantee oxide reliability for oxide voltages greater than the chip VDD. If a low voltage chip is tied to a bus which connects several chips, some with higher supply voltages, then the Input buffer must be designed such that there is no chance of a problem with the oxide Tri-State Output Circuit The circuits of VLSI chips are designed to be tri-statable as shown in Figure 33.41, which is designed to be driven only when the output enable signal is asserted. The circuit implementation requires 12 transistors. However in terms of silicon area, this implementation may require a relatively small area since the last stage transistors need not be sized large. Fig Tri-State Output Circuit 33.5 Latch-Up Large MOS transistors are susceptible to the latch-up effect. In the chip substrate, at the junctions of the p and n material, parasitic pnp and npn bipolar transistors are formed as in the following cross-sectional view shown in Figure 33.51

5 Fig 33.51: Latch-Up These bipolar transistors form a silicon-controlled rectifier (SRC) with positive feedback as in the following circuit model shown in Figure Fig 33.52: SRC With Positive Feedback

6 The final result of the latch-up is the formation of a short-circuit (a low impedance path) between VDD and GND which results in the destruction of the MOS transistor Prevention of Latch-Up Fig 33.61: Latch-Up Prevention Techniques The following techniques can be used to prevent latch-up: Use p+ guard rings to ground around nmos transistors and n+ guard rings connected to VDD around pmos transistors to reduce Rwell and Rsub and to capture injected minority carriers before they reach the base of the parasitic BJTs Place substrate and well contacts as close as possible to the source connections Use minimum area p-wells (in case of twin-tub technology or n-type substrate) so that the p-well photocurrent can be minimized during transient pulses Source diffusion regions of pmos transistors should be placed so that they lie along equipotential lines when currents flow between VDD and p-wells. In some n- well I/O circuits, wells are eliminated by using only nmos transistors. Avoid the forward biasing of source/drain junctions so as not to inject high currents; the use of a lightly doped epitaxial layer on top of a heavily doped substrate has the effect of shunting lateral currents from the vertical transistor through the low-resistance substrate. Layout n- and p-channel transistors such that all nmos transistors are placed close to GND and pmos transistors are placed close to VDD rails. Also maintain sufficient spacings between pmos and nmos transistors.

7 Recap In this lecture you have learnt the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up Congratulations, you have finished Lecture 33.

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