Optimization and Comparison of 4-Stage Inverter, 2-i/p NAND Gate, 2-i/p NOR Gate Driving Standard Load By Using Logical Effort
|
|
- Lewis Leon McLaughlin
- 7 years ago
- Views:
Transcription
1 Optimization and Comparison of -Stage, -i/p NND Gate, -i/p NOR Gate Driving Standard Load By Using Logical Effort Satyajit nand *, and P.K.Ghosh ** * Mody Institute of Technology & Science/ECE, Lakshmangarh, India bstract- pplication of logical effort on transistor-level analysis of -stage inverter, -i/p stage NND and -i/p stage NOR gate is presented. Logical effort method is used to estimate delay and to evaluate the validity of the results obtained by using logical effort. The tested gate topologies were -stage inverter, -i/p- stage NND gate and, -i/p stage NOR gate. The quality of the obtained estimates is validated by circuit simulation using T-SPICE for.8v, 80nm technologies. Index Terms: NND, NOR, Gate, logical path optimization, logical effort. I. Introduction CMOS logic gates are basic building blocks for gate circuits. The delay through these gates is related to their sizes and their during loads. Logical effort is a technique, which gives insight about proper sizing of CMOS logic gates to have the minimum achievable delay. Three architectures for -stage inverter, -i/p- stage NND gate, and -i/p stage NOR gate are sized using logical effort to get the minimum possible delay simulated. The paper is organized as follows. Section II describes the theory of logical effort and the expression for delays. nalytical results are shown in section III. Simulate results are shown in section IV Finally, conclusion is given in section V. II.Logical Effort The method of logical effort is founded on a simple model of the delay through a single MOS logic gate. The model describes delays caused by the capacitive load that the logic gate drives and by the topology of the logic gate. Clearly, as the load increases, the delay increases, but delay also depends on the logic function of the gate. s, the simplest logic gates, drive loads best and are often used as amplifiers to drive large capacitances. Logic gates that compute other functions require more transistors, some of which are connected in series, making them poorer than inverters at driving current. Thus a NND gate must have more delay than an inverter with similar transistor sizes that drives the same load. The method of logical effort (LE) quantifies these effects to simplify delay analysis for individual logic gates and multi-stage logic networks. The first step in modeling delays is to isolate the effects of a particular integrated circuit fabrication process by expressing all delays in terms of a basic delay unit τ, thus we express absolute delay d abs as the product of a unitless delay of the gate, and the delay unit that characterizes a given process []: d abs =dτ () Unless otherwise indicated, we will measure all times in units of τ which is about 50 ps in a typical process. The delay incurred by a logic gate is comprised of two components, a fixed part called the parasitic delay, p and a part that is proportional to the load on the gate s output, called the effort delay or stage effort, f. The total delay, measured in units of τ, is the sum of the effort and parasitic delays.thus d= f+p () The effort delay depends on the load and on properties of the logic gate driving the load. We introduce two related terms for these effects: the logical effort g, captures properties of the logic gate, while the electrical effort h, characterizes the load. The effort delay of the logic gate is the product of these two factors. f=gh () The logical effort captures the effect of the logic gate s topology on its ability to produce output current. It is independent of the size of the transistors in the circuit. The electrical effort describes how the electrical environment of the logic gate affects performance and how the size of the transistors in the gate determines its load-driving capability. The electrical effort is defined by h = C out / () where C out is the capacitance that loads the logic gate and c in is the capacitance presented by the logic gate at one of its input terminals. Many CMOS designers also call electrical effort as fanout. Combining Equations and, we obtain the basic equation that models the delay through a single logic gate, in time scale is d = gh+ p (5) This equation shows that logical effort g and electrical effort h both contribute to delay in the same way. This formulation separates g, h, p and τ the four contributions to delay. The process parameter τ represents the speed of the basic transistors. The parasitic delay p expresses the intrinsic delay of the gate due to its own internal capacitance, which is largely independent of the size of the transistors in the logic gate. The electrical effort h combines the effects of external load, which establishes
2 C out with the sizes of the transistors in the logic gate, which establish of parasitic delay of various logic gate types assuming simple layout styles. typical value of p inv the parasitic delay of an inverter is.0 shown in Table. The logical effort, g expresses the effects of circuit topology on the delay free of considerations of loading or transistor size. Logical effort is useful because it depends only on circuit topology. Logical effort values for a few CMOS logic gates are shown in Table. Logical effort is defined so that an inverter has a logical effort of one. This unitless form means that all delays are measured relative to the delay of a simple inverter. n inverter driving an exact copy of it experiences an electrical effort of one. Because the logical effort of an inverter is defined to be one, an inverter driving an exact copy of it will therefore have an effort delay of one. Fig. shows the architectures of, NND and NOR gates. Table : Estimates of parasitic delay of various logic gate types assuming simple layout styles. typical value of p inv the parasitic delay of an inverter is.0. Gate type NND NOR XOR, XNOR 6 Number of inputs 8 n p inv np inv np inv np inv = g = / B = g = / (a) (b) (c) B = 5 g = 5/ i) For -stage inverter Given: N =, C out = 00f III NLTICL RESULTS To find least delay (D) = N [F /N + P in ] = [00 / +] =6.69sec For τ = ps in 80 nm process Fig.. Simple gates architecture for (a) (b) two i/p Nand gate and (c) two i/p Nor gate Table.Logical effort of static CMOS gates. (γ =,where γ is the ratio between PMOS and NMOS transistor size.) bsolute delay (d abs ) = Dτ = sec = sec. ii) For -stage -i/p Nand gate Given: N =, C out = 00f Gate type Number of inputs To find least delay (D) = N [F /N + P in ] n = [(00/) / +] =.59sec For τ = ps in 80 nm process NND / 5/ 6/ (n+)/ bsolute delay (d abs ) = Dτ = sec = sec. NOR 5/ 7/ 9/ (n+)/ iii) For -stage -i/p Nor gate XOR, XNOR Given: N =, C out = 00f
3 To find least delay (D) = N [F /N ] + P in = [(500/) / +] =.7sec For τ = ps in 80 nm processes bsolute delay (d abs ) = Dτ = sec = sec IV SIMULTION RESULTS The original logical effort model has been studied and tested using 80 nm CMOS technology. n extended model has been introduced and compared against the original one. It improves by including the effect on delay time from transition times at the input. The simulation results by using logical effort shows that the new model exceeds the original model on delay accuracy for -stage inverter, -i/p stage Nand gate, -i/p stage Nor gate by 6.85%, 8%, 5.6% respectively. This result is very beneficial to circuit optimization since a more accurate model will bring closer to the best implementation of a particular logic circuit. Figure illustrates simple gate sized for roughly equal output currents.. From the ratio of input capacitances, one can see that the NND gate has logical effort / and the NOR gate has logical effort 5/. It is interesting but not surprising to note from Table that more complex logic functions have larger logical effort. Moreover, the logical effort of most logic gates grows with the number of inputs to the gate. Larger or more complex logic gates will thus exhibit greater delay. s we shall see later on, these properties make it worthwhile to contrast different choices of logical structure. Designs that minimize the number of stages of logic will require more inputs for each logic gate and thus have larger logical effort. Designs with fewer inputs and thus less logical effort per stage may require more stages of logic. The electrical effort is just a ratio of two capacitances. The load driven by a logic gate is the capacitance of whatever is connected to its output; any such load will slow down the circuit. The input capacitance of the circuit is a measure of the size of its transistors [-6]..0E-09.00E E E-0.00E-0.00E E+00 verage delay in sec verage Delay in sec Using logical Effort verage Delay in sec Using nalytical Method -I/p - stage Nor gate -I/p -stage NND gate -stage Table Delay Comparison between simulated and analytical of a logic gate using logical effort Design -stage -I/p - stage NND gate -I/p - stage Nor gate verage delay in sec verage Delay in sec Using logical Effort V CONCLUSION Use of Logical Effort methods for performance comparison of three different gate topologies were presented with wire capacitance included. Obtained results are found consistent with simulation and are encouraging that NND are faster than NOR in CMOS logic gates Paths are fastest when effort delays are, Path delay is weakly sensitive to stages, sizes but using fewer stages doesn t mean faster paths s and NND best for driving large capacitance. They show that incorporating Logical Effort into the analysis of VLSI three different gate topologies can help find better gate topologies. REFERENCES verage Delay in sec Using nalytical Method.576e-00.05e e e e e I. Sutherland, B. Sproull, D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann Publisher, M.J Sebastian smith, application specific integrated circuits, addision- wesely 9997.Kabbani, Modeling and optimization of switching power dissipation in static CMOS circuits, IEEE Computer Society nnual Symposium on VLSI (008), pp pr..j. Park et al., 70ps 6-Bit Parallel Binary dder, 000 Symposium on VLSI Circuits Digest of Technical Papers. 5.H. Q. Dao, V. G. Oklobdzija, pplication of Logical Effort Techniques for Speed Optimization and nalysis of Representative dders, 5 th nnual silomar Conference on Signals, Systems and Computers, Pacific Grove, California, November 7, V.G.Oklobdzija, High-Performance System Design: Circuits and Logic, IEEE Press, 999 Figure. Delay plot
4
5
Module 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits
Module 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits Objectives In this lecture you will learn the following Introduction Logical Effort of an Inverter
More informationGate Delay Model. Estimating Delays. Effort Delay. Gate Delay. Computing Logical Effort. Logical Effort
Estimating Delays Would be nice to have a back of the envelope method for sizing gates for speed Logical Effort Book by Sutherland, Sproull, Harris Chapter 1 is on our web page Also Chapter 4 in our textbook
More informatione.g. τ = 12 ps in 180nm, 40 ps in 0.6 µm Delay has two components where, f = Effort Delay (stage effort)= gh p =Parasitic Delay
Logic Gate Delay Chip designers need to choose: What is the best circuit topology for a function? How many stages of logic produce least delay? How wide transistors should be? Logical Effort Helps make
More informationLecture 5: Logical Effort
Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harvey Mudd College Spring 2004 Outline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of
More informationNEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.
CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache
More informationCMOS Binary Full Adder
CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry - - Table of Contents Key Terminology...- - Introduction...- 3 - Design Architectures...-
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim
More informationDesign of Low Power One-Bit Hybrid-CMOS Full Adder Cells
Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells Sushil B. Bhaisare 1, Sonalee P. Suryawanshi 2, Sagar P. Soitkar 3 1 Lecturer in Electronics Department, Nagpur University, G.H.R.I.E.T.W. Nagpur,
More informationChapter 10 Advanced CMOS Circuits
Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in
More informationGates & Boolean Algebra. Boolean Operators. Combinational Logic. Introduction
Introduction Gates & Boolean lgebra Boolean algebra: named after mathematician George Boole (85 864). 2-valued algebra. digital circuit can have one of 2 values. Signal between and volt =, between 4 and
More informationDesign of Energy Efficient Low Power Full Adder using Supply Voltage Gating
Design of Energy Efficient Low Power Full Adder using Supply Voltage Gating S.Nandhini 1, T.G.Dhaarani 2, P.Kokila 3, P.Premkumar 4 Assistant Professor, Dept. of ECE, Nandha Engineering College, Erode,
More informationCSE140 Homework #7 - Solution
CSE140 Spring2013 CSE140 Homework #7 - Solution You must SHOW ALL STEPS for obtaining the solution. Reporting the correct answer, without showing the work performed at each step will result in getting
More information10 BIT s Current Mode Pipelined ADC
10 BIT s Current Mode Pipelined ADC K.BHARANI VLSI DEPARTMENT VIT UNIVERSITY VELLORE, INDIA kothareddybharani@yahoo.com P.JAYAKRISHNAN VLSI DEPARTMENT VIT UNIVERSITY VELLORE, INDIA pjayakrishnan@vit.ac.in
More informationInternational Journal of Electronics and Computer Science Engineering 1482
International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant
More informationHere we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.
Outline Here we introduced () basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Circuit Logic Gate A logic gate is an elemantary building block
More informationSequential 4-bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationPass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches).
Pass Gate Logic n alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Switch Network Regeneration is performed via a buffer. We have already
More informationTRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN
TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN USING DIFFERENT FOUNDRIES Priyanka Sharma 1 and Rajesh Mehra 2 1 ME student, Department of E.C.E, NITTTR, Chandigarh, India 2 Associate Professor, Department
More informationAnalog & Digital Electronics Course No: PH-218
Analog & Digital Electronics Course No: PH-218 Lec-28: Logic Gates & Family Course Instructor: Dr. A. P. VAJPEYI Department of Physics, Indian Institute of Technology Guwahati, India 1 Digital Logic Gates
More informationHIGH SPEED AREA EFFICIENT 1-BIT HYBRID FULL ADDER
HIGH SPEED AREA EFFICIENT 1-BIT HYBRID FULL ADDER Sachin Kumar *1, Aman Kumar #2, Puneet Bansal #3 * Department of Electronic Science, Kurukshetra University, Kurukshetra, Haryana, India # University Institute
More informationGates, Circuits, and Boolean Algebra
Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks
More informationA Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem
A Novel Low Power, High Speed 4 Transistor CMOS Full Adder Cell with 5% Improvement in Threshold Loss Problem T. Vigneswaran, B. Mukundhan, and P. Subbarami Reddy Abstract Full adders are important components
More information1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
More informationEfficient Interconnect Design with Novel Repeater Insertion for Low Power Applications
Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,
More informationAN IMPROVED DESIGN OF REVERSIBLE BINARY TO BINARY CODED DECIMAL CONVERTER FOR BINARY CODED DECIMAL MULTIPLICATION
American Journal of Applied Sciences 11 (1): 69-73, 2014 ISSN: 1546-9239 2014 Science Publication doi:10.3844/ajassp.2014.69.73 Published Online 11 (1) 2014 (http://www.thescipub.com/ajas.toc) AN IMPROVED
More informationLOW POWER MULTIPLEXER BASED FULL ADDER USING PASS TRANSISTOR LOGIC
LOW POWER MULTIPLEXER BASED FULL ADDER USING PASS TRANSISTOR LOGIC B. Dilli kumar 1, K. Charan kumar 1, M. Bharathi 2 Abstract- The efficiency of a system mainly depends on the performance of the internal
More informationAdder.PPT(10/1/2009) 5.1. Lecture 13. Adder Circuits
Adder.T(//29) 5. Lecture 3 Adder ircuits Objectives Understand how to add both signed and unsigned numbers Appreciate how the delay of an adder circuit depends on the data values that are being added together
More informationA New Low Power Dynamic Full Adder Cell Based on Majority Function
World Applied Sciences Journal 4 (1): 133-141, 2008 ISSN 1818-4952 IDOSI Publications, 2008 A New Low Power Dynamic Full Adder Cell Based on Majority Function 1 Vahid Foroutan, 2 Keivan Navi and 1 Majid
More informationTwo-level logic using NAND gates
CSE140: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing 1 Two-level logic using NND gates Replace minterm ND gates with NND gates Place
More informationHigh Speed Gate Level Synchronous Full Adder Designs
High Speed Gate Level Synchronous Full Adder Designs PADMANABHAN BALASUBRAMANIAN and NIKOS E. MASTORAKIS School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, UNITED
More informationStatic-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology
Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department
More informationECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data
More informationDigital to Analog Converter. Raghu Tumati
Digital to Analog Converter Raghu Tumati May 11, 2006 Contents 1) Introduction............................... 3 2) DAC types................................... 4 3) DAC Presented.............................
More informationECE124 Digital Circuits and Systems Page 1
ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly
More informationThree-Phase Dual-Rail Pre-Charge Logic
Infineon Page 1 CHES 2006 - Yokohama Three-Phase Dual-Rail Pre-Charge Logic L. Giancane, R. Luzzi, A. Trifiletti {marco.bucci, raimondo.luzzi}@infineon.com {giancane, trifiletti}@die.mail.uniroma1.it Summary
More informationGates. J. Robert Jump Department of Electrical And Computer Engineering Rice University Houston, TX 77251
Gates J. Robert Jump Department of Electrical And Computer Engineering Rice University Houston, T 77251 1. The Evolution of Electronic Digital Devices...1 2. Logical Operations and the Behavior of Gates...2
More informationModule 7 : I/O PADs Lecture 33 : I/O PADs
Module 7 : I/O PADs Lecture 33 : I/O PADs Objectives In this lecture you will learn the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up
More informationCHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
More informationUnderstanding Logic Design
Understanding Logic Design ppendix of your Textbook does not have the needed background information. This document supplements it. When you write add DD R0, R1, R2, you imagine something like this: R1
More informationNAME AND SURNAME. TIME: 1 hour 30 minutes 1/6
E.T.S.E.T.B. MSc in ICT FINAL EXAM VLSI Digital Design Spring Course 2005-2006 June 6, 2006 Score publication date: June 19, 2006 Exam review request deadline: June 22, 2006 Academic consultancy: June
More informationWeste04r4.fm Page 67 Monday, January 5, 2004 1:24 AM. 4.1 Introduction
Weste04r4.fm Page 67 Monday, January 5, 2004 1:24 AM 4 4.1 Introduction In Chapter 1 we learned how to make chips that work. Now we move on to making chips that work well,where well can be defined as fast,
More informationBasic Logic Gates Richard E. Haskell
BASIC LOGIC GATES 1 E Basic Logic Gates Richard E. Haskell All digital systems are made from a few basic digital circuits that we call logic gates. These circuits perform the basic logic functions that
More informationINSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043
INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043 ELECTRONICS AND COMMUNICATION ENGINEERING Course Title VLSI DESIGN Course Code 57035 Regulation R09 COURSE DESCRIPTION Course Structure
More informationLecture 10: Latch and Flip-Flop Design. Outline
Lecture 1: Latch and Flip-Flop esign Slides orginally from: Vladimir Stojanovic Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in latches and flip-flops
More informationISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7
ISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7 13.7 A 40Gb/s Clock and Data Recovery Circuit in 0.18µm CMOS Technology Jri Lee, Behzad Razavi University of California, Los Angeles, CA
More informationCMOS Logic Integrated Circuits
CMOS Logic Integrated Circuits Introduction CMOS Inverter Parameters of CMOS circuits Circuits for protection Output stage for CMOS circuits Buffering circuits Introduction Symetrical and complementary
More informationLFSR BASED COUNTERS AVINASH AJANE, B.E. A technical report submitted to the Graduate School. in partial fulfillment of the requirements
LFSR BASED COUNTERS BY AVINASH AJANE, B.E A technical report submitted to the Graduate School in partial fulfillment of the requirements for the degree Master of Science in Electrical Engineering New Mexico
More informationLayout of Multiple Cells
Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed
More informationElementary Logic Gates
Elementary Logic Gates Name Symbol Inverter (NOT Gate) ND Gate OR Gate Truth Table Logic Equation = = = = = + C. E. Stroud Combinational Logic Design (/6) Other Elementary Logic Gates NND Gate NOR Gate
More informationS. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India
Power reduction on clock-tree using Energy recovery and clock gating technique S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India Abstract Power consumption of
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationA high Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
A high Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha Abstract The paper proposes the novel design of a 3T
More informationThese help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption
Basic Properties of a Digital Design These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption Which of these criteria is important
More informationELEC 2210 - EXPERIMENT 1 Basic Digital Logic Circuits
Objectives ELEC - EXPERIMENT Basic Digital Logic Circuits The experiments in this laboratory exercise will provide an introduction to digital electronic circuits. You will learn how to use the IDL-00 Bit
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
More informationField-Effect (FET) transistors
Field-Effect (FET) transistors References: Hayes & Horowitz (pp 142-162 and 244-266), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and,
More informationMETHODOLOGICAL CONSIDERATIONS OF DRIVE SYSTEM SIMULATION, WHEN COUPLING FINITE ELEMENT MACHINE MODELS WITH THE CIRCUIT SIMULATOR MODELS OF CONVERTERS.
SEDM 24 June 16th - 18th, CPRI (Italy) METHODOLOGICL CONSIDERTIONS OF DRIVE SYSTEM SIMULTION, WHEN COUPLING FINITE ELEMENT MCHINE MODELS WITH THE CIRCUIT SIMULTOR MODELS OF CONVERTERS. Áron Szûcs BB Electrical
More informationPerformance of Flip-Flop Using 22nm CMOS Technology
Performance of Flip-Flop Using 22nm CMOS Technology K.Rajasri 1, A.Bharathi 2, M.Manikandan 3 M.E, Applied Electronics, IFET College of Engineering, Villupuram, India 1, 2 Assistant Professor, Department
More informationASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
More informationTrue Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique
True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique Priyanka Sharma ME (ECE) Student NITTTR Chandigarh Rajesh Mehra Associate Professor Department of ECE NITTTR Chandigarh
More informationDigital Logic Elements, Clock, and Memory Elements
Physics 333 Experiment #9 Fall 999 Digital Logic Elements, Clock, and Memory Elements Purpose This experiment introduces the fundamental circuit elements of digital electronics. These include a basic set
More informationFault Modeling. Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults. Transistor faults Summary
Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at
More informationFloating Point Fused Add-Subtract and Fused Dot-Product Units
Floating Point Fused Add-Subtract and Fused Dot-Product Units S. Kishor [1], S. P. Prakash [2] PG Scholar (VLSI DESIGN), Department of ECE Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu,
More informationUpon completion of unit 1.1, students will be able to
Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal
More informationSequential Logic: Clocks, Registers, etc.
ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design
More informationCHAPTER 16 MEMORY CIRCUITS
CHPTER 6 MEMORY CIRCUITS Chapter Outline 6. atches and Flip-Flops 6. Semiconductor Memories: Types and rchitectures 6.3 Random-ccess Memory RM Cells 6.4 Sense-mplifier and ddress Decoders 6.5 Read-Only
More informationCHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS
CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS Chapter Outline 10.1 The Two-Stage CMOS Op Amp 10.2 The Folded-Cascode CMOS Op Amp 10.3 The 741 Op-Amp Circuit 10.4 DC Analysis of the 741 10.5 Small-Signal Analysis
More informationA Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology
International Journal of Computer Sciences and Engineering Open Access Research Paper Volume-4, Issue-1 E-ISSN: 2347-2693 A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology Zahra
More informationCancellation of Load-Regulation in Low Drop-Out Regulators
Cancellation of Load-Regulation in Low Drop-Out Regulators Rajeev K. Dokania, Student Member, IEE and Gabriel A. Rincόn-Mora, Senior Member, IEEE Georgia Tech Analog Consortium Georgia Institute of Technology
More informationVENDING MACHINE. ECE261 Project Proposal Presentaion. Members: ZHANG,Yulin CHEN, Zhe ZHANG,Yanni ZHANG,Yayuan
VENDING MACHINE ECE261 Project Proposal Presentaion Members: ZHANG,Yulin CHEN, Zhe ZHANG,Yanni ZHANG,Yayuan Abstract This project will design and implement a coin operated vending machine controller The
More informationUsing Op Amps As Comparators
TUTORIAL Using Op Amps As Comparators Even though op amps and comparators may seem interchangeable at first glance there are some important differences. Comparators are designed to work open-loop, they
More informationDesign Verification and Test of Digital VLSI Circuits NPTEL Video Course. Module-VII Lecture-I Introduction to Digital VLSI Testing
Design Verification and Test of Digital VLSI Circuits NPTEL Video Course Module-VII Lecture-I Introduction to Digital VLSI Testing VLSI Design, Verification and Test Flow Customer's Requirements Specifications
More informationCMOS Thyristor Based Low Frequency Ring Oscillator
CMOS Thyristor Based Low Frequency Ring Oscillator Submitted by: PIYUSH KESHRI BIPLAB DEKA 4 th year Undergraduate Student 4 th year Undergraduate Student Electrical Engineering Dept. Electrical Engineering
More informationSeries and Parallel Circuits
Direct Current (DC) Direct current (DC) is the unidirectional flow of electric charge. The term DC is used to refer to power systems that use refer to the constant (not changing with time), mean (average)
More informationTopics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology
Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Two-phase clocking. Testing of combinational (Chapter 4) and sequential (Chapter
More informationBridgeless PFC Implementation Using One Cycle Control Technique
Bridgeless PFC Implementation Using One Cycle Control Technique Bing Lu Center for Power Electronics Systems Virginia Polytechnic Institute and State University 674 Whittemore Hall Blacksburg, VA 24061
More informationInterfacing 3V and 5V applications
Authors: Tinus van de Wouw (Nijmegen) / Todd Andersen (Albuquerque) 1.0 THE NEED FOR TERFACG BETWEEN 3V AND 5V SYSTEMS Many reasons exist to introduce 3V 1 systems, notably the lower power consumption
More informationStep Response of RC Circuits
Step Response of RC Circuits 1. OBJECTIVES...2 2. REFERENCE...2 3. CIRCUITS...2 4. COMPONENTS AND SPECIFICATIONS...3 QUANTITY...3 DESCRIPTION...3 COMMENTS...3 5. DISCUSSION...3 5.1 SOURCE RESISTANCE...3
More informationCurrent vs. Voltage Feedback Amplifiers
Current vs. ltage Feedback Amplifiers One question continuously troubles the analog design engineer: Which amplifier topology is better for my application, current feedback or voltage feedback? In most
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More informationApplication Note AN-940
Application Note AN-940 How P-Channel MOSFETs Can Simplify Your Circuit Table of Contents Page 1. Basic Characteristics of P-Channel HEXFET Power MOSFETs...1 2. Grounded Loads...1 3. Totem Pole Switching
More informationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 3, SEPTEMBER 1999 321
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 3, SEPTEMBER 1999 321 The Design of a SRAM-Based Field-Programmable Gate Array Part II: Circuit Design and Layout Paul Chow,
More informationPerformance Comparison of an Algorithmic Current- Mode ADC Implemented using Different Current Comparators
Performance Comparison of an Algorithmic Current- Mode ADC Implemented using Different Current Comparators Veepsa Bhatia Indira Gandhi Delhi Technical University for Women Delhi, India Neeta Pandey Delhi
More informationDIGITAL-TO-ANALOGUE AND ANALOGUE-TO-DIGITAL CONVERSION
DIGITAL-TO-ANALOGUE AND ANALOGUE-TO-DIGITAL CONVERSION Introduction The outputs from sensors and communications receivers are analogue signals that have continuously varying amplitudes. In many systems
More informationDesign of a Fully Differential Two-Stage CMOS Op-Amp for High Gain, High Bandwidth Applications
Design of a Fully Differential Two-Stage CMOS Op-Amp for High Gain, High Bandwidth Applications Rajkumar S. Parihar Microchip Technology Inc. Rajkumar.parihar@microchip.com Anu Gupta Birla Institute of
More informationOp-Amp Simulation EE/CS 5720/6720. Read Chapter 5 in Johns & Martin before you begin this assignment.
Op-Amp Simulation EE/CS 5720/6720 Read Chapter 5 in Johns & Martin before you begin this assignment. This assignment will take you through the simulation and basic characterization of a simple operational
More informationLOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP
LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP Anurag #1, Gurmohan Singh #2, V. Sulochana #3 # Centre for Development of Advanced Computing, Mohali, India 1 anuragece09@gmail.com 2 gurmohan@cdac.in
More informationChapter 19 Operational Amplifiers
Chapter 19 Operational Amplifiers The operational amplifier, or op-amp, is a basic building block of modern electronics. Op-amps date back to the early days of vacuum tubes, but they only became common
More informationContent Map For Career & Technology
Content Strand: Applied Academics CT-ET1-1 analysis of electronic A. Fractions and decimals B. Powers of 10 and engineering notation C. Formula based problem solutions D. Powers and roots E. Linear equations
More informationTransistor Amplifiers
Physics 3330 Experiment #7 Fall 1999 Transistor Amplifiers Purpose The aim of this experiment is to develop a bipolar transistor amplifier with a voltage gain of minus 25. The amplifier must accept input
More informationEMI in Electric Vehicles
EMI in Electric Vehicles S. Guttowski, S. Weber, E. Hoene, W. John, H. Reichl Fraunhofer Institute for Reliability and Microintegration Gustav-Meyer-Allee 25, 13355 Berlin, Germany Phone: ++49(0)3046403144,
More informationChapter 2 Basic Structure of Computers. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 Basic Structure of Computers Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Functional Units Basic Operational Concepts Bus Structures Software
More informationMonte Carlo Simulation of Device Variations and Mismatch in Analog Integrated Circuits
Proceedings of The National Conference On Undergraduate Research (NCUR) 2006 The University of North Carolina at Asheville Asheville, North Carolina April 6 8, 2006 Monte Carlo Simulation of Device Variations
More informationAnalysis and Design of High gain Low Power Fully Differential Gain- Boosted Folded-Cascode Op-amp with Settling time optimization
Analysis and Design of High gain Low Power Fully Differential Gain- Boosted Folded-Cascode Op-amp with Settling time optimization Shubhara Yewale * and R. S. Gamad ** * (Department of Electronics & Instrumentation
More informationNotes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits
Notes about Small Signal Model for EE 40 Intro to Microelectronic Circuits 1. Model the MOSFET Transistor For a MOSFET transistor, there are NMOS and PMOS. The examples shown here would be for NMOS. Figure
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationAn Introduction to the EKV Model and a Comparison of EKV to BSIM
An Introduction to the EKV Model and a Comparison of EKV to BSIM Stephen C. Terry 2. 3.2005 Integrated Circuits & Systems Laboratory 1 Overview Characterizing MOSFET operating regions EKV model fundamentals
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #4 Solutions EECS141 PROBLEM 1: Shoot-Through Current In this problem,
More informationA New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits
A New Reversible TSG Gate and Its Application For Designing Efficient Adder s Himanshu Thapliyal Center for VLSI and Embedded System Technologies International Institute of Information Technology Hyderabad-500019,
More informationKarnaugh Maps & Combinational Logic Design. ECE 152A Winter 2012
Karnaugh Maps & Combinational Logic Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 4 Optimized Implementation of Logic Functions 4. Karnaugh Map 4.2 Strategy for Minimization 4.2. Terminology
More information