Combinational-Circuit Building Blocks

Transcription

1 May 9, 24 :4 vra6857_ch6 Sheet number Page number 35 black chapter 6 Combinational-Circuit Building Blocks Chapter Objectives In this chapter you will learn about: Commonly used combinational subcircuits Multiplexers, which can be used or selection o signals and or implementation o general logic unctions Circuits used or encoding, decoding, and code-conversion purposes Key VHDL constructs used to deine combinational circuits 35

2 May 9, 24 :4 vra6857_ch6 Sheet number 2 Page number 36 black 36 CHAPTER 6 Combinational-Circuit Building Blocks Previous chapters have introduced the basic techniques or design o logic circuits. In practice, a ew types o logic circuits are oten used as building blocks in larger designs. This chapter discusses a number o these blocks and gives examples o their use. The chapter also includes a major section on VHDL, which describes several key eatures o the language. 6. Multiplexers Multiplexers were introduced briely in Chapters 2 and 3. A multiplexer circuit has a number o data inputs, one or more select inputs, and one output. It passes the signal value on one o the data inputs to the output. The data input is selected by the values o the select inputs. Figure 6. shows a 2-to- multiplexer. Part (a) gives the symbol commonly used. The select input, s, chooses as the output o the multiplexer either input w or w. The multiplexer s unctionality can be described in the orm o a truth table as shown in part (b) o the igure. Part (c) gives a sum-o-products implementation o the 2-to- multiplexer, and part (d) illustrates how it can be constructed with transmission gates. Figure 6.2a depicts a larger multiplexer with our data inputs, w,...,, and two select inputs, s and s. As shown in the truth table in part (b) o the igure, the two-bit number represented by s s selects one o the data inputs as the output o the multiplexer. s s w w w w (a) Graphical symbol (b) Truth table w w s s w w (c) Sum-o-products circuit (d) Circuit with transmission gates Figure 6. A 2-to- multiplexer.

3 May 9, 24 :4 vra6857_ch6 Sheet number 3 Page number 37 black 6. Multiplexers 37 s s s s w w w w (a) Graphical symbol (b) Truth table s s w w (c) Circuit Figure 6.2 A 4-to- multiplexer. A sum-o-products implementation o the 4-to- multiplexer appears in Figure 6.2c. It realizes the multiplexer unction = s s w + s s w + s s + s s It is possible to build larger multiplexers using the same approach. Usually, the number o data inputs, n, is an integer power o two. A multiplexer that has n data inputs, w,...,w n, requires log 2 n select inputs. Larger multiplexers can also be constructed rom smaller multiplexers. For example, the 4-to- multiplexer can be built using three 2-to- multiplexers as illustrated in Figure 6.3. I the 4-to- multiplexer is implemented using transmission gates, then the structure in this igure is always used. Figure 6.4 shows how a 6-to- multiplexer is constructed with ive 4-to- multiplexers.

4 May 9, 24 :4 vra6857_ch6 Sheet number 4 Page number 38 black 38 CHAPTER 6 Combinational-Circuit Building Blocks s s w w Figure 6.3 Using 2-to- multiplexers to build a 4-to- multiplexer. s s w w 4 s 2 s 3 w 7 w 8 w w 5 Figure 6.4 A 6-to- multiplexer.

5 May 9, 24 :4 vra6857_ch6 Sheet number 5 Page number 39 black 6. Multiplexers 39 Figure 6.5 shows a circuit that has two inputs, x and x 2, and two outputs, y and y 2.As indicated by the blue lines, the unction o the circuit is to allow either o its inputs to be connected to either o its outputs, under the control o another input, s. A circuit that has n inputs and k outputs, whose sole unction is to provide a capability to connect any input to any output, is usually reerred to as an n k crossbar switch. Crossbars o various sizes can be created, with dierent numbers o inputs and outputs. When there are two inputs and two outputs, it is called a 2 2 crossbar. Figure 6.5b shows how the 2 2 crossbar can be implemented using 2-to- multiplexers. The multiplexer select inputs are controlled by the signal s. I s =, the crossbar connects x to y and x 2 to y 2, while i s =, the crossbar connects x to y 2 and x 2 to y. Crossbar switches are useul in many practical applications in which it is necessary to be able to connect one set o wires to another set o wires, where the connection pattern changes rom time to time. Example 6. We introduced ield-programmable gate array (FPGA) chips in section Figure 3.39 depicts a small FPGA that is programmed to implement a particular circuit. The logic blocks in the FPGA have two inputs, and there are our tracks in each routing channel. Each o the programmable switches that connects a logic block input or output to an interconnection wire is shown as an X. A small part o Figure 3.39 is reproduced in Figure 6.6a. For clarity, Example 6.2 s x y x 2 y 2 (a) A 2x2 crossbar switch x y s x 2 y 2 (b) Implementation using multiplexers Figure 6.5 A practical application o multiplexers.

6 May 9, 24 :4 vra6857_ch6 Sheet number 6 Page number 32 black 32 CHAPTER 6 Combinational-Circuit Building Blocks i i 2 (a) Part o the FPGA in Figure 3.39 / / / / i i 2 Storage cell / / / / (b) Implementation using pass transistors / / i i 2 / / (c) Implementation using multiplexers Figure 6.6 Implementing programmable switches in an FPGA.

7 May 9, 24 :4 vra6857_ch6 Sheet number 7 Page number 32 black 6. Multiplexers 32 the igure shows only a single logic block and the interconnection wires and switches associated with its input terminals. One way in which the programmable switches can be implemented is illustrated in Figure 6.6b. Each X in part (a) o the igure is realized using an NMOS transistor controlled by a storage cell. This type o programmable switch was also shown in Figure We described storage cells briely in section and will discuss them in more detail in section.. Each cell stores a single logic value, either or, and provides this value as the output o the cell. Each storage cell is built by using several transistors. Thus the eight cells shown in the igure use a signiicant amount o chip area. The number o storage cells needed can be reduced by using multiplexers, as shown in Figure 6.6c. Each logic block input is ed by a 4-to- multiplexer, with the select inputs controlled by storage cells. This approach requires only our storage cells, instead o eight. In commercial FPGAs the multiplexer-based approach is usually adopted. 6.. Synthesis o Logic Functions Using Multiplexers Multiplexers are useul in many practical applications, such as those described above. They can also be used in a more general way to synthesize logic unctions. Consider the example in Figure 6.7a. The truth table deines the unction = w. This unction can be implemented by a 4-to- multiplexer in which the values o in each row o the truth table are connected as constants to the multiplexer data inputs. The multiplexer select inputs are driven by w and. Thus or each valuation o w, the output is equal to the unction value in the corresponding row o the truth table. The above implementation is straightorward, but it is not very eicient. A better implementation can be derived by manipulating the truth table as indicated in Figure 6.7b, which allows to be implemented by a single 2-to- multiplexer. One o the input signals, w in this example, is chosen as the select input o the 2-to- multiplexer. The truth table is redrawn to indicate the value o or each value o w. When w =, has the same value as input, and when w =, has the value o. The circuit that implements this truth table is given in Figure 6.7c. This procedure can be applied to synthesize a circuit that implements any logic unction. Figure 6.8a gives the truth table or the three-input majority unction, and it shows how the truth table can be modiied to implement the unction using a 4-to- multiplexer. Any two o the three inputs may be chosen as the multiplexer select inputs. We have chosen w and or this purpose, resulting in the circuit in Figure 6.8b. Example 6.3

8 May 9, 24 :4 vra6857_ch6 Sheet number 8 Page number 322 black 322 CHAPTER 6 Combinational-Circuit Building Blocks w w (a) Implementation using a 4-to- multiplexer w w w2 (b) Modiied truth table w (c) Circuit Figure 6.7 Synthesis o a logic unction using mutiplexers. Example 6.4 Figure 6.9a indicates how the unction = w can be implemented using 2-to- multiplexers. When w =, is equal to the XOR o and, and when w =, is the XNOR o and. The let multiplexer in the circuit produces, using the result rom Figure 6.7, and the right multiplexer uses the value o w to select either or its complement. Note that we could have derived this circuit directly by writing the unction as = ( ) w. Figure 6. gives an implementation o the three-input XOR unction using a 4-to- multiplexer. Choosing w and or the select inputs results in the circuit shown.

9 May 9, 24 :4 vra6857_ch6 Sheet number 9 Page number 323 black 6. Multiplexers 323 w w (a) Modiied truth table w (b) Circuit Figure 6.8 Implementation o the three-input majority unction using a 4-to- multiplexer. w w (a) Truth table (b) Circuit Figure 6.9 Three-input XOR implemented with 2-to- multiplexers.

10 May 9, 24 :4 vra6857_ch6 Sheet number Page number 324 black 324 CHAPTER 6 Combinational-Circuit Building Blocks w w (a) Truth table (b) Circuit Figure 6. Three-input XOR implemented with a 4-to- multiplexer Multiplexer Synthesis Using Shannon s Expansion Figures 6.8 through 6. illustrate how truth tables can be interpreted to implement logic unctions using multiplexers. In each case the inputs to the multiplexers are the constants and, or some variable or its complement. Besides using such simple inputs, it is possible to connect more complex circuits as inputs to a multiplexer, allowing unctions to be synthesized using a combination o multiplexers and other logic gates. Suppose that we want to implement the three-input majority unction in Figure 6.8 using a 2-to- multiplexer in this way. Figure 6. shows an intuitive way o realizing this unction. The truth table can be modiied as shown on the right. I w =, then =, and i w =, then = +. Using w as the select input or a 2-to- multiplexer leads to the circuit in Figure 6.b. This implementation can be derived using algebraic manipulation as ollows. The unction in Figure 6.a is expressed in sum-o-products orm as = w + w + w + w It can be manipulated into = w ( ) + w ( + + ) = w ( ) + w ( + ) which corresponds to the circuit in Figure 6.b. Multiplexer implementations o logic unctions require that a given unction be decomposed in terms o the variables that are used as the select inputs. This can be accomplished by means o a theorem proposed by Claude Shannon [].

11 May 9, 24 :4 vra6857_ch6 Sheet number Page number 325 black 6. Multiplexers 325 w w w2 w3 + (a) Truth table w2 w (b) Circuit Figure 6. The three-input majority unction implemented using a 2-to- multiplexer. Shannon s Expansion Theorem Any Boolean unction (w,...,w n ) can be written in the orm (w,,...,w n ) = w (,,...,w n ) + w (,,...,w n ) This expansion can be done in terms o any o the n variables. We will leave the proo o the theorem as an exercise or the reader (see problem 6.9). To illustrate its use, we can apply the theorem to the three-input majority unction, which can be written as (w,, ) = w + w + Expanding this unction in terms o w gives = w ( ) + w ( + ) which is the expression that we derived above.

12 May 9, 24 :4 vra6857_ch6 Sheet number 2 Page number 326 black 326 CHAPTER 6 Combinational-Circuit Building Blocks For the three-input XOR unction, we have = w = w ( ) + w ( ) which gives the circuit in Figure 6.9b. In Shannon s expansion the term (,,...,w n ) is called the coactor o with respect to w ; it is denoted in shorthand notation as w. Similarly, the term (,,...,w n ) is called the coactor o with respect to w, written w. Hence we can write = w w + w w In general, i the expansion is done with respect to variable w i, then wi (w,...,w i,, w i+,...,w n ) and denotes (w,...,w n ) = w i wi + w i wi The complexity o the logic expression may vary, depending on which variable, w i, is used, as illustrated in Example 6.5. Example 6.5 For the unction = w +, decomposition using w gives Using instead o w produces Finally, using gives = w w + w w = w ( + ) + w ( ) = w2 + w2 = (w ) + (w + ) = w3 + w3 = ( ) + (w ) The results generated using w and have the same cost, but the expression produced using has a lower cost. In practice, the CAD tools that perorm decompositions o this type try a number o alternatives and choose the one that produces the best result. Shannon s expansion can be done in terms o more than one variable. For example, expanding a unction in terms o w and gives (w,...,w n ) = w (,,,...,w n ) + w (,,,...,w n ) + w (,,,, w n ) + w (,,,...,w n ) This expansion gives a orm that can be implemented using a 4-to- multiplexer. I Shannon s expansion is done in terms o all n variables, then the result is the canonical sum-oproducts orm, which was deined in section 2.6..

13 May 9, 24 :4 vra6857_ch6 Sheet number 3 Page number 327 black 6. Multiplexers 327 w (a) Using a 2-to- multiplexer w (b) Using a 4-to- multiplexer Figure 6.2 The circuits synthesized in Example 6.6. Assume that we wish to implement the unction Example 6.6 = w + w + w using a 2-to- multiplexer and any other necessary gates. Shannon s expansion using w gives = w w + w w = w ( ) + w ( + ) The corresponding circuit is shown in Figure 6.2a. Assume now that we wish to use a 4-to- multiplexer instead. Further decomposition using gives = w w + w w + w w + w w = w ( ) + w ( ) + w ( ) + w () The circuit is shown in Figure 6.2b. Consider the three-input majority unction Example 6.7 = w + w +

14 May 9, 24 :4 vra6857_ch6 Sheet number 4 Page number 328 black 328 CHAPTER 6 Combinational-Circuit Building Blocks w Figure 6.3 The circuit synthesized in Example 6.7. We wish to implement this unction using only 2-to- multiplexers. Shannon s expansion using w yields = w ( ) + w ( + + ) = w ( ) + w ( + ) Let g = and h = +. Expansion o both g and h using gives g = () + ( ) h = ( ) + () The corresponding circuit is shown in Figure 6.3. It is equivalent to the 4-to- multiplexer circuit derived using a truth table in Figure 6.8. Example 6.8 In section we said that most FPGAs use lookup tables or their logic blocks. Assume that an FPGA exists in which each logic block is a three-input lookup table (3-LUT). Because it stores a truth table, a 3-LUT can realize any logic unction o three variables. Using Shannon s expansion, any our-variable unction can be realized with at most three 3-LUTs. Consider the unction Expansion in terms o w produces = w w + w w = + w + w 4 + w w 4 = w ( + + w 4 ) + w ( + w 4 + w 4 ) = w ( + ) + w ( + w 4 + w 4 ) A circuit with three 3-LUTs that implements this expression is shown in Figure 6.4a. Decomposition o the unction using, instead o w, gives = w2 + w2 = ( + w w 4 ) + (w + w 4 )

15 May 9, 24 :4 vra6857_ch6 Sheet number 5 Page number 329 black 6.2 Decoders 329 w w w w 4 (a) Using three 3-LUTs w w 4 w2 (b) Using two 3-LUTs Figure 6.4 Circuits synthesized in Example 6.8. Observe that w2 = w2 ; hence only two 3-LUTs are needed, as illustrated in Figure 6.4b. The LUT on the right implements the two-variable unction w2 + w2. Since it is possible to implement any logic unction using multiplexers, general-purpose chips exist that contain multiplexers as their basic logic resources. Both Actel Corporation [2] and QuickLogic Corporation [3] oer FPGAs in which the logic block comprises an arrangement o multiplexers. Texas Instruments oers gate array chips that have multiplexerbased logic blocks [4]. 6.2 Decoders Decoder circuits are used to decode encoded inormation. A binary decoder, depicted in Figure 6.5, is a logic circuit with n inputs and 2 n outputs. Only one output is asserted at a time, and each output corresponds to one valuation o the inputs. The decoder also has an enable input, En, that is used to disable the outputs; i En =, then none o the decoder outputs is asserted. I En =, the valuation o w n w w determines which o the outputs is asserted. An n-bit binary code in which exactly one o the bits is set to at a

16 May 9, 24 :4 vra6857_ch6 Sheet number 6 Page number 33 black 33 CHAPTER 6 Combinational-Circuit Building Blocks w y n inputs w n 2 n outputs Enable En y 2 n Figure 6.5 An n-to-2 n binary decoder. time is reerred to as one-hot encoded, meaning that the single bit that is set to is deemed to be hot. The outputs o a binary decoder are one-hot encoded. A 2-to-4 decoder is given in Figure 6.6. The two data inputs are w and w. They represent a two-bit number that causes the decoder to assert one o the outputs y,...,y 3. Although a decoder can be designed to have either active-high or active-low outputs, in En w w y y y 2 y 3 x x w y w y y 2 En y 3 (a) Truth table (b) Graphical symbol w y w y y 2 y 3 En (c) Logic circuit Figure 6.6 A 2-to-4 decoder.

17 May 9, 24 :4 vra6857_ch6 Sheet number 7 Page number 33 black 6.2 Decoders 33 w w y y w w y y y 2 y 2 En y 3 y 3 En w y y 4 w y y 5 En y 2 y 3 y 6 y 7 Figure 6.7 A 3-to-8 decoder using two 2-to-4 decoders. Figure 6.6 active-high outputs are assumed. Setting the inputs w w to,,, or causes the output y, y, y 2,ory 3 to be set to, respectively. A graphical symbol or the decoder is given in part (b) o the igure, and a logic circuit is shown in part (c). Larger decoders can be built using the sum-o-products structure in Figure 6.6c, or else they can be constructed rom smaller decoders. Figure 6.7 shows how a 3-to-8 decoder is built with two 2-to-4 decoders. The input drives the enable inputs o the two decoders. The top decoder is enabled i =, and the bottom decoder is enabled i =. This concept can be applied or decoders o any size. Figure 6.8 shows how ive 2-to-4 decoders can be used to construct a 4-to-6 decoder. Because o its treelike structure, this type o circuit is oten reerred to as a decoder tree. Decoders are useul or many practical purposes. In Figure 6.2c we showed the sum-oproducts implementation o the 4-to- multiplexer, which requires AND gates to distinguish the our dierent valuations o the select inputs s and s. Since a decoder evaluates the values on its inputs, it can be used to build a multiplexer as illustrated in Figure 6.9. The enable input o the decoder is not needed in this case, and it is set to. The our outputs o the decoder represent the our valuations o the select inputs. Example 6.9 In Figure 3.59 we showed how a 2-to- multiplexer can be constructed using two tri-state buers. This concept can be applied to any size o multiplexer, with the addition o a decoder. An example is shown in Figure 6.2. The decoder enables one o the tri-state buers or each valuation o the select lines, and that tri-state buer drives the output,, with the selected data input. We have now seen that multiplexers can be implemented in various ways. The choice o whether to employ the sum-o-products orm, transmission gates, or tri-state buers depends on the resources available in the chip being used. For instance, most FPGAs that use lookup tables or their logic blocks do not contain tri-state Example 6.

18 May 9, 24 :4 vra6857_ch6 Sheet number 8 Page number 332 black 332 CHAPTER 6 Combinational-Circuit Building Blocks w w y y w w y y En y 2 y 3 y 2 y 3 w y y 4 w y y 5 y 2 y 6 w y En y 3 y 7 w y y 2 En En y 3 w y y 8 w y y 9 En y 2 y 3 y y w y y 2 w y y 3 En y 2 y 3 y 4 y 5 Figure 6.8 A 4-to-6 decoder built using a decoder tree. w w s s w y w y y 2 En y 3 Figure 6.9 A 4-to- multiplexer built using a decoder.

19 May 9, 24 :4 vra6857_ch6 Sheet number 9 Page number 333 black 6.2 Decoders 333 w s w y w s w y y 2 En y 3 Figure 6.2 A 4-to- multiplexer built using a decoder and tri-state buers. buers. Hence multiplexers must be implemented in the sum-o-products orm using the lookup tables (see Example 6.3) Demultiplexers We showed in section 6. that a multiplexer has one output, n data inputs, and log 2 n select inputs. The purpose o the multiplexer circuit is to multiplex the n data inputs onto the single data output under control o the select inputs. A circuit that perorms the opposite unction, namely, placing the value o a single data input onto multiple data outputs, is called a demultiplexer. The demultiplexer can be implemented using a decoder circuit. For example, the 2-to-4 decoder in Figure 6.6 can be used as a -to-4 demultiplexer. In this case the En input serves as the data input or the demultiplexer, and the y to y 3 outputs are the data outputs. The valuation o w w determines which o the outputs is set to the value o En. To see how the circuit works, consider the truth table in Figure 6.6a. When En =, all the outputs are set to, including the one selected by the valuation o w w. When En =, the valuation o w w sets the appropriate output to. In general, an n-to-2 n decoder circuit can be used as a -to-n demultiplexer. However, in practice decoder circuits are used much more oten as decoders rather than as demultiplexers. In many applications the decoder s En input is not actually needed; hence it can be omitted. In this case the decoder always asserts one o its data outputs, y,...,y 2 n, according to the valuation o the data inputs, w n w. Example 6. uses a decoder that does not have the En input.

20 May 9, 24 :4 vra6857_ch6 Sheet number 2 Page number 334 black 334 CHAPTER 6 Combinational-Circuit Building Blocks Example 6. One o the most important applications o decoders is in memory blocks, which are used to store inormation. Such memory blocks are included in digital systems, such as computers, where there is a need to store large amounts o inormation electronically. One type o memory block is called a read-only memory (ROM). A ROM consists o a collection o storage cells, where each cell permanently stores a single logic value, either or. Figure 6.2 shows an example o a ROM block. The storage cells are arranged in 2 m rows with n cells per row. Thus each row stores n bits o inormation. The location o each row in the ROM is identiied by its address. In the igure the row at the top o the ROM has address, and the row at the bottom has address 2 m. The inormation stored in the rows can be accessed by asserting the select lines, Sel to Sel 2 m. As shown in the igure, a decoder with m inputs and 2 m outputs is used to generate the signals on the select lines. Since the inputs to the decoder choose the particular address (row) selected, they are called the address lines. The inormation stored in the row appears on the data outputs o the ROM, d n,...,d, which are called the data lines. Figure 6.2 shows that each data line has an associated tri-state buer that is enabled by the ROM input named Read. To access, or read, data rom the ROM, the address o the desired row is placed on the address lines and Read is set to. Sel / / / Sel / / / Address a a a m m-to-2 m decoder Sel 2 / / / Sel m 2 / / / Read Data d n d n 2 d Figure 6.2 A 2 m n read-only memory (ROM) block.

21 May 9, 24 :4 vra6857_ch6 Sheet number 2 Page number 335 black 6.3 Encoders 335 Many dierent types o memory blocks exist. In a ROM the stored inormation can be read out o the storage cells, but it cannot be changed (see problem 6.32). Another type o ROM allows inormation to be both read out o the storage cells and stored, or written, into them. Reading its contents is the normal operation, whereas writing requires a special procedure. Such a memory block is called a programmable ROM (PROM). The storage cells in a PROM are usually implemented using EEPROM transistors. We discussed EEPROM transistors in section 3. to show how they are used in PLDs. Other types o memory blocks are discussed in section Encoders An encoder perorms the opposite unction o a decoder. It encodes given inormation into a more compact orm Binary Encoders A binary encoder encodes inormation rom 2 n inputs into an n-bit code, as indicated in Figure Exactly one o the input signals should have a value o, and the outputs present the binary number that identiies which input is equal to. The truth table or a 4-to-2 encoder is provided in Figure 6.23a. Observe that the output y is when either input w or is, and output y is when input or is. Hence these outputs can be generated by the circuit in Figure 6.23b. Note that we assume that the inputs are one-hot encoded. All input patterns that have multiple inputs set to are not shown in the truth table, and they are treated as don t-care conditions. Encoders are used to reduce the number o bits needed to represent given inormation. A practical use o encoders is or transmitting inormation in a digital system. Encoding the inormation allows the transmission link to be built using ewer wires. Encoding is also useul i inormation is to be stored or later use because ewer bits need to be stored. w 2 n inputs n y y n n outputs Figure 6.22 A 2 n -to-n binary encoder.

22 May 9, 24 :4 vra6857_ch6 Sheet number 22 Page number 336 black 336 CHAPTER 6 Combinational-Circuit Building Blocks w w y y (a) Truth table w w y y (b) Circuit Figure 6.23 A 4-to-2 binary encoder Priority Encoders Another useul class o encoders is based on the priority o input signals. In a priority encoder each input has a priority level associated with it. The encoder outputs indicate the active input that has the highest priority. When an input with a high priority is asserted, the other inputs with lower priority are ignored. The truth table or a 4-to-2 priority encoder is shown in Figure It assumes that w has the lowest priority and the highest. The outputs y and y represent the binary number that identiies the highest priority input set to. Since it is possible that none o the inputs is equal to, an output, z, is provided to indicate this condition. It is set to when at least one o the inputs is equal to. It is set to w w y y z x x x x x x d d Figure 6.24 Truth table or a 4-to-2 priority encoder.

23 May 9, 24 :4 vra6857_ch6 Sheet number 23 Page number 337 black 6.4 Code Converters 337 when all inputs are equal to. The outputs y and y are not meaningul in this case, and hence the irst row o the truth table can be treated as a don t-care condition or y and y. The behavior o the priority encoder is most easily understood by irst considering the last row in the truth table. It speciies that i input is, then the outputs are set to y y =. Because has the highest priority level, the values o inputs, w, and w do not matter. To relect the act that their values are irrelevant,, w, and w are denoted by the symbol x in the truth table. The second-last row in the truth table stipulates that i =, then the outputs are set to y y =, but only i =. Similarly, input w causes the outputs to be set to y y = only i both and are. Input w produces the outputs y y = only i w is the only input that is asserted. Alogic circuit that implements the truth table can be synthesized by using the techniques developed in Chapter 4. However, a more convenient way to derive the circuit is to deine a set o intermediate signals, i,...,i 3, based on the observations above. Each signal, i k, is equal to only i the input with the same index, w k, represents the highest-priority input that is set to. The logic expressions or i,...,i 3 are i = w w i = w i 2 = i 3 = Using the intermediate signals, the rest o the circuit or the priority encoder has the same structure as the binary encoder in Figure 6.23, namely The output z is given by y = i + i 3 y = i 2 + i 3 z = i + i + i 2 + i Code Converters The purpose o the decoder and encoder circuits is to convert rom one type o input encoding to a dierent output encoding. For example, a 3-to-8 binary decoder converts rom a binary number on the input to a one-hot encoding at the output. An 8-to-3 binary encoder perorms the opposite conversion. There are many other possible types o code converters. One common example is a BCD-to-7-segment decoder, which converts one binary-coded decimal (BCD) digit into inormation suitable or driving a digit-oriented display. As illustrated in Figure 6.25a, the circuit converts the BCD digit into seven signals that are used to drive the segments in the display. Each segment is a small light-emitting diode (LED), which glows when driven by an electrical signal. The segments are labeled rom a to g in the igure. The truth table or the BCD-to-7-segment decoder is given in Figure 6.25c. For each valuation o the inputs,...,w, the seven outputs are set to

24 May 9, 24 :4 vra6857_ch6 Sheet number 24 Page number 338 black 338 CHAPTER 6 Combinational-Circuit Building Blocks c e w a b w c d e g (c) Truth table (a) Code converter w a w b c d e g a g b d (b) 7-segment display Figure 6.25 A BCD-to-7-segment display code converter. display the appropriate BCD digit. Note that the last 6 rows o a complete 6-row truth table are not shown. They represent don t-care conditions because they are not legal BCD codes and will never occur in a circuit that deals with BCD data. A circuit that implements the truth table can be derived using the synthesis techniques discussed in Chapter 4. Finally, we should note that although the word decoder is traditionally used or this circuit, a more appropriate term is code converter. The term decoder is more appropriate or circuits that produce one-hot encoded outputs. 6.5 Arithmetic Comparison Circuits Chapter 5 presented arithmetic circuits that perorm addition, subtraction, and multiplication o binary numbers. Another useul type o arithmetic circuit compares the relative sizes o two binary numbers. Such a circuit is called a comparator. This section considers the

25 May 9, 24 :4 vra6857_ch6 Sheet number 25 Page number 339 black 6.6 VHDL or Combinational Circuits 339 design o a comparator that has two n-bit inputs, A and B, which represent unsigned binary numbers. The comparator produces three outputs, called AeqB, AgtB, and AltB. The AeqB output is set to i A and B are equal. The AgtB output is i A is greater than B, and the AltB output is i A is less than B. The desired comparator can be designed by creating a truth table that speciies the three outputs as unctions o A and B. However, even or moderate values o n, the truth table is large. A better approach is to derive the comparator circuit by considering the bits o A and B in pairs. We can illustrate this by a small example, where n = 4. Let A = a 3 a 2 a a and B = b 3 b 2 b b. Deine a set o intermediate signals called i 3, i 2, i, and i. Each signal, i k, is i the bits o A and B with the same index are equal. That is, i k = a k b k. The comparator s AeqB output is then given by AeqB = i 3 i 2 i i An expression or the AgtB output can be derived by considering the bits o A and B in the order rom the most-signiicant bit to the least-signiicant bit. The irst bit-position, k, at which a k and b k dier determines whether A is less than or greater than B. Ia k = and b k =, then A < B. But i a k = and b k =, then A > B. The AgtB output is deined by AgtB = a 3 b 3 + i 3 a 2 b 2 + i 3 i 2 a b + i 3 i 2 i a b The i k signals ensure that only the irst digits, considered rom the let to the right, o A and B that dier determine the value o AgtB. The AltB output can be derived by using the other two outputs as AltB = AeqB + AgtB A logic circuit that implements the our-bit comparator circuit is shown in Figure This approach can be used to design a comparator or any value o n. Comparator circuits, like most logic circuits, can be designed in dierent ways. Another approach or designing a comparator circuit is presented in Example 5. in Chapter VHDL or Combinational Circuits Having presented a number o useul circuits that can be used as building blocks in larger circuits, we will now consider how such circuits can be described in VHDL. Rather than relying on the simple VHDL statements used in previous examples, such as logic expressions, we will speciy the circuits in terms o their behavior. We will also introduce a number o new VHDL constructs Assignment Statements VHDL provides several types o statements that can be used to assign logic values to signals. In the examples o VHDL code given so ar, only simple assignment statements have been used, either or logic or arithmetic expressions. This section introduces other types o

26 May 9, 24 :4 vra6857_ch6 Sheet number 26 Page number 34 black 34 CHAPTER 6 Combinational-Circuit Building Blocks a 3 i 3 b 3 a 2 i 2 b 2 AeqB a i b a i b AltB AgtB Figure 6.26 A our-bit comparator circuit. assignment statements, which are called selected signal assignments, conditional signal assignments, generate statements, i-then-else statements, and case statements Selected Signal Assignment A selected signal assignment allows a signal to be assigned one o several values, based on a selection criterion. Figure 6.27 shows how it can be used to describe a 2-to- multiplexer. The entity, named mux2to, has the inputs w, w, and s, and the output. The selected signal assignment begins with the keyword WITH, which speciies that s is to be used or the selection criterion. The two WHEN clauses state that is assigned the value o w when s = ; otherwise, is assigned the value o w. The WHEN clause that selects w uses the word OTHERS, instead o the value. This is required because the VHDL syntax speciies that a WHEN clause must be included or every possible value o the selection signal s.

27 May 9, 24 :4 vra6857_ch6 Sheet number 27 Page number 34 black 6.6 VHDL or Combinational Circuits 34 LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY mux2to IS PORT ( w, w, s : IN STD LOGIC ; : OUT STD LOGIC ) ; END mux2to ; ARCHITECTURE Behavior OF mux2to IS WITH s SELECT < w WHEN, w WHEN OTHERS ; END Behavior ; Figure 6.27 VHDL code or a 2-to- multiplexer. Since it has the STD_LOGIC type, discussed in section 4.2, s can take the values,, Z,, and others. The keyword OTHERS provides a convenient way o accounting or all logic values that are not explicitly listed in a WHEN clause. A 4-to- multiplexer is described by the entity named mux4to, shown in Figure The two select inputs, which are called s and s in Figure 6.2, are represented by the two-bit STD_LOGIC_VECTOR signal s. The selected signal assignment sets to the value o one o the inputs w,...,, depending on the valuation o s. Compiling the code results in the circuit shown in Figure 6.2c. At the end o Figure 6.28, the mux4to entity is deined as a component in the package named mux4to_package. We showed in section that the component declaration allows the entity to be used as a subcircuit in other VHDL code. Example 6.2 Figure 6.4 showed how a 6-to- multiplexer is built using ive 4-to- multiplexers. Figure 6.29 presents VHDL code or this circuit, using the mux4to component. The lines o code are numbered so that we can easily reer to them. The mux4to_package is included in the code, because it provides the component declaration or mux4to. The data inputs to the mux6to entity are the 6-bit signal named w, and the select inputs are the our-bit signal named s. In the VHDL code signal names are needed or the outputs o the our 4-to- multiplexers on the let o Figure 6.4. Line deines a our-bit signal named m or this purpose, and lines 3 to 6 instantiate the our multiplexers. For instance, line 3 corresponds to the multiplexer at the top let o Figure 6.4. Its irst our ports, which correspond to w,..., in Figure 6.28, are driven by the signals w(),...,w(3). Example 6.3

28 May 9, 24 :4 vra6857_ch6 Sheet number 28 Page number 342 black 342 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY mux4to IS PORT ( w, w, w2, w3 : IN STD LOGIC ; s : IN STD LOGIC VECTOR( DOWNTO ) ; : OUT STD LOGIC ) ; END mux4to ; ARCHITECTURE Behavior OF mux4to IS WITH s SELECT < w WHEN, w WHEN, w2 WHEN, w3 WHEN OTHERS ; END Behavior ; LIBRARY ieee ; USE ieee.std logic 64.all ; PACKAGE mux4to package IS COMPONENT mux4to PORT ( w, w, w2, w3 : IN STD LOGIC ; s : IN STD LOGIC VECTOR( DOWNTO ) ; : OUT STD LOGIC ) ; END COMPONENT ; END mux4to package ; Figure 6.28 VHDL code or a 4-to- multiplexer. The syntax s( DOWNTO ) is used to attach the signals s() and s() to the two-bit s port o the mux4to component. The m() signal is connected to the multiplexer s output port. Line 7 instantiates the multiplexer on the right o Figure 6.4. The signals m,...,m 3 are connected to its data inputs, and bits s(3) and s(2), which are speciied by the syntax s(3 DOWNTO 2), are attached to the select inputs. The output port generates the mux6to output. Compiling the code results in the multiplexer unction = s 3 s 2 s s w + s 3 s 2 s s w + s 3 s 2 s s + +s 3 s 2 s s w 4 + s 3 s 2 s s w 5 Example 6.4 The selected signal assignments can also be used to describe other types o circuits. Figure 6.3 shows how a selected signal assignment can be used to describe the truth table or a 2-to-4 binary decoder. The entity is called dec2to4. The data inputs are the two-bit signal

29 May 9, 24 :4 vra6857_ch6 Sheet number 29 Page number 343 black 6.6 VHDL or Combinational Circuits 343 LIBRARY ieee ; 2 USE ieee.std logic 64.all ; 3 LIBRARY work ; 4 USE work.mux4to package.all ; 5 ENTITY mux6to IS 6 PORT ( w : IN STD LOGIC VECTOR( TO 5) ; 7 s : IN STD LOGIC VECTOR(3 DOWNTO ) ; 8 : OUT STD LOGIC ) ; 9 END mux6to ; ARCHITECTURE Structure OF mux6to IS SIGNAL m : STD LOGIC VECTOR( TO 3) ; 2 3 Mux: mux4to PORT MAP ( w(), w(), w(2), w(3), s( DOWNTO ), m() ) ; 4 Mux2: mux4to PORT MAP ( w(4), w(5), w(6), w(7), s( DOWNTO ), m() ) ; 5 Mux3: mux4to PORT MAP ( w(8), w(9), w(), w(), s( DOWNTO ), m(2) ) ; 6 Mux4: mux4to PORT MAP ( w(2), w(3), w(4), w(5), s( DOWNTO ), m(3) ) ; 7 Mux5: mux4to PORT MAP ( m(), m(), m(2), m(3), s(3 DOWNTO 2), ) ; 8 END Structure ; Figure 6.29 Hierarchical code or a 6-to- multiplexer. named w, and the enable input is En. The our outputs are represented by the our-bit signal y. In the truth table or the decoder in Figure 6.6a, the inputs are listed in the order En w w. To represent these three signals, the VHDL code deines the three-bit signal named Enw. The statement Enw <= En & w uses the VHDL concatenate operator, which was discussed in section 5.5.4, to combine the En and w signals into the Enw signal. Hence Enw(2) = En, Enw() = w, and Enw() = w. The Enw signal is used as the selection signal in the selected signal assignment statement. It describes the truth table in Figure 6.6a. In the irst our WHEN clauses, En =, and the decoder outputs have the same patterns as in the irst our rows o the truth table. The last WHEN clause uses the OTH- ERS keyword and sets the decoder outputs to, because it represents the cases where En =.

30 May 9, 24 :4 vra6857_ch6 Sheet number 3 Page number 344 black 344 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY dec2to4 IS PORT ( w : IN STD LOGIC VECTOR( DOWNTO ) ; En : IN STD LOGIC ; y : OUT STD LOGIC VECTOR( TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD LOGIC VECTOR(2 DOWNTO ) ; Enw < En & w ; WITH Enw SELECT y < WHEN, WHEN, WHEN, WHEN, WHEN OTHERS ; END Behavior ; Figure 6.3 VHDL code or a 2-to-4 binary decoder Conditional Signal Assignment Similar to the selected signal assignment, a conditional signal assignment allows a signal to be set to one o several values. Figure 6.3 shows a modiied version o the 2-to- multiplexer entity rom Figure It uses a conditional signal assignment to speciy that is assigned the value o w when s =, or else is assigned the value o w. Compiling LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY mux2to IS PORT ( w, w, s : IN STD LOGIC ; : OUT STD LOGIC ) ; END mux2to ; ARCHITECTURE Behavior OF mux2to IS < w WHEN s ELSE w ; END Behavior ; Figure 6.3 Speciication o a 2-to- multiplexer using a conditional signal assignment.

31 May 9, 24 :4 vra6857_ch6 Sheet number 3 Page number 345 black 6.6 VHDL or Combinational Circuits 345 the code generates the same circuit as the code in Figure In this small example the conditional signal assignment has only one WHEN clause. A more complex example, which better illustrates the eatures o the conditional signal assignment, is given in Example 6.5. Figure 6.24 gives the truth table or a 4-to-2 priority encoder. VHDL code that describes this truth table is shown in Figure The inputs to the encoder are represented by the our-bit signal named w. The encoder has the outputs y, which is a two-bit signal, and z. The conditional signal assignment speciies that y is assigned the value when input w(3) =. I this condition is true, then the other WHEN clauses that ollow the ELSE keyword do not aect the value o. Hence the values o w(2), w(), and w() do not matter, which implements the desired priority scheme. The second WHEN clause states that when w(2) =, then y is assigned the value. This can occur only i w(3) =. Each successive WHEN clause can aect y only i none o the conditions associated with the preceding WHEN clauses are true. Figure 6.32 includes a second conditional signal assignment or the output z. It states that when all our inputs are, z is assigned the value ; else z is assigned the value. The priority level associated with each WHEN clause in the conditional signal assignment is a key dierence rom the selected signal assignment, which has no such priority scheme. It is possible to describe the priority encoder using a selected signal assignment, but the code is more awkward. One possibility is shown by the architecture in Figure The irst WHEN clause sets y to when w is the only input that is. The next two clauses state that y should be when = = and w =. The next our clauses speciy that y should be i = and =. Finally, the last WHEN clause states that y should be or all other input valuations, which includes all valuations or which is. Note that Example 6.5 LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY priority IS PORT ( w : IN STD LOGIC VECTOR(3 DOWNTO ) ; y : OUT STD LOGIC VECTOR( DOWNTO ) ; z : OUT STD LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS y < WHEN w(3) ELSE WHEN w(2) ELSE WHEN w() ELSE ; z < WHEN w ELSE ; END Behavior ; Figure 6.32 VHDL code or a priority encoder.

32 May 9, 24 :4 vra6857_ch6 Sheet number 32 Page number 346 black 346 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY priority IS PORT ( w : IN STD LOGIC VECTOR(3 DOWNTO ) ; y : OUT STD LOGIC VECTOR( DOWNTO ) ; z : OUT STD LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS WITH w SELECT y < WHEN, WHEN, WHEN, WHEN, WHEN, WHEN, WHEN, WHEN OTHERS ; WITH w SELECT z < WHEN, WHEN OTHERS ; END Behavior ; Figure 6.33 Less eicient code or a priority encoder. the OTHERS clause includes the input valuation. This pattern results in z =, and the value o y does not matter in this case. Example 6.6 We derived the circuit or a comparator in Figure Figure 6.34 shows how this circuit can be described with VHDL code. Each o the three conditional signal assignments determines the value o one o the comparator outputs. The package named std_logic_unsigned is included in the code because it speciies that STD_LOGIC_VECTOR signals, namely, A and B, can be used as unsigned binary numbers with VHDL relational operators. The relational operators provide a convenient way o speciying the desired unctionality. The circuit generated rom the code in Figure 6.34 is similar, but not identical, to the circuit in Figure The VHDL compiler instantiates a predeined module to implement each o the comparison operations. In Quartus II the modules that are instantiated are rom the LPM library, which was introduced in section 5.5.

33 May 9, 24 :4 vra6857_ch6 Sheet number 33 Page number 347 black 6.6 VHDL or Combinational Circuits 347 LIBRARY ieee ; USE ieee.std logic 64.all ; USE ieee.std logic unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD LOGIC VECTOR(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS AeqB < WHEN A B ELSE ; AgtB < WHEN A > B ELSE ; AltB < WHEN A < B ELSE ; END Behavior ; Figure 6.34 VHDL code or a our-bit comparator. Instead o using the std_logic_unsigned library, another way to speciy that the generated circuit should use unsigned numbers is to include the library named std_logic_arith. In this case the signals A and B should be deined with the type UNSIGNED, rather than STD_LOGIC_VECTOR. I we want the circuit to work with signed numbers, signals A and B should be deined with the type SIGNED. This code is given in Figure LIBRARY ieee ; USE ieee.std logic 64.all ; USE ieee.std logic arith.all ; ENTITY compare IS PORT ( A, B : IN SIGNED(3 DOWNTO ) ; AeqB, AgtB, AltB : OUT STD LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS AeqB < WHEN A B ELSE ; AgtB < WHEN A > B ELSE ; AltB < WHEN A < B ELSE ; END Behavior ; Figure 6.35 The code rom Figure 6.34 or signed numbers.

34 May 9, 24 :4 vra6857_ch6 Sheet number 34 Page number 348 black 348 CHAPTER 6 Combinational-Circuit Building Blocks Generate Statements Figure 6.29 gives VHDL code or a 6-to- multiplexer using ive instances o a 4-to- multiplexer subcircuit. The regular structure o the code suggests that it could be written in a more compact orm using a loop. VHDL provides a eature called the FOR GENERATE statement or describing regularly structured hierarchical code. Figure 6.36 shows the code rom Figure 6.29 rewritten using a FOR GENERATE statement. The generate statement must have a label, so we have used the label G in the code. The loop instantiates our copies o the mux4to component, using the loop index i in the range rom to 3. The variable i is not explicitly declared in the code; it is automatically deined as a local variable whose scope is limited to the FOR GENERATE statement. The irst loop iteration corresponds to the instantiation statement labeled Mux in Figure The * operator represents multiplication; hence or the irst loop iteration the VHDL compiler translates the signal names w(4 i), w(4 i + ), w(4 i + 2), and w(4 i + 3) into signal names w(), w(), w(2), and w(3). The loop iterations or i =, i = 2, and i = 3 correspond to the statements labeled Mux2, Mux3, and Mux4 in Figure The statement labeled Mux5 in Figure 6.29 does not it within the loop, so it is included as a separate statement in Figure The circuit generated rom the code in Figure 6.36 is identical to the circuit produced by using the code in Figure LIBRARY ieee ; USE ieee.std logic 64.all ; USE work.mux4to package.all ; ENTITY mux6to IS PORT ( w : IN STD LOGIC VECTOR( TO 5) ; s : IN STD LOGIC VECTOR(3 DOWNTO ) ; : OUT STD LOGIC ) ; END mux6to ; ARCHITECTURE Structure OF mux6to IS SIGNAL m : STD LOGIC VECTOR( TO 3) ; G: FOR i IN TO 3 GENERATE Muxes: mux4to PORT MAP ( w(4*i), w(4*i+), w(4*i+2), w(4*i+3), s( DOWNTO ), m(i) ) ; END GENERATE ; Mux5: mux4to PORT MAP ( m(), m(), m(2), m(3), s(3 DOWNTO 2), ) ; END Structure ; Figure 6.36 Code or a 6-to- multiplexer using a generate statement.

35 May 9, 24 :4 vra6857_ch6 Sheet number 35 Page number 349 black 6.6 VHDL or Combinational Circuits 349 In addition to the FOR GENERATE statement, VHDL provides another type o generate statement called IF GENERATE. Figure 6.37 illustrates the use o both types o generate statements. The code shown is a hierarchical description o the 4-to-6 decoder given in Figure 6.8, using ive instances o the dec2to4 component deined in Figure 6.3. The decoder inputs are the our-bit signal w, the enable is En, and the outputs are the 6-bit signal y. Following the component declaration or the dec2to4 subcircuit, the architecture deines the signal m, which represents the outputs o the 2-to-4 decoder on the let o Figure 6.8. The ive copies o the dec2to4 component are instantiated by the FOR GENERATE statement. In each iteration o the loop, the statement labeled Dec_ri instantiates a dec2to4 component that corresponds to one o the 2-to-4 decoders on the right side o Figure 6.8. The irst loop iteration generates the dec2to4 component with data inputs w and w, enable input m, and outputs y, y, y 2, y 3. The other loop iterations also use data inputs w w, but use dierent bits o m and y. The IF GENERATE statement, labeled G2, instantiates a dec2to4 component in the last loop iteration, or which the condition i = 3 is true. This component represents the 2-to-4 decoder on the let o Figure 6.8. It has the two-bit data inputs and, the enable En, and Example 6.7 LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY dec4to6 IS PORT ( w : IN STD LOGIC VECTOR(3 DOWNTO ) ; En : IN STD LOGIC ; y : OUT STD LOGIC VECTOR( TO 5) ) ; END dec4to6 ; ARCHITECTURE Structure OF dec4to6 IS COMPONENT dec2to4 PORT ( w : IN STD LOGIC VECTOR( DOWNTO ) ; En : IN STD LOGIC ; y : OUT STD LOGIC VECTOR( TO 3) ) ; END COMPONENT ; SIGNAL m : STD LOGIC VECTOR( TO 3) ; G: FOR i IN TO 3 GENERATE Dec ri: dec2to4 PORT MAP ( w( DOWNTO ), m(i), y(4*i TO 4*i+3) ); G2: IF i=3 GENERATE Dec let: dec2to4 PORT MAP ( w(i DOWNTO i-), En, m ) ; END GENERATE ; END GENERATE ; END Structure ; Figure 6.37 Hierarchical code or a 4-to-6 binary decoder.

36 May 9, 24 :4 vra6857_ch6 Sheet number 36 Page number 35 black 35 CHAPTER 6 Combinational-Circuit Building Blocks the outputs m, m, m 2, and m 3. Note that instead o using the IF GENERATE statement, we could have instantiated this component outside the FOR GENERATE statement. We have written the code as shown simply to give an example o the IF GENERATE statement. The generate statements in Figures 6.36 and 6.37 are used to instantiate components. Another use o generate statements is to generate a set o logic equations. An example o this use will be given in Figure Concurrent and Sequential Assignment Statements We have introduced several types o assignment statements: simple assignment statements, which involve logic or arithmetic expressions, selected assignment statements, and conditional assignment statements. All o these statements share the property that the order in which they appear in VHDL code does not aect the meaning o the code. Because o this property, these statements are called the concurrent assignment statements. VHDL also provides a second category o statements, called sequential assignment statements, or which the ordering o the statements may aect the meaning o the code. We will discuss two types o sequential assignment statements, called i-then-else statements and case statements. VHDL requires that the sequential assignment statements be placed inside another type o statement, called a process statement Process Statement Figures 6.27 and 6.3 show two ways o describing a 2-to- multiplexer, using the selected and conditional signal assignments. The same circuit can also be described using an i-thenelse statement, but this statement must be placed inside a process statement. Figure 6.38 shows such code. The process statement, or simply process, begins with the PROCESS keyword, ollowed by a parenthesized list o signals, called the sensitivity list. For a combinational circuit like the multiplexer, the sensitivity list includes all input signals that are used inside the process. The process statement is translated by the VHDL compiler into logic equations. In the igure the process consists o the single i-then-else statement that describes the multiplexer unction. Thus the sensitivity list comprises the data inputs, w and w, and the select input s. In general, there can be a number o statements inside a process. These statements are considered as ollows. Using VHDL jargon, we say that when there is a change in the value o any signal in the process s sensitivity list, then the process becomes active. Once active, the statements inside the process are evaluated in sequential order. Any assignments made to signals inside the process are not visible outside the process until all o the statements in the process have been evaluated. I there are multiple assignments to the same signal, only the last one has any visible eect. This is illustrated in Example 6.8.

37 May 9, 24 :4 vra6857_ch6 Sheet number 37 Page number 35 black 6.6 VHDL or Combinational Circuits 35 LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY mux2to IS PORT ( w, w, s : IN STD LOGIC ; : OUT STD LOGIC ) ; END mux2to ; ARCHITECTURE Behavior OF mux2to IS PROCESS ( w, w, s ) IF s THEN < w ; ELSE < w ; END IF ; END PROCESS ; END Behavior ; Figure 6.38 A 2-to- multiplexer speciied using the i-then-else statement. The code in Figure 6.39 is equivalent to the code in Figure The irst statement in the process assigns the value o w to. This provides a deault value or but the assignment does not actually take place until the end o the process. In VHDL jargon we say that the assignment is scheduled to occur ater all o the statements in the process have been evaluated. I another assignment to takes place while the process is active, the deault assignment will be overridden. The second statement in the process assigns the value o w to i the value o s is equal to. I this condition is true, then the deault assignment is overridden. Thus i s =, then = w, and i s =, then = w, which deines the 2-to- multiplexer. Compiling this code results in the same circuit as or Figures 6.27, 6.3, and 6.38, namely, = sw + sw. The process statement in Figure 6.39 illustrates that the ordering o the statements in a process can aect the meaning o the code. Consider reversing the order o the two statements so that the i-then-else statement is evaluated irst. I s =, is assigned the value o w. This assignment is scheduled and does not take place until the end o the process. However, the statement <= w is evaluated last. It overrides the irst assignment, and is assigned the value o w regardless o the value o s. Hence instead o describing a multiplexer, when the statements inside the process are reversed, the code represents the trivial circuit = w. Example 6.8

38 May 9, 24 :4 vra6857_ch6 Sheet number 38 Page number 352 black 352 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY mux2to IS PORT ( w, w, s : IN STD LOGIC ; : OUT STD LOGIC ) ; END mux2to ; ARCHITECTURE Behavior OF mux2to IS PROCESS ( w, w, s ) < w ; IF s THEN < w ; END IF ; END PROCESS ; END Behavior ; Figure 6.39 Alternative code or the 2-to- multiplexer using an i-then-else statement. Example 6.9 Figure 6.4 gives an example that contains both a concurrent assignment statement and a process statement. It describes a priority encoder and is equivalent to the code in Figure The process describes the desired priority scheme using an i-then-else statement. It speciies that i the input is, then the output is set to y =. This assignment does not depend on the values o inputs, w,orw ; hence their values do not matter. The other clauses in the i-then-else statement are evaluated only i =. The irst ELSIF clause states that i is, then y =. I =, then the next ELSIF clause results in y = i w =. I = = w =, then the ELSE clause results in y =. This assignment is done whether or not w is ; Figure 6.24 indicates that y can be set to any pattern when w = because z will be set to in this case. The priority encoder s output z must be set to whenever at least one o the data inputs is. This output is deined by the conditional assignment statement at the end o Figure 6.4. The VHDL syntax does not allow a conditional assignment statement (or a selected assignment statement) to appear inside a process. An alternative would be to speciy the value o z by using an i-then-else statement inside the process. The reason that we have written the code as given in the igure is to illustrate that concurrent assignment statements can be used in conjunction with process statements. The process statement serves the purpose o separating the sequential statements rom the concurrent statements. Note that the ordering o the process statement and the conditional assignment statement does not matter. VHDL stipulates that while the statements inside a process are sequential statements, the process statement itsel is a concurrent statement.

39 May 9, 24 :4 vra6857_ch6 Sheet number 39 Page number 353 black 6.6 VHDL or Combinational Circuits 353 LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY priority IS PORT ( w : IN STD LOGIC VECTOR(3 DOWNTO ) ; y : OUT STD LOGIC VECTOR( DOWNTO ) ; z : OUT STD LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS PROCESS ( w ) IF w(3) THEN y < ; ELSIF w(2) THEN y < ; ELSIF w() THEN y < ; ELSE y < ; END IF ; END PROCESS ; z < WHEN w ELSE ; END Behavior ; Figure 6.4 A priority encoder speciied using the i-then-else statement. Figure 6.4 shows an alternative style o code or the priority encoder, using i-then-else statements. The irst statement in the process provides the deault value o or y y. The second statement overrides this i w is, and sets y y to. Similarly, the third and ourth statements override the previous ones i or are, and set y y to and, respectively. These our statements are equivalent to the single i-then-else statement in Figure 6.4 that describes the priority scheme. The value o z is speciied using a deault assignment statement, ollowed by an i-then-else statement that overrides the deault i w =. Although the examples in Figures 6.4 and 6.4 are equivalent, the meaning o the code in Figure 6.4 is probably easier to understand. Example 6.2 Figure 6.34 speciies a our-bit comparator that produces the three outputs AeqB, AgtB, and AltB. Figure 6.42 shows how such speciication can be written using i-then-else statements. For simplicity, one-bit numbers are used or the inputs A and B, and only the code or the Example 6.2

40 May 9, 24 :4 vra6857_ch6 Sheet number 4 Page number 354 black 354 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY priority IS PORT ( w : IN STD LOGIC VECTOR(3 DOWNTO ) ; y : OUT STD LOGIC VECTOR( DOWNTO ) ; z : OUT STD LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS PROCESS ( w ) y < ; IF w() THEN y < ; END IF ; IF w(2) THEN y < ; END IF ; IF w(3) THEN y < ; END IF ; z < ; IF w THEN z < ; END IF ; END PROCESS ; END Behavior ; Figure 6.4 Alternative code or the priority encoder. LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY compare IS PORT ( A, B : IN STD LOGIC ; AeqB : OUT STD LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS PROCESS ( A, B ) AeqB < ; IF A B THEN AeqB < ; END IF ; END PROCESS ; END Behavior ; Figure 6.42 Code or a one-bit equality comparator.

41 May 9, 24 :4 vra6857_ch6 Sheet number 4 Page number 355 black 6.6 VHDL or Combinational Circuits 355 LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY implied IS PORT ( A, B : IN STD LOGIC ; AeqB : OUT STD LOGIC ) ; END implied ; ARCHITECTURE Behavior OF implied IS PROCESS ( A, B ) IF A B THEN AeqB < ; END IF ; END PROCESS ; END Behavior ; Figure 6.43 An example o code that results in implied memory. AeqB output is shown. The process assigns the deault value o to AeqB and then the i-then-else statement changes AeqB to ia and B are equal. It is instructive to consider the eect on the semantics o the code i the deault assignment statement is removed, as illustrated in Figure With only the i-then-else statement, the code does not speciy what value AeqB should have i the condition A = B is not true. The VHDL semantics stipulate that in cases where the code does not speciy the value o a signal, the signal should retain its current value. For the code in Figure 6.43, once A and B are equal, resulting in AeqB =, then AeqB will remain set to indeinitely, even i A and B are no longer equal. In the VHDL jargon, the AeqB output is said to have implied memory because the circuit synthesized rom the code will remember, or store the value AeqB =. Figure 6.44 shows the circuit synthesized rom the code. The XOR gate produces a when A and B are equal, and the OR gate ensures that AeqB remains set to indeinitely. The implied memory that results rom the code in Figure 6.43 is not useul, because it generates a comparator circuit that does not unction correctly. However, we will show A B AeqB Figure 6.44 The circuit generated rom the code in Figure 6.43.

42 May 9, 24 :4 vra6857_ch6 Sheet number 42 Page number 356 black 356 CHAPTER 6 Combinational-Circuit Building Blocks in Chapter 7 that the semantics o implied memory are useul or other types o circuits, which have the capability to store logic signal values in memory elements Case Statement A case statement is similar to a selected signal assignment in that the case statement has a selection signal and includes WHEN clauses or various valuations o this selection signal. Figure 6.45 shows how the case statement can be used as yet another way o describing the 2-to- multiplexer circuit. The case statement begins with the CASE keyword, which speciies that s is to be used as the selection signal. The irst WHEN clause speciies, ollowing the => symbol, the statements that should be evaluated when s =. In this example the only statement evaluated when s = is <= w. The case statement must include a WHEN clause or all possible valuations o the selection signal. Hence the second WHEN clause, which contains <= w, uses the OTHERS keyword. Example 6.22 Figure 6.3 gives the code or a 2-to-4 decoder. A dierent way o describing this circuit, using sequential assignment statements, is shown in Figure The process irst uses an i-then-else statement to check the value o the decoder enable signal En. IEn =, the LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY mux2to IS PORT ( w, w, s : IN STD LOGIC ; : OUT STD LOGIC ) ; END mux2to ; ARCHITECTURE Behavior OF mux2to IS PROCESS ( w, w, s ) CASE s IS WHEN > < w ; WHEN OTHERS > < w ; END CASE ; END PROCESS ; END Behavior ; Figure 6.45 A case statement that represents a 2-to- multiplexer.

43 May 9, 24 :4 vra6857_ch6 Sheet number 43 Page number 357 black 6.6 VHDL or Combinational Circuits 357 LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY dec2to4 IS PORT ( w : IN STD LOGIC VECTOR( DOWNTO ) ; En : IN STD LOGIC ; y : OUT STD LOGIC VECTOR( TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS PROCESS ( w, En ) IF En THEN CASE w IS WHEN > y < ; WHEN > y < ; WHEN > y < ; WHEN OTHERS > y < ; END CASE ; ELSE y < ; END IF ; END PROCESS ; END Behavior ; Figure 6.46 A process statement that describes a 2-to-4 binary decoder. case statement sets the output y to the appropriate value based on the input w. The case statement represents the irst our rows o the truth table in Figure 6.6a. I En =, the ELSE clause sets y to, as speciied in the bottom row o the truth table. Another example o a case statement is given in Figure The entity is named seg7, and it represents the BCD-to-7-segment decoder in Figure The BCD input is represented by the our-bit signal named bcd, and the seven outputs are the seven-bit signal named leds. The case statement is ormatted so that it resembles the truth table in Figure 6.25c. Note that there is a comment to the right o the case statement, which labels the seven outputs Example 6.23

44 May 9, 24 :4 vra6857_ch6 Sheet number 44 Page number 358 black 358 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY seg7 IS PORT ( bcd : IN STD LOGIC VECTOR(3 DOWNTO ) ; leds : OUT STD LOGIC VECTOR( TO 7) ) ; END seg7 ; ARCHITECTURE Behavior OF seg7 IS PROCESS ( bcd ) CASE bcd IS - - abcde g WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN > leds < ; > leds < ; > leds < ; > leds < ; > leds < ; > leds < ; > leds < ; > leds < ; > leds < ; > leds < ; END CASE ; END PROCESS ; END Behavior ; WHEN OTHERS > leds < ; Figure 6.47 Code that represents a BCD-to-7-segment decoder. with the letters rom a to g. These labels indicate to the reader the correlation between the seven-bit leds signal in the VHDL code and the seven segments in Figure 6.25b. The inal WHEN clause in the case statement sets all seven bits o leds to. Recall that is used in VHDL to denote a don t-care condition. This clause represents the don t-care conditions discussed or Figure 6.25, which are the cases where the bcd input does not represent a valid BCD digit. Example 6.24 An arithmetic logic unit (ALU) is a logic circuit that perorms various Boolean and arithmetic operations on n-bit operands. In section 3.5 we discussed a amily o standard chips called the 74-series chips. We said that some o these chips contain basic logic gates, and others provide commonly used logic circuits. One example o an ALU is the standard chip called the Table 6. speciies the unctionality o this chip. It has 2 our-bit data inputs, named A and B; a three-bit select input s; and a our-bit output F. As the table shows,

45 May 9, 24 :4 vra6857_ch6 Sheet number 45 Page number 359 black 6.6 VHDL or Combinational Circuits 359 Table 6. The unctionality o the 7438 ALU. Inputs Outputs Operation s 2 s s F Clear B A B A A B A B ADD A + B XOR A XOR B OR A OR B AND A AND B Preset F is deined by various arithmetic or Boolean operations on the inputs A and B. In this table + means arithmetic addition, and means arithmetic subtraction. To avoid conusion, the table uses the words XOR, OR, and AND or the Boolean operations. Each Boolean operation is done in a bit-wise ashion. For example, F = A AND B produces the our-bit result = a b, = a b, 2 = a 2 b 2, and 3 = a 3 b 3. Figure 6.48 shows how the unctionality o the 7438 ALU can be described using VHDL code. The std_logic_unsigned package, introduced in section 5.5.4, is included so that the STD_LOGIC_VECTOR signals A and B can be used in unsigned arithmetic operations. The case statement shown corresponds directly to Table 6.. To check the unctionality o the code, we synthesized a circuit or implementation in a CPLD. An example o a timing simulation is illustrated in Figure For each valuation o s, the circuit generates the appropriate Boolean or arithmetic operation VHDL Operators In this section we discuss the VHDL operators that are useul or synthesizing logic circuits. Table 6.2 lists these operators in groups that relect the type o operation perormed. To illustrate the results produced by the various operators, we will use three-bit vectors A(2 DOWNTO ), B(2 DOWNTO ), and C(2 DOWNTO ). Logical Operators The logical operators can be used with bit and boolean types o operands. The operands can be either single-bit scalars or multibit vectors. For example, the statement C <= NOT A;

46 May 9, 24 :4 vra6857_ch6 Sheet number 46 Page number 36 black 36 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; USE ieee.std logic unsigned.all ; ENTITY alu IS PORT ( s : IN STD LOGIC VECTOR(2 DOWNTO ) ; A, B : IN STD LOGIC VECTOR(3 DOWNTO ) ; F : OUT STD LOGIC VECTOR(3 DOWNTO ) ) ; END alu ; ARCHITECTURE Behavior OF alu IS PROCESS ( s, A, B ) CASE s IS WHEN > F < ; WHEN > F < B A ; WHEN > F < A B ; WHEN > F < A + B ; WHEN > F < A XOR B ; WHEN > F < AORB; WHEN > F < AANDB; WHEN OTHERS > F < ; END CASE ; END PROCESS ; END Behavior ; Figure 6.48 Code that represents the unctionality o the 7438 ALU chip. produces the result c 2 = a 2, c = a, and c = a, where a i and c i are the bits o the vectors A and C. The statement C <= A AND B; generates c 2 = a 2 b 2, c = a b, and c = a b. The other operators lead to similar evaluations.

47 May 9, 24 :4 vra6857_ch6 Sheet number 47 Page number 36 black 6.6 VHDL or Combinational Circuits 36 Figure 6.49 Timing simulation or the code in Figure Table 6.2 VHDL operators (used or synthesis). Operator category Operator symbol Operation perormed Logical AND AND OR OR NAND Not AND NOR Not OR XOR XOR XNOR Not XOR NOT NOT Relational = Equality /= Inequality > Greater than < Less than >= Greater than or equal to <= Less than or equal to Arithmetic + Addition Subtraction Multiplication / Division Concatenation & Concatenation Shit and Rotate SLL Shit let logical SRL Shit right logical SLA Shit let arithmetic SRA Shit right arithmetic ROL Rotate let ROR Rotate right Relational Operators The relational operators are used to compare expressions. The result o the comparison is TRUE or FALSE. The expressions that are compared must be o the same type. For example, i A = and B = then A > B evaluates to TRUE, and B /= evaluates to FALSE.

48 May 9, 24 :4 vra6857_ch6 Sheet number 48 Page number 362 black 362 CHAPTER 6 Combinational-Circuit Building Blocks Arithmetic Operators We have already encountered the arithmetic operators in Chapter 5. They perorm standard arithmetic operations. Thus C <= A + B; puts the three-bit sum o A plus B into C, while C <= A B; puts the dierence o A and B into C. The operation C <= A; places the 2 s complement o A into C. The addition, subtraction, and multiplication operations are supported by most CAD synthesis tools. However, the division operation is oten not supported. When the VHDL compiler encounters an arithmetic operator, it usually synthesizes it by using an appropriate module rom a library. Concatenate Operator This operator concatenates two or more vectors to create a larger vector. For example, D <= A&B; deines the six-bit vector D = a 2 a a b 2 b b. Similarly, the concatenation E <= & A & ; produces the eight-bit vector E = a 2 a a. Shit and Rotate Operators A vector operand can be shited to the right or let by a number o bits speciied as a constant. When bits are shited, the vacant bit positions are illed with s. For example, B <= A SLL ; results in b 2 = a, b = a, and b =. Similarly, B <= A SRL 2; yields b 2 = b = and b = a 2. The arithmetic shit let, SLA, has the same eect as SLL. But, the arithmetic shit right, SRA, perorms the sign extension by replicating the sign bit into the positions let vacant ater shiting. Hence B <= A SRA ; gives b 2 = a 2, b = a 2, and b = a. An operand can also be rotated, in which case the bits shited out rom one end are placed into the vacated positions at the other end. For example, B <= A ROR 2; produces b 2 = a, b = a, and b = a 2.

49 May 9, 24 :4 vra6857_ch6 Sheet number 49 Page number 363 black 6.7 Concluding Remarks 363 Operator Precedence Operators in dierent categories have dierent precedence. Operators in the same category have the same precedence, and are evaluated rom let to right in a given expression. It is a good practice to use parentheses to indicate the desired order o operations in the expression. To illustrate this point, consider the statement S <= A + B + C + D; which deines the addition o our vector operands. The VHDL compiler will synthesize a circuit as i the expression was written in the orm ((A + B) + C) + D, which gives a cascade o three adders so that the inal sum will be available ater a propagation delay through three adders. By writing the statement as S <= (A + B) + (C + D); the synthesized circuit will still have three adders, but since the sums A + B and C + D are generated in parallel, the inal sum will be available ater a propagation delay through only two adders. Table 6.2 groups the operators inormally according to their unctionality. It shows only those operators that are used to synthesize logic circuits. The VHDL Standard speciies additional operators, which are useul or simulation and documentation purposes. All operators are grouped into dierent classes, with a deined precedence ordering between classes. We discuss this issue in Appendix A, section A Concluding Remarks This chapter has introduced a number o circuit building blocks. Examples using these blocks to construct larger circuits will be presented in Chapters 7 and. To describe the building block circuits eiciently, several VHDL constructs have been introduced. In many cases a given circuit can be described in various ways, using dierent constructs. A circuit that can be described using a selected signal assignment can also be described using a case statement. Circuits that it well with conditional signal assignments are also well-suited to i-then-else statements. In general, there are no clear rules that dictate when one type o assignment statement should be preerred over another. With experience the user develops a sense or which types o statements work well in a particular design situation. Personal preerence also inluences how the code is written. VHDL is not a programming language, and VHDL code should not be written as i it were a computer program. The concurrent and sequential assignment statements discussed in this chapter can be used to create large, complex circuits. A good way to design such circuits is to construct them using well-deined modules, in the manner that we illustrated or the multiplexers, decoders, encoders, and so on. Additional examples using the VHDL statements introduced in this chapter are given in Chapters 7 and 8. In Chapter we provide a number o examples o using VHDL code to describe larger digital systems. For more inormation on VHDL, the reader can consult more specialized books [5 ]. In the next chapter we introduce logic circuits that include the ability to store logic signal values in memory elements.

50 May 9, 24 :4 vra6857_ch6 Sheet number 5 Page number 364 black 364 CHAPTER 6 Combinational-Circuit Building Blocks 6.8 Examples o Solved Problems This section presents some typical problems that the reader may encounter, and shows how such problems can be solved. Example 6.25 Problem: Implement the unction (w,, ) = m(,, 3, 4, 6, 7) by using a 3-to-8 binary decoder and an OR gate. Solution: The decoder generates a separate output or each minterm o the required unction. These outputs are then combined in the OR gate, giving the circuit in Figure 6.5. Example 6.26 Problem: Derive a circuit that implements an 8-to-3 binary encoder. Solution: The truth table or the encoder is shown in Figure 6.5. Only those rows or which a single input variable is equal to are shown; the other rows can be treated as don t care cases. From the truth table it is seen that the desired circuit is deined by the equations y 2 = w 4 + w 5 + w 6 + w 7 y = + + w 6 + w 7 y = w + + w 5 + w 7 Example 6.27 Problem: Implement the unction (w,,, w 4 ) = w w 4 w 5 + w + w + w w 4 + w 4 w 5 by using a 4-to- multiplexer and as ew other gates as possible. Assume that only the uncomplemented inputs w,,, and w 4 are available. w y w y w y 2 y 3 y 4 y 5 En y 6 y 7 Figure 6.5 Circuit or Example 6.25.

51 May 9, 24 :4 vra6857_ch6 Sheet number 5 Page number 365 black 6.8 Examples o Solved Problems 365 w 7 w 6 w 5 w 4 w w y 2 y y Figure 6.5 Truth table or an 8-to-3 binary encoder. Solution: Since variables w and w 4 appear in more product terms in the expression or than the other three variables, let us perorm Shannon s expansion with respect to these two variables. The expansion gives = w w 4 w w 4 + w w 4 w w 4 + w w 4 w w 4 + w w 4 w w 4 = w w 4 ( w 5 ) + w w 4 ( w 5 ) + w w 4 ( + ) + w () We can use a NOR gate to implement w 5 = + w 5. We also need an AND gate and an OR gate. The complete circuit is presented in Figure w w 4 w 5 w 5 w 5 + Figure 6.52 Circuit or Example 6.27.

52 May 9, 24 :4 vra6857_ch6 Sheet number 52 Page number 366 black 366 CHAPTER 6 Combinational-Circuit Building Blocks b 2 b b g 2 g g Figure 6.53 Binary to Gray code coversion. Example 6.28 Problem: In Chapter 4 we pointed out that the rows and columns o a Karnaugh map are labeled using Gray code. This is a code in which consecutive valuations dier in one variable only. Figure 6.53 depicts the conversion between three-bit binary and Gray codes. Design a circuit that can convert a binary code into a Gray according the igure. Solution: From the igure it ollows that g 2 = b 2 g = b b 2 + b b 2 = b b 2 g = b b + b b = b b Example 6.29 Problem: In section 6..2 we showed that any logic unction can be decomposed using Shannon s expansion theorem. For a our-variable unction, (w,...,w 4 ), the expansion with respect to w is (w,...,w 4 ) = w w + w w A circuit that implements this expression is given in Figure 6.54a. (a) I the decomposition yields w =, then the multiplexer in the igure can be replaced by a single logic gate. Show this circuit. (b) Repeat part (a) or the case where w =. Solution: The desired circuits are shown in parts (b) and (c) o Figure Example 6.3 Problem: In several commercial FPGAs the logic blocks are 4-LUTs. What is the minimum number o 4-LUTs needed to construct a 4-to- multiplexer with select inputs s and s and data inputs,, w, and w?

53 May 9, 24 :4 vra6857_ch6 Sheet number 53 Page number 367 black 6.8 Examples o Solved Problems 367 w w w 4 w (a) Shannon s expansion o the unction. w w w 4 (b) Solution or part a w w w 4 (c) Solution or part b Figure 6.54 Circuits or Example Solution: A straightorward attempt is to use directly the expression that deines the 4-to- multiplexer = s s w + s s w + s s + s s Let g = s s w + s s w and h = s s + s s, so that = g + h. This decomposition leads to the circuit in Figure 6.55a, which requires three LUTs. When designing logic circuits, one can sometimes come up with a clever idea which leads to a superior implementation. Figure 6.55b shows how it is possible to implement the multiplexer with just two LUTs, based on the ollowing observation. The truth table in Figure 6.2b indicates that when s = the output must be either w or w, as determined by the value o s. This can be generated by the irst LUT. The second LUT must make the choice between and when s =. But, the choice can be made only by knowing the value o s. Since it is impossible to have ive inputs in the LUT, more inormation has to

54 May 9, 24 :4 vra6857_ch6 Sheet number 54 Page number 368 black 368 CHAPTER 6 Combinational-Circuit Building Blocks s s w LUT g w LUT LUT h (a) Using three LUTs s s w w LUT k LUT (b) Using two LUTs Figure 6.55 Circuits or Example 6.3. be passed rom the irst to the second LUT. Observe that when s = the output will be equal to either or, in which case it is not necessary to know the values o w and w. Hence, in this case we can pass on the value o s through the irst LUT, rather than w or w. This can be done by making the unction o this LUT Then, the second LUT perorms the unction k = s s w + s s w + s s = s k + s k + s kw 4 Example 6.3 Problem: In digital systems it is oten necessary to have circuits that can shit the bits o a vector by one or more bit positions to the let or right. Design a circuit that can shit a

55 May 9, 24 :4 vra6857_ch6 Sheet number 55 Page number 369 black 6.8 Examples o Solved Problems 369 w w Shit y 3 y 2 y y k Figure 6.56 A shiter circuit. our-bit vector W = w w one bit position to the right when a control signal Shit is equal to. Let the outputs o the circuit be a our-bit vector Y = y 3 y 2 y y and a signal k, such that i Shit = then y 3 =, y 2 =, y =, y = w, and k = w.ishit = then Y = W and k =. Solution: The required circuit can be implemented with ive 2-to- multiplexers as shown in Figure The Shit signal is used as the select input to each multiplexer. Problem: The shiter circuit in Example 6.3 shits the bits o an input vector by one bit position to the right. It ills the vacated bit on the let side with. A more versatile shiter circuit may be able to shit by more bit positions at a time. I the bits that are shited out are placed into the vacated positions on the let, then the circuit eectively rotates the bits o the input vector by a speciied number o bit positions. Such a circuit is oten called a barrel shiter. Design a our-bit barrel shiter that rotates the bits by,, 2, or 3 bit positions as determined by the valuation o two control signals s and s. Solution: The required action is given in Figure 6.57a. The barrel shiter can be implemented with our 4-to- multiplexers as shown in Figure 6.57b. The control signals s and s are used as the select inputs to the multiplexers. Example 6.32 Problem: Write VHDL code that represents the circuit in Figure 6.9. Use the dec2to4 entity in Figure 6.3 as a subcircuit in your code. Solution: The code is shown in Figure Note that the dec2to4 entity can be included in the same ile as we have done in the igure, but it can also be in a separate ile in the project directory. Example 6.33

56 May 9, 24 :4 vra6857_ch6 Sheet number 56 Page number 37 black 37 CHAPTER 6 Combinational-Circuit Building Blocks s s y 3 y 2 y y w w w w w w w w (a) Truth table w w s s y 3 y 2 y y (b) Circuit Figure 6.57 A barrel shiter circuit. Example 6.34 Problem: Write VHDL code that represents the shiter circuit in Figure Solution: There are two possible approaches: structural and behavioral. A structural description is given in Figure The IF construct is used to deine the desired shiting o individual bits. A typical VHDL compiler will implement this code with 2-to- multiplexers as depicted in Figure A behavioral speciication is given in Figure 6.6. It makes use o the shit operator SRL. Since the shit and rotate operators are supported in the ieee.numeric_std.all library, this library must be included in the code. Note that the vectors w and y are deined to be o UNSIGNED type. Example 6.35 Problem: Write VHDL code that deines the barrel shiter in Figure Solution: The easiest way to speciy the barrel shiter is by using the VHDL rotate operator. The complete code is presented in Figure 6.6.

57 May 9, 24 :4 vra6857_ch6 Sheet number 57 Page number 37 black 6.8 Examples o Solved Problems 37 LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY mux4to IS PORT ( s : IN STD LOGIC VECTOR( DOWNTO ) ; w : IN STD LOGIC VECTOR( 3 DOWNTO ) ; : OUT STD LOGIC ) ; END mux4to ; ARCHITECTURE Structure OF mux4to IS COMPONENT dec2to4 PORT ( w : IN STD LOGIC VECTOR( DOWNTO ) ; En : IN STD LOGIC ; y : OUT STD LOGIC VECTOR( TO 3) ); END COMPONENT; SIGNAL High : STD LOGIC ; SIGNAL y : STD LOGIC VECTOR( 3 DOWNTO ) ; decoder: dec2to4 PORT MAP ( s,,y); < (w() AND y()) OR (w() AND y()) OR (w(2) AND y(2)) OR w(3) AND y(3) ) ; END Structure ; LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY dec2to4 IS PORT ( w : IN STD LOGIC VECTOR( DOWNTO ) ; En : IN STD LOGIC ; y : OUT STD LOGIC VECTOR( TO 3) ) ; END dec2to4 ; ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD LOGIC VECTOR(2 DOWNTO ) ; Enw < En & w ; WITH Enw SELECT y < WHEN, WHEN, WHEN, WHEN, WHEN OTHERS ; END Behavior ; Figure 6.58 VHDL code or Example 6.38.

58 May 9, 24 :4 vra6857_ch6 Sheet number 58 Page number 372 black 372 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY shiter IS PORT ( w : IN STD LOGIC VECTOR(3 DOWNTO ) ; Shit : IN STD LOGIC ; y : OUT STD LOGIC VECTOR(3 DOWNTO ) ; k : OUT STD LOGIC ) ; END shiter ; ARCHITECTURE Behavior OF shiter IS PROCESS (Shit, w) IF Shit THEN y(3) < ; y(2 DOWNTO ) < w(3 DOWNTO ) ; k < w() ; ELSE y < w; k < ; END IF ; END PROCESS ; END Behavior ; Figure 6.59 Structural VHDL code that speciies the shiter circuit in Figure Problems Answers to problems marked by an asterisk are given at the back o the book. 6. Show how the unction (w,, ) = m(, 2, 3, 4, 5, 7) can be implemented using a 3-to-8 binary decoder and an OR gate. 6.2 Show how the unction (w,, ) = m(, 2, 3, 5, 6) can be implemented using a 3-to-8 binary decoder and an OR gate. *6.3 Consider the unction = w + + w. Use the truth table to derive a circuit or that uses a 2-to- multiplexer. 6.4 Repeat problem 6.3 or the unction = + w. *6.5 For the unction (w,, ) = m(, 2, 3, 6), use Shannon s expansion to derive an implementation using a 2-to- multiplexer and any other necessary gates. 6.6 Repeat problem 6.5 or the unction (w,, ) = m(, 4, 6, 7).

59 May 9, 24 :4 vra6857_ch6 Sheet number 59 Page number 373 black Problems 373 LIBRARY ieee ; USE ieee.std logic 64.all ; USE ieee.numeric std.all ; ENTITY shiter IS PORT ( w : IN UNSIGNED(3 DOWNTO ) ; Shit : IN STD LOGIC ; y : OUT UNSIGNED(3 DOWNTO ) ; k : OUT STD LOGIC ) ; END shiter ; ARCHITECTURE Behavior OF shiter IS PROCESS (Shit, w) IF Shit = THEN y < wsrl; k < w() ; ELSE y < w; k < ; END IF ; END PROCESS ; END Behavior ; Figure 6.6 Behavioral VHDL code that speciies the shiter circuit in Figure Consider the unction = +w +w. Show how repeated application o Shannon s expansion can be used to derive the minterms o. 6.8 Repeat problem 6.7 or = + w. 6.9 Prove Shannon s expansion theorem presented in section *6. Section 6..2 shows Shannon s expansion in sum-o-products orm. Using the principle o duality, derive the equivalent expression in product-o-sums orm. 6. Consider the unction = w + + w. Give a circuit that implements using the minimal number o two-input LUTs. Show the truth table implemented inside each LUT. *6.2 For the unction in problem 6., the cost o the minimal sum-o-products expression is 4, which includes our gates and inputs to the gates. Use Shannon s expansion to derive a multilevel circuit that has a lower cost and give the cost o your circuit. 6.3 Consider the unction (w,,, w 4 ) = m(,, 3, 6, 8, 9, 4, 5). Derive an implementation using the minimum possible number o three-input LUTs.

60 May 9, 24 :4 vra6857_ch6 Sheet number 6 Page number 374 black 374 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; USE ieee.numeric std.all ; ENTITY barrel IS PORT ( w : IN UNSIGNED(3 DOWNTO ) ; s : IN UNSIGNED( DOWNTO ) ) ; y : OUT UNSIGNED(3 DOWNTO ) ) ; END barrel ; ARCHITECTURE Behavior OF barrel IS PROCESS (s, w) CASE s IS WHEN > y < w; WHEN > y < wror; WHEN > y < wror2; WHEN OTHERS > y < wror3; END CASE ; END PROCESS ; END Behavior ; Figure 6.6 VHDL code that speciies the barrel shiter circuit in Figure *6.4 Give two examples o logic unctions with ive inputs, w,...,w 5, that can be realized using 2 our-input LUTs. 6.5 For the unction,, in Example 6.27 perorm Shannon s expansion with respect to variables w and, rather than w and w 4. How does the resulting circuit compare with the circuit in Figure 6.52? 6.6 Actel Corporation manuactures an FPGA amily called Act, which has the multiplexerbased logic block illustrated in Figure P6.. Show how the unction = + w + can be implemented using only one Act logic block. 6.7 Show how the unction = w + w + + w can be realized using Act logic blocks. Note that there are no NOT gates in the chip; hence complements o signals have to be generated using the multiplexers in the logic block.

61 May 9, 24 :4 vra6857_ch6 Sheet number 6 Page number 375 black Problems 375 i i 2 i 3 i 4 i 5 i 6 i 7 i 8 Figure P6. The Actel Act logic block. *6.8 Consider the VHDL code in Figure P6.2. What type o circuit does the code represent? Comment on whether or not the style o code used is a good choice or the circuit that it represents. 6.9 Write VHDL code that represents the unction in problem 6., using one selected signal assignment. 6.2 Write VHDL code that represents the unction in problem 6.2, using one selected signal assignment. 6.2 Using a selected signal assignment, write VHDL code or a 4-to-2 binary encoder Using a conditional signal assignment, write VHDL code or an 8-to-3 binary encoder Derive the circuit or an 8-to-3 priority encoder Using a conditional signal assignment, write VHDL code or an 8-to-3 priority encoder Repeat problem 6.24, using an i-then-else statement Create a VHDL entity named i2to4 that represents a 2-to-4 binary decoder using an ithen-else statement. Create a second entity named h3to8 that represents the 3-to-8 binary decoder in Figure 6.7, using two instances o the i2to4 entity Create a VHDL entity named h6to64 that represents a 6-to-64 binary decoder. Use the treelike structure in Figure 6.8, in which the 6-to-64 decoder is built using ive instances o the h3to8 decoder created in problem Write VHDL code or a BCD-to-7-segment code converter, using a selected signal assignment. *6.29 Derive minimal sum-o-products expressions or the outputs a, b, and c o the 7-segment display in Figure 6.25.

62 May 9, 24 :4 vra6857_ch6 Sheet number 62 Page number 376 black 376 CHAPTER 6 Combinational-Circuit Building Blocks LIBRARY ieee ; USE ieee.std logic 64.all ; ENTITY problem IS PORT ( w : IN STD LOGIC VECTOR( DOWNTO ) ; En : IN STD LOGIC ; y, y, y2, y3 : OUT STD LOGIC ) ; END problem ; ARCHITECTURE Behavior OF problem IS PROCESS (w, En) y < ;y< ;y2< ;y3< ; IF En THEN IF w THEN y < ; ELSIF w THEN y < ; ELSIF w THEN y2 < ; ELSE y3 < ; END IF ; END IF ; END PROCESS ; END Behavior ; Figure P6.2 Code or problem Derive minimal sum-o-products expressions or the outputs d, e,, and g o the 7-segment display in Figure Design a shiter circuit, similar to the one in Figure 6.56, which can shit a our-bit input vector, W = w w, one bit-position to the right when the control signal Right is equal to, and one bit-position to the let when the control signal Let is equal to. When Right = Let =, the output o the circuit should be the same as the input vector. Assume that the condition Right = Let = will never occur Figure 6.2 shows a block diagram o a ROM. A circuit that implements a small ROM, with our rows and our columns, is depicted in Figure P6.3. Each X in the igure represents a switch that determines whether the ROM produces aorwhen that location is read. (a) Show how a switch (X) can be realized using a single NMOS transistor. (b) Draw the complete 4 4 ROM circuit, using your switches rom part (a). The ROM should be programmed to store the bits in row (the top row), in row, in ro, and in ro (the bottom row). (c) Show how each (X) can be implemented as a programmable switch (as opposed to providing either a or permanently), using an EEPROM cell as shown in Figure Briely describe how the storage cell is used.

63 May 9, 24 :4 vra6857_ch6 Sheet number 63 Page number 377 black Reerences 377 V DD a a 2-to-4 decoder d 3 d 2 d d Figure P6.3 A 4 4 ROM circuit Show the complete circuit or a ROM using the storage cells designed in Part (a) o problem 6.33 that realizes the logic unctions d 3 = a a d 2 = a a d = a a d = a + a Reerences. C. E. Shannon, Symbolic Analysis o Relay and Switching Circuits, Transactions AIEE 57 (938), pp Actel Corporation, MX FPGA Data Sheet, 3. QuickLogic Corporation, pasic 3 FPGA Data Sheet,

64 May 9, 24 :4 vra6857_ch6 Sheet number 64 Page number 378 black 378 CHAPTER 6 Combinational-Circuit Building Blocks 4. R. Landers, S. Mahant-Shetti, and C. Lemonds, A Multiplexer-Based Architecture or High-Density, Low Power Gate Arrays, IEEE Journal o Solid-State Circuits 3, no. 4 (April 995). 5. Z. Navabi, VHDL Analysis and Modeling o Digital Systems, 2nd ed. (McGraw-Hill: New York, 998). 6. J. Bhasker, A VHDL Primer, 3rd ed. (Prentice-Hall: Englewood Clis, NJ, 998). 7. D. L. Perry, VHDL, 3rd ed. (McGraw-Hill: New York, 998). 8. K. Skahill, VHDL or Programmable Logic (Addison-Wesley: Menlo Park, CA, 996). 9. A. Dewey, Analysis and Design o Digital Systems with VHDL (PWS Publishing Co.: Boston, 997).. D. J. Smith, HDL Chip Design (Doone Publications: Madison, AL, 996).