DESIGN AND ANALYSIS OF LOW POWER TEST PATTERN GENERATOR USING D FLIP-FLOP

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1 DESIGN AND ANALYSIS OF LOW POWER TEST PATTERN GENERATOR USING D FLIP-FLOP R.Ramalakshmi, M.E-VLSI Design, PSNA CET, Dindigul,Tamil Nadu,India, Abstract: - This paper focuses the design of power efficient Test Pattern Generator (TPG) using various flip-flops as the basic building block. In this paper, a novel Reconfigurable Johnson counter is constructed to generate a class of minimum transition sequences using modified D flip-flops which has the advantage of uniform distribution and low power transition density. The proposed design is analyzed for 0.12µm, 90nm and 70nm technology. From the analysis made by us, the proposed design revealed that the power efficiency improved by 7% and 56% area reduction can be achieved. Key Terms: Test Pattern Generator, Flip-flop, Reconfigurable Johnson counter, minimum transition sequences. I. INTRODUCTION TPG is a device which generates uniqueness of patterns to test the Circuit under Test (CUT). TPG is designed by using Reconfigurable Johnson counter (RJC). The TPG is going to be designed by power efficient flip-flop. The performance of the flip-flop and TPG are analyzed in terms of Power, Delay and Area. Flip-flop is an electronic circuit that stores a logical state of one or more data input signals in response to a clock pulse. The memory elements used in clocked sequential circuits are flip- flops. The state of a flip-flop is switched by a change in control input. The major difference among various flip-flops are based on 1. Number of inputs 2. The manner in which the inputs affect the binary state. A. AUTOMATIC TEST PATTERN GENERATION (ATPG) ATPG is an electronic design automation method technology used to find an input sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The generated patterns are used to test semiconductor devices after manufacture, and in S.Bibiana Vincy, M.E-VLSI Design, PSNA CET, Dindigul,Tamil Nadu,India, some cases to assist with determining the cause of failure the effectiveness of ATPG is measured by the amount of modeled defects, or fault models, that are detected and the number of generated patterns. These metrics generally indicate test quality and test application time. ATPG efficiency is another important consideration. It is influenced by the fault model under consideration, the type of circuit under test, the level of abstraction used to represent the circuit under test and the required test quality. II. PRIOR WORK Girard et al. analyzed the impact of an LFSR s polynomial on the CUT s switching activity, and proposed a method to select the LFSR seed for energy reduction [1]. Low-power TPGs are the lowtransition TPGs. Wang and Gupta used two LFSRs of different speeds to control those inputs that have elevated transition densities [2]. Corno et al. provided a low power TPG based on the cellular automata to reduce the test power in combinational circuits [3]. Another approach focuses on modifying LFSRs. The scheme in [4] reduces the power in the CUT in general and clock tree in particular. In [5], a lowpower BIST for data path architecture is proposed, which is circuit dependent. However, this dependency implies that non-detecting subsequences must be determined for each circuit test sequence. Bonhomme et al. [6] used a clock gating technique where two non-overlapping clocks control the odd and even scan cells of the scan chain so that the shift power dissipation is reduced by a factor of two. The ring generator [7] can generate a single-input change (SIC) sequence which can effectively reduce test power. The third class makes use of the prevention of pseudorandom patterns that do not have new fault detecting abilities [8] [10]. These flip-flops are critical timing elements in digital circuits and have a large effect on speed and power consumption of the digital circuits. Intensive research is going on in the field of low power, high speed flip-flops. In [11] Jaehyun et.al proposes a mixed- Vt flip-flop with reduced leakage which has a small increase in either setup time or clock-to-q delay. In [12] Weiqiang presents a reduction technique of leakage consumption for adiabatic sequential circuits based ISSN: Page 124

2 on two-phase complementary pass-transistor adiabatic logic using power gating scheme. A combined dual voltage assignment technique with intended clock skew scheduling is presented by Meng Tie et.al in [13]. III. SEQUENTIAL CIRCUITS The Sequential circuit is designed by using combinational circuits and flip-flops. Flipflop/clocked latch is an electronic circuit that is used as a Memory element in response to a clock pulse. A switching circuit whose output depends not only upon the present state of its input, but also on what its input conditions have been in the past. The sequential circuit made up of the memory elements and the clock distribution network the total. Fig. 1 shows that the basic diagram of clocked latch. The total power consumed =The power consumed by the flip-flop + The power by the sequential circuits + The power consumed by the Clock distribution N/W. Fig. 2.Diagram of TPG using LFSR With carefully looking at the bit pattern in the shift register, you can see there are all 4-bit combinations appeared except all 0 s. If you feed the pattern of 0000, the shift register would be stuck and it generates only 0 s infinitely. A seed pattern must not be 0 s. A. Draw back In Linear Feedback Shift Register generates pseudo random patterns. This leads high switching activities and high power dissipation in CUT. LFSR needs to generate long pseudo random sequences to achieve target fault coverage. V. Flip-flops Fig. 1.Basic diagram of clocked latch IV. LINEAR FEEDBACK SHIFT REGISTER The wide use of sequential logic and memory storage systems in modern electronics results in the implementation of low power and high speed design of basic memory elements. One of the most important basic memory elements is the D flip-flop (DFF). Two different designs of D flip-flops in CMOS logic are proposed in this section. Flip-flops are the basic building block for TPG. LFSR is a linear feedback shift register whose input bit is a linear function of previous function that contains the signal through the register from one bit to the next most-significant when it is clocked. Fig. 2 shows the block diagram of LFSR. Linear feedback shift register can be made simple by performing exclusive-or gate on the outputs of two or more of the flip-flops and feeding those outputs back in to the input of one of the flip-flops. Linear feedback shift registers generates extremely good pseudorandom pattern generators. Fig. 3 shows the pattern generation in LFSR. A PRBS bit stream can be generated by using a LFSR. When the shift register is filled up with a seed pattern of 1 s here, the table in the right hand side depicts how the register contents change and put out a series of PRBS. Right after the final bit, it returns to the top of the bit stream. There are 15 bits of pseudo random bit stream generated. An L bit LFSR generates 2^L-1 of PRBS. Fig. 3.Pattern Generation Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"), and JK types are the common ones. Their ISSN: Page 125

3 performances are analyzed in various technologies i.e., 0.18µm, 0.12 µm, 90nm and 70nm. TABLE I. ANALYSIS OF FLIP-FLOPS Fig. 4.Reconfigurable Johnson Counter A. Advantages of the proposed method i) Minimum transitions In the proposed pattern, each generated sequence applied to each scan chain is a single input change sequence, which can minimize the input transition and reduce the test power. ii) Uniqueness of patterns From the analysis we have chosen the results of 90nm technology as an example. RS flip-flop consumes 10.35% lower power and 20% smaller area than D flip-flop. Even though RS flip-flop takes lower power and smaller area, it has an indeterminate state as disadvantage. Indeterminate state of RS flipflop does not give the accurate output. So RS flipflop may not be used as a basic building block. JK flip-flop consumes 92.69% higher power and 43.75% larger area than D flip-flop. Because of having higher power and larger area, the JK flip-flop is not used as a basic building block for TPG. The proposed sequence does not contain any repeated patterns, and the number of distinct patterns in a sequence can meet the requirement of the target fault coverage for the CUT. iii) Uniform distribution of patterns In LFSR we use extra hardware to get more correlated test sequences with a low number of transitions. However, they may reduce the randomness in the patterns, which may result in lower fault coverage and higher test time. This should be avoided in our proposed method. Based on the above analysis we select D flipflop as a basic building block for the TPG. VI. Reconfigurable Johnson Counter The basic building block for this Reconfigurable Johnson Counter is D Flip-flop. It also has a multiplexer and an AND gate. When selection line is set to 1 and input is set to 0, the RJC is initialized to all zero states. When input is set to 1 and selection line is set to 0, the RJC generates the test pattern by the clock signal. Fig. 4 shows the RJC. Fig. 5.Test Pattern of RJC ISSN: Page 126

4 FLIP-FLOP MODELS TABLE II. PERFORMANCE OF D FLIP-FLOPS Fig. 6.16T D Flip-flop Fig. 7.15T D Flip-flop The existing D flip-flops are 16T and 15T consumes more power and have larger area than the 5T D flip-flop. The proposed 18 T D flip-flop consumes lower power but occupies slightly larger area than the existing flip-flops, so we select 5 T D flip-flop for designing the TPG. PROPOSED FLIP-FLOP Fig. 8.18T D Flip-flop Fig. 10. Schematic diagram of 5T TPG Fig. 9.5T D Flip-flop ISSN: Page 127

5 TABLE III. ANALYSIS OF TPG 3) F. Corno, M. Rebaudengo, M. Reorda, G. Squillero, and M. Violante, Low power BIST via non-linear hybrid cellular automata, in Proc. 18th IEEE VLSI Test Symp., Apr. May 2000, pp ) P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H. Wunderlich, A modified clock scheme for a low power BIST test pattern generator, in Proc. 19th IEEE VTS VLSI Test Symp., Mar. Apr. 2001, pp ) D. Gizopoulos, N. Krantitis, A. Paschalis, M. Psarakis, and Y. Zorian, Low power/energy BIST scheme for datapaths, in Proc. 18th IEEE VLSI Test Symp., Apr. May 2000, pp The TPG using existing D flip-flops are 16T TPG and 15 T TPG consumes more power and have larger area than the 5T TPG. The proposed 18 T TPG consumes lower power but occupies slightly larger area than the existing 16 T TPG and 15 T TPG, so we select 5 T TPG for generating the minimum transition sequences. VII. CONCLUSION TPG is constructed and analyzed by its performance parameters such as area, power, delay, using various micrometer technologies 0.18μm, 0.12μm, 90nm and 70nm. The performance analysis is made using double edge triggered flip-flops and single edge triggered flip flops. It reveals that double edge triggered flip flop performance degraded when compared to their single edge triggered flip-flops, due to more complex design and the fact that most of that complexity affects the signal propagation along the critical path. From the analysis made by us, the proposed design revealed that the power efficiency improved by 7% and 56% area reduction can be achieved. References 1) P.Girard, L.Guiller, C.Landrault and S.Pravossoudovitch (Apr.1999) A test vector inhibiting technique for low energy BIST design in Proc.17th IEEE VLSI Test Symp., pp ) S.Wang and S.Gupta. (Jul.2002) DS-LFSR: A BIST TPG for low switching activity, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.21, no.7, pp ) Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, A gated clock scheme for low power scan testing of logic ICs or embedded cores, in Proc. 10th Asian Test Symp., Nov. 2001, pp LIANG et al.: TEST PATTERNS OF MULTIPLE SIC VECTORS 623 7) Laoudias and D. Nikolos, A new test pattern generator for high defect coverage in a BIST environment, in Proc. 14th ACM Great Lakes Symp. VLSI, Apr. 2004, pp ) P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, A test vector inhibiting technique for low energy BIST design, in Proc. 17 th IEEE VLSI Test Symp., Apr. 1999, pp ) S. Manich, A. Gabarro, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira, and M. Santos, Low power BIST by filtering nondetecting vectors, J. Electron. Test.-Theory Appl., vol. 16, no. 3, pp , Jun ) F. Corno, M. Rebaudengo, M. Reorda, and M. Violante, A new BIST architecture for low power circuits, in Proc. Eur. Test Workshop, May 1999, pp ) Jaehyun Kim, Chungki Oh and Youngsoo Shin, (2009) Minimizing Leakage Power Of Sequential Circuits Through Mixed-Vt Flip-Flops And Multi-VtCombinational Gates, Journal ACM Transactions on ISSN: Page 128

6 Design Automation of Electronic Systems, Volume 15 Issue 1, December International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February ) Weiqiang Zhang, Yu Zhang, Shi Xuhua and Jianping Hu, (2010) Leakage Reduction of Power- Gating Sequential Circuits Based on Complementary Pass-Transistor Adiabatic Logic Circuits, Innovative Computing & Communication, Intl. Conference on and Information Technology & Ocean Engineering, pp ) Meng Tie, Haiying Dong, Tong Wang and Xu Cheng,(2010) Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement, Design, Automation& Test in Europe Conference & Exhibition (DATE). ISSN: Page 129