HIGH SPEED AREA EFFICIENT 1-BIT HYBRID FULL ADDER

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1 HIGH SPEED AREA EFFICIENT 1-BIT HYBRID FULL ADDER Sachin Kumar *1, Aman Kumar #2, Puneet Bansal #3 * Department of Electronic Science, Kurukshetra University, Kurukshetra, Haryana, India # University Institute of Engineering and Technology, Kurukshetra University, Kurukshetra, Haryana, India Abstract- The main requirement of Very Large Scale Integration (VLSI) circuit is to be fast and low energy consumption. So, the analysis is done by optimizing the delay, which results in fast processing and low average energy consumed. In this paper, 1-bit hybrid full adder is designed using Complementary Metal Oxide Semiconductor (CMOS), transmission gate and pass transistor logic. The circuit is implemented on Cadence Virtuoso 6.1 tool in 180-nm technology with 1.8V supply voltage. The delay (14.32ps) is found to be very small with significant reduction in the Power- Delay-Product(0.904fJ). The number of transistors is reduced; resulting in area optimization. The proposed 1-bit hybrid full adder design is found to be very fast as compared to the previous existing full adder circuits. Keywords CMOS,CPL,Hybrid Full Adder,Transmission Gate. I. INTRODUCTION The demand of Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) with an reduced delay and energy consumption characteristics is increasing rapidly with the use of battery operated high speed portable devices like mobile phones, netbooks, super computers, etc. [1]. Digital circuits i.e. Combinational and sequential perform a number of arithmetic and logical operations. Addition is one of the most important arithmetic operations which will add two or more numbers. This operation also works as a nucleus for many other important operations like subtraction, multiplication, and address calculation etc. [2] The addition operation is performed by digital device known as adder. In the designing of the complex arithmetic circuits, mainly two types of adders i.e. half adder and full adder are used. The combinational circuit that is used to perform the addition of 2 numbers is known as half adder, and the combinational circuit used for addition of 3 numbers is known as full adder. Full adders affect the overall performance of the complex arithmetic circuits as these are used in the critical paths of circuits. As speed is one of the most important factors in the modern life, designer tries to speed up the system while designing.[3] Therefore, analysis is performed to obtain optimum performance. A. Conventional Half Adder Combinational circuit that performs addition of 2 bits is known as half adder. Half adder is a 2-input and 2-output device. The inputs i.e. the augend and the addend are named as A and B, and the outputs the sum and carry are named as S and C respectively. The truth table of the half adder is shown in the Table 1. Table I. Half Adder Truth Table Inputs Outputs A B S C By using Karnaugh (K) map, the truth table is expressed in the relationship between the input and output functions as described in(1) and (2). S = A B (1) C = AB (2) The circuit diagram of the half adder is shown in Fig. 1. Fig. 1. Half Adder This configuration can generate a carry signal to the next order bit, but it cannot accept a carry from the lower order bit, therefore it is termed as half adder. Whereas in full adder, in addition to the two addends we have a carry input signal, which is generated from the previous lower order bit operation. B. Conventional Full Adder Full adder is a combinational circuit that performs the addition of 3 bits. Full adder is 3-input and 2-output device. Two input

2 variables (A and B) represent the most significant bits to be added and the third input variable (C in ) represent the least significant bit generated from the previous order bit, known as carry input.the outputs are named as sum(s) and carry output (C out ).The three input variables with eight possible combinations and corresponding outputs are shown in Table 2. TABLE II. Full Adder Truth Table INPUTS OUTPUTS A B Cin S Cout others[1].the most basic logic design styles used for designing full adder are complementary metal oxide semiconductor (CMOS)[4,5],Complementary pass-transistor logic (CPL)[6,7] and transmission gate full adder (TGA)[2,8]. The other logic designs that use more than one logic style for their implementation are known as hybrid design. These designs exploit the features of different logic styles to improve the overall performance of the full adder [1]. The proposed adder consists of hybrid design, and known as hybrid full adder. The proposed circuit is represented with the combination of three blocks as shown in Fig. 3. Block 1 is the XNOR blocks that is followed by block 2 and block 3 for generating the output carry (C out ) and sum signal (S) respectively. The output variables sum and carry out are expressed in terms of inputs by using Boolean Expression as shown in(3) and (4). S=A B C in (3) C out = (A B)C in +AB (4) The circuit diagram of the full adder is shown in Fig 2. Fig. 3 Full Adder Block Diagram The circuit diagram of the 1-bit hybrid full adder is shown in Fig.4. Fig. 2. Full Adder Logic Diagram II. PROPOSED FULL ADDER In order to match with the throughput required in modern high performance applications, the operating frequency and circuit complexity of the circuits are improved. On the other hand, with the increasing number of portable electronic devices, the demand of low power building blocks also increases, which makes possible the existence of long lasting battery operated systems [11].With the improvement in speed, reduction in delayand the power consumption of the system is also required [10]. While designing the proposed 1-bit hybrid full adder, power-delay product is considered to be the major factor. The power-delay product relates the amount of energy consumed in execution of an operation [11].The proposed full adder is designed using number of different logic circuits having their own advantages and disadvantages. Multiple logic styles in a circuit tend to favor one performance aspect at the expense of Fig. 4.Proposed Hybrid Full Adder Circuit

3 The blocksare designed effectively to optimize the delay, energy consumption and number of transistors. A. Modified XNOR Block XNOR block is responsible for the large delay in the full adder circuit. So, in the proposed full adder circuit,the XNOR circuit i.e. block 1 is optimized and designed only using three transistors. The modified XNOR block presented here offers very high-speed (with acceptable small increase in power) as compared with other XNOR circuit. Hence, reducing the overall circuit delay [1]. B. Carry Generation Block In the proposed circuit, the carry generation block is similar to existing hybrid full adder circuit as shown in [1].The carry generation block is implemented using an inverter consisting PM2 and NM3 followed by the pair of transmission gates (PM3, NM4 and PM4, NM5) as shown in Fig. 4. The input carry signal (C in ) propagates through a single transmission gate (PM3 and NM4), reducing the overall carry propagation path significantly. The deliberate use of strong transmission gates guarantees further reduction in propagation delay of the carry signal [1]. C. Sum Generation Module Inthe proposed hybrid design, the sum module is also similar to existing hybrid full adder circuit as shown in [1]. Output of Block 1 is applied to block 3 consisting of PMOS transistors (PM5 and PM6) and NMOS transistors (NM6 AND NM7); realizing the second stage XNOR block to implement the complete Sum function. III. OPERATION OF THE PROPOSED FULL ADDER Fig. 3 shows the detailed diagram of the proposed 1-bit hybrid full adder. The proposed adder is designed with the combination of three different logic blocks. The first block is the XNOR circuit having three transistors. The transistor PM1 is permanently ON in the circuit, by applying a Vss voltage at the gate terminal. Inputs A and B are applied to source terminals of the pull down NMOS transistors (NM1 and NM2).These three transistors PM1, NM1 and NM2 constitute the XNOR logic. Output of XNOR block is applied to block 2 and block 3 which are known as the carry generation block and the sum generation block respectively. The inverter (PM2) of block 2 having width (1600nm) prevents the loading effect so that block 2 and block 3 will operate efficiently and act as buffer between the input and output stages. The carry generation block is fed by a buffered inverter. The carry block is made up of two strong transmission gates which are responsible for fast switching in the carry logic thus, minimizing the propagation delay. In the sum generation block, the second stage XNOR circuit is used to generate the sum output. The generation of Cout has also been analysed from the full adder truth table shown in Table II as follows: If, A=B, then Cout=B; else, Cout=Cin. [1] The condition i.e. whether A=B is checked by the XNOR block. If they are same, then either the Cout is equals to the Bor it is equal to Cin. Two strong transmission gates are used in the carry generation block, each for implementing one condition out of two. The lower transmission gate consisting of MP3 and NM4 is used for implementing the first condition i.e. Cout=B and the upper transmission gate consisting of MP4 and NM5 is used for implementing the second condition i.e. Cout=Cin [1]. The transistor dimensions are chosen efficiently to take out the best results. The transistor sizing is shown in Table III. TABLE III. Transistors Size Transistor Width(nm) Length(nm) PM NM1, NM PM NM PM3. PM NM4, NM PM5, PM NM6, NM The simulation waveform of the hybrid 1-full adder is shown in Fig. 5. Fig. 5. SimulationWaveform IV. RESULTS The simulation of the proposed 1-bit hybrid full adder is carried out using 180-nm technology and compared with the other potential adder designs shown in Table IV.The powerdelay product(pdp) also known as energy consumption has been minimized in the proposed circuit with an aim to optimize the number of transistor used and delay of the circuit. The proposed 1-bit hybrid full adder uses only 13 transistors as compared to other full addersas shown in Table IV.Because of huge reduction in propagation delay, the PDP of the

4 proposed hybrid full adder is significantly improved as comparison shown in Table IV. TABLE IV.Comparison Table Design Delay PDP Transistor Ref. (ps) (fj) Count TGA ,8 FA_SR CPL CPL ,7 C-CMOS ,10 HPSC Hybrid Full Adder Hybrid 1-Bit- FA Present Work Present signal and either of the input signals A or B (when A=B). The carry signal path length is also minimized as it propagates through a strong single transmission gate. The comparison between the delays of various full addersis shown in Fig. 7. The comparison between the power-delay products of various full adders is shown in Fig. 6. Fig. 7.Comparison between the delays of various full adders Fig. 6.Comparison between the power-delay products of various full adders. A. Calculation of Average Power Consumption Power consumption is classified in two categories i.e. static power and dynamic power also known as average power consumption[1].dynamic power consumption is the dominant component of the power consumption and it arises because of charging and discharging of the load capacitances. The dynamic or the average power consumption of the proposed 1- bit hybrid full adder is calculated and found to be 63.13µw. Mostly power of the circuit is consumed by the XNOR block. This is because of the PMOS transistor (PM1) which is permanently turned ON and also because of absence of buffer inverter at the input of XNOR block. B. Calculation of Propagation Delay Adder is used asa fundamental computational unit in many systems. Also, the overall speed of the entire system depends mainly upon the adders delay. [1] Thespeed of adder is defined by the path lengths of the input signals, and here it mainly dependsupon the input carry signal. So, the overall speed of the adder depends on the propagation delay of the input carry signal. In the proposed 1-bit hybrid full adder design,in order to reduce the path length of the carry signal, it is generated by controlled transmission of the input carry V. CONCLUSION In this paper, we have represented a new hybrid design of a 1- bit full adder.the simulation was carried out using Cadence Virtuoso 6.1with 180-nm technology. The proposed hybrid 1- bit full adder is compared with the standard design approaches like CMOS, CPL, TGA and other existing full adder designs. The simulation result reflects clearly that the proposed hybrid 1-bit full adder offered reduced Power-Delay-Product (0.904fJ) as compared to the previous results. The number of transistor count has been reduced in the proposed design by using the modified XNOR block, results in a very low delay (14.32ps). The proposed full adder can be used in very high speed device applications with acceptable energy consumption. ACKNOWLEDGMENT The authors would also like to thank the University Institute of Engineering and Technology, Kurukshetra University, Kurukshetra, Haryana, India, for providing the necessary computing facility and tools. REFERENCES [1] Patha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar and Anup Dandapat, Performance analysis of a low-power high speed hybrid 1-bit full adder circuit, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. Sep [2] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, Performance analysis of low-power 1-bit CMOS full adder cells, IEEE Trans. Very LargeScale Integr. (VLSI) Syst., vol. 10, no. 1, pp , Feb [3] S. Goel, A. Kumar, and M. A. Bayoumi, Design of robust, energyefficient full adders for deep-submicrometer design using hybrid-cmos logic style, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp , Dec [4] N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI Design:A Circuits and Systems Perspective, 3rd ed. Delhi, India: PearsonEducation, [5] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital

5 IntegratedCircuits: A Design Perspective, 2nd ed. Delhi, India: Pearson Education,2003. [6] D. Radhakrishnan, Low-voltage low-power CMOS full adder, IEEEProc.-Circuits Devices Syst., vol. 148, no. 1, pp , Feb [7] R. Zimmermann and W. Fichtner, Low-power logic styles: CMOS versus pass-transistor logic, IEEE J. Solid-State Circuits, vol. 32, no. 7, pp , Jul [8] C. H. Chang, J. M. Gu, and M. Zhang, A review of 0.18-μm full adder performances for tree structured arithmetic circuits, IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp , Jun [9] M. Zhang, J. Gu, and C.-H. Chang, A novel hybrid pass logic with static CMOS output drive full-adder cell, in Proc. Int. Symp. CircuitsSyst., May 2003, pp [10] K. Navi, M. Maeen, V. Foroutan, S. Timarchi, and O. Kavehei, A novel low-power full-adder cell for low voltage, VLSI J. Integr., vol. 42, no. 4, pp , Sep [11] M. Aguirre-Hernandez and M. Linares-Aranda, CMOS full-adders for energy-efficient arithmetic applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp , Apr

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