Lab 1: Study of Gates & Flip-flops

Transcription

1 Aim Lab 1: Study of Gates & Flip-flops To familiarize with circuit implementations using ICs and test the behavior of different logic gates and Flip-flops. Hardware Requirement a. Equipments - Digital IC Trainer Kit b. Discrete Components - 74LS00 Quad 2-Input NAND gate 74LS02 Quad 2-Input NOR gate 74LS04 Hex 1-Input NOT gate 74LS08 Quad 2-Input AND gate 74LS10 Triple 3-Input NAND gate 74LS11 Triple 3-Input AND gate 74LS32 Quad 2-Input OR gate 74LS86 Quad 2-Input XOR 74LS73 JK-Flip flop 74LS74 D Flip flop Background Digital logic devices are the circuits that electronically perform logic operations on binary variables. The binary information is represented by high and low voltage levels, which the device processes electronically. The devices that perform the simplest of the logic operations (such as AND, OR, NAND, etc.) are called gates. For example, an AND gate electronically computes the AND of the voltage encoded binary signals appearing at its inputs and presents the voltage encoded result at its output. The digital logic circuits used in this laboratory are contained in integrated circuit (IC) packages, with generally 14 or 16 pins for electrical connections. Each IC is labeled (usually with an 74LSxx number) to identify the logic it performs. The logic diagrams and pin connections for these IC s are described in the TTL Data Book by Texas Instruments1. The transistor-transistor logic(ttl) IC s used in this laboratory require a 5.0 volt power supply for operation. TTL inputs require a voltage greater than 2 volts to represent a binary 1 and a voltage less than 0.8 volts to represent a binary 0. Pin numbering is standard on IC s. Figure 1-1 illustrates the pin numbering for a 14-pin dual in-line package (DIP). With the IC oriented as shown, the numbering starts at the top left and proceeds counter-clockwise around the chip: Figure 1.1: A 14-pin DIP To construct circuits with IC s, a circuit board that allows easy connections to IC pins should be used. The circuit board contains rows of solder less tie points, a 5-volt power supply, a common circuit point (ground), toggle switches for input, and LEDs (light emitting diodes) for output. 1

2 Logic Gates and their Properties Figure 1.2: Logic Gates: Its symbols and description Figure 1.3: Truth Table of 2 input logic gates 2

3 Figure 1.4: Pin configuration diagrams of some commonly used logic gates 3

4 Flip- Flops-Theory Digital electronic circuit is classified into combinational logic and sequential logic. Combinational logic output depends on the inputs levels, whereas sequential logic output depends on stored levels and also the input levels. Figure 1.5: Sequential logic representation The storage elements (Flip -flops) are devices capable of storing 1-bit binary info. The binary info stored in the memory elements at any given time defines the state of the Sequential circuit. The input and the present state of the memory element determines the output. Storage elements next state is also a function of external inputs and present state. Flip-Flops and their properties Flip-flops are synchronous bistable devices. The term synchronous means the output changes state only when the clock input is triggered. That is, changes in the output occur in synchronization with the clock. A flip-flop circuit has two outputs, one for the normal value and one for the complement value of the stored bit. Since memory elements in sequential circuits are usually flip-flops, it is worth summarizing the behavior of various flip-flop types before proceeding further. All flip -flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in the response invoked by different value of input signals. The four types of flip -flops are defined in the Table 1.1. Flip Flop Name Flip Flop Symbol Characteristic Table Characteristic Equation Excitation Table SR S R Q(next) 0 0 Q ? Q(next) = S + R Q SR = 0 Q Q(next) S R X X 0 JK J K Q(next) 0 0 Q Q Q(next) = JQ + K Q Q Q(next) J K X X 1 0 X X 0 4

5 D T D Q(next) T Q(next) 0 Q 1 Q Q(next) = D Q(next) = TQ + T Q Q Q(next) D Q Q(next) T Table 1.1 Flip-flops and their properties The characteristic table in the third column of Table 1.1 defines the state of each flip-flop as a function of its inputs and previous state. Q refers to the present state and Q(next) refers to the next state after the occurrence of the clock pulse. Figure 1.6: IC7474 D Flip-flop connection diagram Figure 1.7: IC7473 J-K Flip-flop connection diagram 5

6 Pre -lab Questions 1. A basic 2-input logic circuit has a HIGH on one input and a LOW on the other input, and the output is HIGH. What type of logic circuit is it? 2. A logic circuit requires HIGH on all its inputs to make the output HIGH. What type of logic circuit is it? 3. Develop the truth table for a 3-input AND gate and also determine the total number of possible combinations for a 4-input AND gate. 4. Which logic gate is used as a two-bit adder? 5. What is Flip flop? Lab Procedure 1. Refer datasheet for the input and output pin numbers of the IC. (For example in a NAND gate IC, pin numbers 1, 2, 4, 5, 9 10, 12, 13 are inputs and 3, 6, 8 and 11 are outputs). 2. Connect the particular input pins to the logic input section using a connecting wire. 3. Similarly connect the output pin to the logic output section of the trainer kit. 4. Verify the functionality of NOT gate and 2-input AND, OR, NAND, NOR and EXOR gates,jk Flip flop and D Flip flop. 5. Write the truth-table for each. Post-lab Questions 1. If the two waveforms A and B shown below are applied to the circuit, draw the timing diagram for the circuit, showing the outputs of G1, G2 and G3 with the inputs A and B. 2. Implement the basic gates using Universal gates. 3. Implement NOR using NAND gates and NAND gate using NOR gates. 4. What type of logic gate does this logic circuit configuration represent? a. NAND Gate b. EXOR Gate c. NOR Gate d. EXNOR Gate 5. What is the Difference between Combinational circuits and Flip-flop? 6. Show how the function A B + CD can be realized. a. Using AND,OR and inverter gates b. Using NAND gates c. Using NOR gates 6

7 7. A circuit has 4 inputs RSTU and for outputs VWYZ. RSTU represents a BCD digit. VW represents the quotient and YZ the remainder when RSTU is divided by 3 (VW and YZ represents 2 bit binary numbers). Assume that invalid inputs do not occur. Realize the circuit using a minimum 2-level NAND gate circuit. 8. Realize the following functions using only NAND gates. a. xyz + x yz b. ( A + B + C)( A + B + C) c. x yz + x yz + xyz + xyz 9. Implement the true form and complement form of the function A+BC+AB. 10. Implement the following function using Ex-OR and Ex-NOR gates: f ( A, B, C, D) = Σm(0,3,5,9,10,12,15) 11. a) How will you use a 4-input AND gate as a 2 input AND gate? b) How will you use a 4-input OR gate as a 2 input OR gate? c) How will you use a 4-input NAND gate as a 2 input NAND gate? d) How will you use a 4-input NOR gate as a 2 input NOR gate? e) How will you use a 4-input Ex-OR gate as a 2 input EX-OR gate? 12. Implement Y=ABCD using 2 input NAND gates. 13. Implement Y = A + B + C + D using 2 input NOR gates. 7

8 Lab 2: Design of Half Adder and Full Adder Aim To design and verify the truth table for half adder & full adder. Hardware Requirement Equipment : Digital IC Trainer Kit Theory Discrete Components : 74LS08 Quad 2 input AND gate 74LS32 Quad 2 input OR gate 74LS86 Quad 2 input XOR gate A Binary adder is a circuit which is able to add together two binary numbers. The half adder adds two binary digits an addend and an augend to produce a sum and carry. The sum can be implemented by using an Exclusive OR gate and an AND gate can be used for carry generation. The Boolean expression for the sum and carry are Sum S = A B Carry C = A.B The full adder adds an addend, an augend and carry input generated by the previous stage addition. It has two outputs, sum and carry. Full adder circuit can be implemented using AND,OR and EX- OR gates. Full adder circuit can also be implemented with the help of two half adder circuits. The first half adder is used to add two inputs and generate sum and carry output. Then second half adder combines the sum and carry input and generate final sum and carry out. The sum and carry can be expressed as Sum S = A B Cin Carry C = (A B)Cin+AB = AB+ BCin + ACin Experimental Procedure HALF ADDER Figure 2.1: Half-Adder Truth table and Schematic 8

9 Figure 2.2: Half-Adder using NAND & NOR logic FULL ADDER Figure 2.3: Full-Adder Truth table and Schematic Figure 2.4: Full-Adder using two Half-Adders Figure 2.5: Full-Adder using NAND logic 9

10 Figure 2.6: Full-Adder using NOR logic Pre lab Questions 1. What is meant by combinational circuit? 2. What is a Half adder? 3. What is a Full adder? 4. What is a Parallel adder? 5. State the limitations of Karnaugh map. Lab Procedure 1. Connect the circuit as shown in the figure. 2. Connect the power supply and ground to the respective pin numbers to all the IC s. 3. Give the inputs and verify the output in the truth table. Post lab Questions 1. Two numbers (1101 and 1011) are applied to a 4-bit parallel adder. The input Carry is 1. Determine the sum and output carry. 2. Design a combinational circuit that will multiply two two-bit binary values. 3. Realize a 4-bit parallel adder by cascading 4-full adder. 4. Realize a 4-bit subtractor by using 4-bit adder and inverters. 5. Design a combinational logic circuit for the following verbal problem statement. An output is to be true when the value of the inputs exceeds 3. The weighing for each input variable is as follows: w=3; x=3; y=2; z=-1 10

11 Lab 3: Design of Magnitude Comparator Introduction The purpose of this experiment is to introduce the design of 2-Bit Magnitude Comparator. Hardware Requirement a. Equipments - Digital IC Trainer Kit b. Discrete Components - 74LS02 Quad 2-Input NOR gate 74LS04 Hex 1-Input NOT gate 74LS08 Quad 2-Input AND gate 74LS00 Quad 2-Input NAND gate 74LS266 Quad 2-Input XNOR gate 74LS86 Quad 2-Input XOR 74LS10 Triple 3-Input NAND Background Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that compare the digital signals at their input terminals and produces an output depending upon the condition of the inputs. For example, whether input A is greater than, smaller than or equal to input B etc. Digital Comparators can compare a variable or unknown number for example A (A1, A2, A3, An, etc) against that of a constant or known value such as B (B1, B2, B3,... Bn, etc) and produce an output depending upon the result. For example, a comparator of 2-bit, (A and B) would produce the following three output conditions. A > B, A = B, A < B This is useful if we want to compare two values and produce an output when the condition is achieved. For example, produce an output from a counter when a certain count number is reached. Consider the simple 2-bit comparator below. 2 Bit Magnitude Comparator Implementation A = A1A0 B = B1B0 Here each subscript represents one of the digits in the numbers. Equality The binary numbers A and B will be equal if all the pairs of significant digits of both numbers are equal, i.e., A1 = B1 and A0 = B0 Since the numbers are binary, the digits are either 0 or 1 and the Boolean function for equality of any two digits Ai and Bi can be expressed as x = Ai B A. B i. i + i i 11

12 xi is 1 only if Ai and Bi are equal. For the equality of A and B, all xi variables (for i=0,1) must be 1. So the equality condition of A and B can be implemented using the AND operation as ( = B) = x x A 1 The binary variable (A=B) is 1 only if all pairs of digits of the two numbers are equal. Inequality In order to manually determine the greater of two binary numbers, we inspect the relative magnitudes of pairs of significant digits, starting from the most significant bit, gradually proceeding towards lower significant bits until an inequality is found. When an inequality is found, if the corresponding bit of A is 1 and that of B is 0 then we conclude that A>B. (A>B) and (A < B) are output binary variables, which are equal to 1 when A>B or A<B respectively. Experimental Procedure o Figure 3.1: 2-bit Magnitude Comparator 12

13 Pre Lab questions Table 3.1: Function Table of 2-bit Magnitude Comparator INPUTS OUTPUTS A1 A0 B1 B0 A < B A = B A > B Define magnitude comparator? 2. Write the output expressions for A<B and A>B. 3. Find out and label the output terminals (A<B, A=B and A>B) for the given 2 bit comparator circuit. (experimental circuit diagram) 4. List out the applications of comparators? 5. Which Logic gate is used to find A=B? Lab Procedure 1. Construct the logic circuit of the 2-bit magnitude comparator shown in Figure Use different sets of inputs for A and B to check each of the outputs A<B, A=B and A>B. Post Lab questions 1. Design 8 bit comparator using IC How many IC 7485 required to design 24 bit comparator? 3. Give a summary of the points that you have learned from this experiment. 4. Design a 4-bit comparator using two 2-bit comparators. 5. Design a 8-bit comparator using two 4-bit comparators. 13

14 Lab 4: Design of Encoder & Decoder Aim To design and verify the truth table for 8-3 Encoder & 3-8 Decoder logic circuit. Hardware Requirement Equipment : Digital IC Trainer Kit Discrete Components : 74LS08 Quad 2 input AND gate 74LS32Quad 2 input OR gate 74LS04 Hex 1 input NOT gate Theory (i) Encoder: Encoder takes all the data inputs one at a time and converts them to a single encoded output, it is a multi-input data line, combinational logic circuit that converts the logic level 1 data at its input to an equivalent binary code at its output. Encoder has 2 n input lines with common types that include 4 to 2,8 to 3 & 16 to 4 line configuration. Encoders are available to encode either a decimal or hexadecimal input pattern to typically binary or BCD output code. (ii)decoder: A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different; e.g. n-to-2n, BCD decoders. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding. Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single n-to-2 n decoder to generate the minterms, and an OR gate to form the sum. The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate. Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder with m OR gates. Suitable when a circuit has many outputs, and each output function is expressed with few minterms. Figure 4.1: Block Schematic of 8x3 Encoder Inputs Outputs I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 D 3 D 2 D

15 The output equations of the encoder 8Χ3 are the following: D3 = I4 +I5 +I6 +I7 D2 = I2 +I3 +I6 +I7 D1 = I1 +I3 +I5 +I7 Figure 4.2: Realization of 8x3 Encoder Figure 4.3: Block Schematic of 3x8 Decoder Inputs Outputs A B C Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y Table 4.2: Function Table of 3x8 Decoder 15

16 Figure 4.4: Realization of 3x8 Decoder Procedure 1. The truth table and a design of 8 to 3 Encoder, 3 to 8 decoder are given. 2. Realize this circuit on your board by using logic circuit. 3. Connect three inputs x,y,z to the switches & eight outputs vice-versa. 4. Connect the functions outputs to LEDs. 5. Verify input/output relation (Truth table) of this converter. Pre lab Questions 1. What is an encoder? 2. What is a decoder? 3. List the difference between Multiplexer & Encoder? 4. Draw 4-2 encoder circuit? Post lab Questions 1. Draw the logic symbol of 3x8 Decoder using two 2x4 decoder? 2. Implement the following expression using decoder F=XY+YZ. 3. Write the truth table for 3-input priority encoder. 4. Realize a Half Adder using a 2-to-4 line decoder. 5. Realize a Full Adder using a 3-to-8 line decoder. 6. Realize a Full Subtractor using 3-to-8 line decoder with inverting outputs. 16

17 Lab 5: Design of 4:1 Multiplexer and 1:4 De-multiplexer Aim To implement and verify the functional table of 4:1 Multiplexer and 1:4 De-multiplexer. Hardware Requirement a. Equipments - Digital IC Trainer Kit b. Discrete Components - 74LS04 Hex 1-Input NOT gate 74LS08 Quad 2-Input AND gate 74LS11 Triple 3-Input AND gate 74LS32 Quad 2-Input OR gate Theory Multiplexer Multiplexers which sometimes are simply called "Mux" or "Muxes", are devices that act like a very fast acting rotary switch. They connect multiple input lines 2, 4, 8, 16 etc one at a time to a common output line and are used as one method of reducing the number of logic gates required in a circuit. A multiplexer of 2 n inputs has n select bits, which are used to select which input line to send to the output. A multiplexer, or data selector, can be also be used to implement combinational logic circuits. A multiplexer implementation table is used to determine the input connections for the multiplexer. A 2 x 1 multiplexer can be used to implement a function of 2 variables, such as f(a,b) A 4 x 1 multiplexer can be used to implement a function of 3 variables, such as f(a,b,c) A 8 x 1 multiplexer can be used to implement a function of 4 variables, such as f(a,b,c,d) Figure 5.1: Block Schematic of 4x1 MUX Select Inputs Output S1 S0 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3 Table 5.1: Function Table of 4x1 MUX 17

18 Figure 5.2: Realization of 4x1 MUX using logic gates De-Multiplexers De-multiplexers or "De-muxes", are the exact opposite of the Multiplexers we saw in the previous tutorial in that they have one single input data line and then switch it to any one of their individual multiple output lines one at a time. The De-multiplexer converts the serial data signal at the input to a parallel data at its output lines. They are digital switches which connect data from one input source to one of n outputs. Usually implemented by using n-to-2n binary decoders where the decoder enable line is used for data input of the de-multiplexer. The figure below shows a de-multiplexer block diagram which has got s-bitswide select input, one b-bits-wide data input and n b-bits-wide outputs. Figure 5.3: Block Schematic of 1x4 De-MUX 18

19 Select Inputs Data Outputs S 1 S 0 Y 0 Y 1 Y 2 Y D in D in D in D in Table 5.2: Function Table of 1x4 De-MUX Figure 5.4: Realization of 1x4 De-MUX Lab Procedure MUX 1. Write the Functional table for 4: 1 MUX. 2. From the functional table, derive the logical expression for the output in terms of the data input and the select inputs. 3. Using the derived expression, implement 4: 1 Mux using logic gates and verify its functional table. 19

20 DEMUX 1. Write the functional table for 1: 4 De- MUX 2. From the functional table, derive the logical expression for the output in terms of the data input and the select inputs. 3. Using the derived expression, implement 1: 4 De- Mux using logic gates and verify its functional table. Pre-lab Questions 1. Multiplexer is also called a data selector. Why? 2. A certain multiplexer can switch one of 32 data inputs to its output. How many select inputs does this MUX have? 3. Implement a 4:1 using 2:1 MUX only? 4. Implement a 1:4 De-Mux using 1:2 De-mux only? 5. Implement a 2-input NAND function using suitable multiplexer? Post Lab questions 1. Draw the block diagram of 1x4 DeMUX using 1x2 DeMUX. Draw its truth table. 2. Implement a Full Adder using two 8-to-1 MUX. 3. Implement a Full Adder using two 4-to-1 MUX and one inverter. 4. Show how to make an 8-to-1 MUX using two 4-to-1 MUX. 5. Show how two 4-to-1 and one 2-to-1 MUX could be connected to form an 8-to-1 MUX. 6. Show how four 2-to-1 and one 4-to-1 MUX could be connected to form an 8-to-1 MUX. 7. Show how two 2-to-1 MUX (with no added gates) could be connected to form a 3-to-1 MUX. Input selection should be as follows. If AB=00, Select I0 If AB=01, Select I1 If AB=1X, Select I2 20

21 Lab 6: DESIGN OF CODE CONVERTERS Aim 1. To design and verify four bit Binary to Gray, Gray to Binary Number converter circuit. Hardware Requirement a. Equipments - Digital IC Trainer Kit b. Discrete Components 74LS86 Quad 2-Input EX-OR gate Theory The conversion from one code to another is common in digital systems. Sometimes the output of a system is used as the input to the other system. The availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code. The bit combination assigned to binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs and outputs. Gray code is a non-weighted code. The input variable are designated as B3,B2,B1,B0 and the output variable are designated as C3,C2,C1,Co.from the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable. Binary-to-Gray code conversion: 1. MSB Gray code = MSB Binary code 2. From left to right, add each adjacent pair of binary code bits to get the next Gray code bit. Discard carries Example: Consider the decimal number 68. (68)10 = ( )2 Binary code : Gray code : Gray-to-binary code conversion: 1. MSB binary code = MSB Gray code 2. Add each binary code bit generated to the Gray code bit in the next adjacent position. Discard carries Example: Consider the decimal number 68. (68)10 = ( )2 Gray code : Binary code :

22 BINARY-TO-GRAY CODE CONVERSION Decimal Binary code Gray code D C B A G3 G2 G1 G Table 6.1: Binary to Gray code conversion The design equations are G0 = B A G1 = C B G2 = D C G3 = D Figure 6.1: Realization of Binary-to-Gray Code Converter 22

23 Gray code Binary code G3 G2 G1 G0 D C B A Table 6.2: Gray-to-Binary code conversion The logic equations for Gray to binary code conversion A = (G3 G2) (G1 G0) B = (G3 G2) G1 C = G3 G2 D = G3 Figure 6.2: Realization of Gray-to-Binary Code Converter 23

24 Lab Procedure 1. Using the derived expression, implement binary to gray and Gray to binary code convertor using logic gates and verify its functional table. 2. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are given at respective pins and outputs B0, B1, B2 and B3 are taken for all the 16 combinations of inputs. 3. In the case of binary to gray code conversion, the inputs B0, B1, B2 and B3 are given at respective pins and outputs G0, G1, G2 and G3 are taken for all the 16 combinations of inputs. Prelab 1. What do you mean by code conversion? What are the applications of code conversion? 2. What are the advantages of gray code? 3. Determine the Gray code for (a) 37 and (b) Derive the Boolean expression for four bit Excess 3 code to Binary code converter 5. Derive the Boolean expression for four bit BCD to Gray code converter 6. Convert gray code into its binary equivalent. Post lab 1. Design the BCD to Binary code converter circuit 24

25 Lab: 7 Combination Circuits using standard ICs Aim To implement the combinational circuits using standard ICs. Apparatus Required Procedure 1. IC :1 Multiplexer 2. IC74LS138-3:8 Decoder 3. IC trainer kit 4. Connecting wires IC :1 Multiplexer IC. IC Description: is a 8 line-to-1 line multiplexer. It has the schematic representation shown in Fig 1. Selection lines S2, S1 and S0 select the particular input to be multiplexed and applied to the output. Strobe S acts as an enable signal. If strobe =1, the chip is disabled and output y = 0. If strobe = 0 then the chip is enabled and functions as a multiplexer. Table 1 shows the multiplex function of in terms of select lines. Fig1. IC74151 Pin Description Table1. Multiplexer Function 3x8 Decoder using IC74LS138. Decoder is the combinational circuit which contains n input lines to 2 n output lines. The decoder is used for converting the binary code into the octal code. The IC74138 is the 3*8 decoder which contains three inputs and eight outputs and also three enables out of them two are active low and one is active high. Decoders are used in the circuit where required to get more outputs than that of the inputs which also used in the chip designing process for reducing the IC chip area. 25

26 Prelab Questions 1. What is meant by combinational circuits? 2. What are the applications of Multiplexer? 3. What are the difference between Decoder and Demultiplexer? 4. Give some examples for standard combinational circuit ICs. Post Lab Questions 1. Implement F(W,X,Y,Z) = Σm(1,2,5,7,9,12,15) using suitable IC Design 4-bit parity generator using Multiplexer IC. 3. Implement the function F(A,B,C,D) = m(1,3,4,11,12,13,14,15) using MUX. Draw its truth table and its logic symbol. 4. Realize the SOP expression y=σ m (1,4,5) using 74LS138 decoder. 5. Realize the POS expression y= ΠM (0,2,3,6,7) using 74LS138 decoder. 6. Use an MSI adder (74LS183) to convert BCD to Excess-3 code. 7. Cascade two 4-bit comparators 74LS85 to realize an 8-bit comparator. 26

27 Lab 8: Design of 3-bit Synchronous Counters Aim To design and verify the truth table for 3-bit synchronous up/down counter. Hardware Requirement Equipment : Digital IC Trainer Kit Discrete Components : IC 7473 Dual JK Flip Flop 74LS08 Quad 2 input AND gate 74LS32Quad 2 input OR gate 74LS04 Hex 1 input NOT gate Theory Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The number of flip flops used and how they are connected determine the number of states and the sequence of the states that the counter goes through in each complete cycle. Counters can be classified into two broad categories according to the way they are clocked: a. Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse, and then each successive flip -flop is clocked by the Q or Q' output of the previous flip -flop. b. Synchronous Counters - all memory elements are simultaneously triggered by the same clock. Synchronous Counters In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0 are connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1. After the 3rd clock pulse both outputs of FF0 and FF1 are HIGH. The positive edge of the 4th clock pulse will cause FF2 to change its state due to the AND gate. PRESET HIGH J CLK K PRE 7476 CLR Q Q J CLK K PRE 7476 CLR Q Q 7408 J CLK K PRE 7476 CLR Q Q CLK CLEAR QA Figure 8.1: Logic diagram of 3-bit Synchronous counter QB QC 27

28 CLK QA QB QC Figure 8.2: Timing Diagram of 3-bit Counter The most important advantage of synchronous counters is that there is no cumulative time delay because all flip -flops are triggered in parallel. Thus, the maximum operating frequency for this counter will be significantly higher than for the corresponding ripple counter. 8.4 Lab Procedure 1. Construct the logic circuit as shown in figure Apply clock pulses. 3. Verify the count sequence as given in figure 8.2. PreLab questions 1. How does synchronous counter differ from asynchronous counter? 2. What is the difference between the latch, flip-flop and master slave Flip-flop? 3. A 4-bit up/down binary counter is in the DOWN mode and in the 1010 state. On the next clock pulse, to what state does the counter go? 4. How many flip-flops do you require to design Mod-7 counter. 5. Give the Transition table and excitation table of JK Flip flop. PostLab questions 1. Configure the given counter to work as a down counter, and verify the operation using simulation. 2. Construct a 3-bit up/down synchronous counter as shown below, and verify the operation using simulation. 3. Deign a 3-bit Up/Down Gray Code Counter using D Flip-flop 28

29 4. What are the differences in Master-Slave JK Flip-flop, a +ve edge triggered JK Flip-flop and a -ve edge triggered JK Flip-flop. 5. When does a JK Flip-flop act as a divide by- 2 circuits? 6. What are the advantages of an edge-triggered Flip-flop over a level-triggered device? 7. A negative edge triggered Flip-flop has the following timing parameters tsu=15ns, thold=5ns, minimum positive clock pulse width=2.sketch the clock, data input and data output waveforms showing these timing relationship. 8. A 4-bit binary synchronous counter uses Flip-flops with propagation delay time of 25ns each. The maximum possible time required for change state will be A 4-bit pre-settable up-counter has preset input 0101.The preset operation takes place as soon as the counter becomes maximum i.e 1111.The modulus of this counter a. Convert D Flip-flop to JK Flip-flop b. Convert T Flip-flop to D Flip-flop 29

30 Lab 9: Design of 3-bit Ripple Counters Aim To design and verify the timing diagram of 3 bit Ripple Counter Apparatus Required a. Equipments - Digital IC Trainer Kit b. Discrete Components - IC7473 Dual JK Flip-flop Theory Asynchronous Counter is sequential circuit that is used to count the number of clock input signal. The output of one flip flop is given as a clock input to another flip-flop, so it is called as Serial Counter. A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops. The MOD of the ripple counter or asynchronous counter is 2 n if n flip-flops are used. A three-bit asynchronous counter is shown on the below figure. The external clock is connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes state at the falling edge of each clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of FF0 similarly FF2 changes only when triggered by the falling edge of the Q output of FF1. Because of the inherent propagation delay through a flip-flop, the transition of the input clock pulse and a transition of the Q output of FF0 can never occur at exactly the same time. Therefore, the flip-flops cannot be triggered simultaneously, producing an asynchronous operation. Usually, all the CLEAR inputs are connected together, so that a single pulse can clear all the flip-flops before counting starts. The clock pulse fed into FF0 is rippled through the other counters after propagation delays, like a ripple on water, hence the name Ripple Counter. PRESET HIGH CLK J CLK PRE 7476 Q J CLK PRE 7476 Q J CLK PRE 7476 Q K Q K Q K Q CLR CLR CLR CLEAR QA QB QC Figure 9.1: 3-bit Asynchronous Counter 30

31 CLK QA QB QC Figure 9.2: Count Sequence Prelab questions 1. What do you mean by Glitch? 2. How many flip-flops are required to produce a divide-by-64 device? 3. Why Asynchronous counter is called as Ripple Counter? 4. What do you mean by synchronous reset and asynchronous reset? 5. What is the use of Preset input? 6. What is use of Ring and Johnson s Counter? Lab Procedure 1. Construct the logic circuit as shown in Figure Verify the count sequence as given in figure 9.2. Postlab questions 1. Design a 4-bit frequency divider. 2. Design a sequential circuit that is used to generate the timing signals with a combination of Shift register and a decoder. 3. What is state table? 4. How many states a 6-bit ripple counter can have? 5. A 4-bit binary ripple counter uses Flip-flops with propagation delay time of 25ns each. The maximum possible time required for change state will be How many Flip-flops a decade counter will require? 7. What is the maximum number that can be obtained by a ripple counter using 5 Flip-flop? 31

32 Lab 10: Design of MOD-N counters Aim The purpose of this experiment is to introduce the design of Mod-N Counter and to implement it using suitable Flip-flops. Hardware Requirement Equipment : Digital IC Trainer Kit Discrete Components : IC 7473 Dual JK Flip Flop IC 7400 NAND Gate Theory Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The number of flip flops used and how they are connected determine the number of states and the sequence of the states that the counter goes through in each complete cycle. Counters can be classified into two broad categories according to the way they are clocked: 1. Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse, and then each successive flip -flop is clocked by the Q or Q' output of the previous flip -flop. 2. Synchronous Counters - all memory elements are simultaneously triggered by the same clock. A mod N counter is a counter that has N states. Its output frequency is f/n. A counter which is reset at the tenth clock pulse is called Mod 10 counter or Divide by 10 counter. The circuit diagram of Mod 10 counter is shown in the figure. This counter contains three JKMS flip-flop. HIGH PRESET J PRE Q J PRE Q J PRE Q J PRE Q 7400 CLK CLK 7476 CLK 7476 CLK 7476 CLK 7476 K Q K Q K Q K Q CLR CLR CLR CLR QA QB QC QD Figure 10.1: Mod 10 Asynchronous Counter A 3 bit binary counter is normally counting from 000 to 111. The actual output of a 3 bit binary counter at the tenth clock pulse is A two input NAND gate is used to make a Mod 10 counter. The outputs QB and QD are connected to the input of the give NAND gate, and its output is connected to the RESET terminal of the counter. Hence, the counter is reset at the tenth clock pulse, which produces the output QD, QC, QB, QA as

33 CLK QA QB QC QD Figure 10.2: Timing Diagram Lab Procedure 1. Connections are made as per circuit diagram. 2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA, QB & QC, QD. 3. Timing diagram is verified. Prelab questions 1. Which flip-flop is suitable for counter? Why? 2. Draw the timing diagrams for mod 6 counter.. PostLab questions 1. Draw the state Diagram, state table and Timing Diagram of a 2-bit synchronous counter. 2. Design a modulus seven synchronous counter using D flip-flop. 3. A mod-5 synchronous counter is designed using JK Flip-flops. What is the number of counts it will skip? 4. The output frequency of a Modulus-16 counter, clocked from a 20kHz clock input signal is

34 Lab 11: Design of Shift Registers and Shift Register Counters Aim The purpose of this experiment is to introduce the design of Shift Registers. The student should also be able to design n-bit shift register. Hardware Requirement a. Equipments - Digital IC Trainer Kit b. Discrete Components - IC7474 Dual JK Flip-flop Theory Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop. Most of the registers possess no characteristic internal sequence of states. All the flip-flops are driven by a common clock, and all are set or reset simultaneously. The basic types of shift registers are 1. Serial-In-Serial-Out 2. Serial-In Parallel-Out 3. Parallel-In Serial-Out 4. Parallel-In Parallel-Out 5. Bidirectional shift registers Serial-In-Serial-Out Shift Registers A basic four-bit shift register can be constructed using four D flip-flops, as shown below. The operation of the circuit is as follows. The register is first cleared, forcing all four outputs to zero. The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0). During each clock pulse, one bit is transmitted from left to right. Assume a data word to be The least significant bit of the data has to be shifted through the register from FF0 to FF3. Assume a data word to be The least significant bit of the data has to be shifted through the register from FF0 to FF3. 34

35 Preset Din D PR Q D PR Q D PR Q Dout 7474 CLK CLK 7474 CLK 7474 CLR CLR CLR Clear CLK Figure 11.1: SISO shift register Figure 11.2: Basic data movement through a shift register Parallel-In Parallel-Out Shift Registers For parallel in - parallel out shift registers, all data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. The following circuit is a four-bit parallel in - parallel out shift register constructed by D flip-flops. The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the data at the D inputs appear at the corresponding Q outputs simultaneously. A B C Preset D PR Q D PR Q D PR Q 7474 CLK CLK 7474 CLK 7474 CLR CLR CLR Clear CLK QA QB QC Figure 11.3: PIPO shift register 35

36 Shift Register Counter Two of the most common types of shift register counters are Ring counter and the Johnson counter. They are basically shift registers with the serial outputs connected back to the serial inputs in order to produce particular sequences. These registers are classified as counters because they exhibit a specified sequence of states. Johnson counters are a variation of standard ring counters, with the inverted output of the last stage fed back to the input of the first stage. They are also known as twisted ring counters. An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to be a mod- 2n counter. The circuit below shows a 4-bit Johnson counter. The state sequence for the counter is given in the table as well as the animation on the left. PRESET D PRE Q D PRE Q D PRE Q CLK 7474 CLK 7474 CLK 7474 CLR Q CLR Q CLR Q CLK CLEAR QA QB QC Figure 11.3: Johnson Counter Figure 11.4: State table of Johnson Counter Prelab questions 1. Redraw the above logic diagrams using JK flip-flops. 2. How many flip-flops are required to store the data 1001? 3. How many clock pulses are required to enter a byte of data serially into an 8-bit shift register? 4. Define shift register counters. 5. What is bidirectional and unidirectional shift register? 6. Explain the function of SHIFT/LOAD input in PISO shift register. 36

37 PostLab questions 1. Draw the Logic diagram of Universal shift register. 2. Write the applications of Shift registers. 3. Draw the State Table and Block diagram of a Serial Adder. 4. How many Flip-flops are required for mod-16 ring counter? 5. How many Flip-flops are required for mod-12 Johnson counter? 37

38 Aim Lab 12: Implementation of sequential logic functions using standard IC s To implement and verify the functional table of sequential logic functions using IC. Hardware Requirement a. Equipments - Digital IC Trainer Kit b. Discrete Components - 74LS194-74LS90 Theory Verify 4-bit Universal Shift Register using IC74LS194. The register capable of shifting both right and left is called a bidirectional shift register. The SN54/74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. Like a parallel register it can load and transmit data in parallel. Like shift registers it can load and transmit data in serial fashions, through left shifts or right shifts. In addition, the universal shift register can combine the capabilities of both parallel and shift registers to accomplish tasks that neither basic type of register can perform on its own. For instance, on a particular job a universal register can load data in series (e.g. through a sequence of left shifts) and then transmit/output data in parallel. Universal shift registers, as all other types of registers, are used in computers as memory elements. Although other types of memory devices are used for the efficient storage of very large volume of data, from a digital system perspective when we say computer memory we mean registers. In fact, all the operations in a digital system are performed on registers. Examples of such operations include multiplication, division, and data transfer. This device can operate in four distinct modes, determined by the values at the control inputs S1 and S0: hold data (S1, S0 = 00), shift right Q0 toward Q3 (S1, S0 = 01), shift left Q3 toward Q0 (S1, S0 = 10), and parallel load from the 0,1, 2, 3 inputs (S1, S0 = 11). In addition, the register has an active low (asynchronous) reset signal CLR and two serial shift inputs DSL and DSR. The parallel load takes place when S1 and S0 are both high and a rising edge arrives at the clock input. At the same time, the value at input P0 replaces the contents of the Q0 flip-flop, P1 replaces Q1, and so on. This is called a synchronous load because it takes place in response to a clock event. S1 low and S0 high indicate a right shift. On the rising edge of the clock, the value on the DSR input replaces Q0, Q0 replaces Q1, Q1 replaces Q2, and Q2 replaces Q3. The old value at Q3 is lost. We can construct a right circular shifter by wiring the Q4 output to the DSR input. S1 high and S0 low specify a left shift. In this case, DSL replaces Q3, Q3 replaces Q2, Q2 replaces Q1, and Q1 replaces Q0, all on the rising edge of the clock. We can construct a left circular shifter by wiring Q0 to DSL. 38

39 S1 and S0 both low tell the shift register to hold its state. The outputs do not change even though the clock signal undergoes a low-to-high transition. A universal shift register is an integrated logic circuit that can transfer data in three different modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it can load and transmit data in serial fashions, through left shifts or right shifts. In addition, the universal shift register can combine the capabilities of both parallel and shift registers to accomplish tasks that neither basic type of register can perform on its own. For instance, on a particular job a universal register can load data in series (e.g. through a sequence of left shifts) and then transmit/output data in parallel. Universal shift registers, as all other types of registers, are used in computers as memory elements. Although other types of memory devices are used for the efficient storage of very large volume of data, from a digital system perspective when we say computer memory we mean registers. In fact, all the operations in a digital system are performed on registers. Examples of such operations include multiplication, division, and data transfer. Figure 12.1: Pin diagram of IC74194 Figure 12.2: Function table of IC

40 Figure 12.3: Internal Schematic of IC74194 Figure 12.4: Waveforms of IC

41 Verify Decade Counter using IC74LS90. IC 7490 is a decade counter which drives input by 10 and provides BCD outputs 0 to 9, also called as decimal counter. These counters comprise of a divide-by 2 and divide-by 5 counters. To use as decade counter we have to cascade divide-by 2 and divide-by 5. Outputs Q0 to Q3 are BCD outputs, inputs CP 1 and CP 0 are clock inputs to the, divide-by 2 and divide-by 5 counters respectively. MR1 and MR2 are the reset inputs, MS1 and MS2 are the set inputs to the counter, and The CP 1 input must be externally connected to the Q0 output. Figure 12.5: Pin diagram of IC74LS90 Figure 12.6: Internal Schematic of IC74LS90 41

42 RESET/SET INPUTS OUTPUTS MR 1 MR 2 MS 1 MS 2 Q 0 Q 1 Q 2 Q 3 H H L X L L L L H H X L L L L L X X H H H L L H L X L X Count X L X L Count L X X L Count X L L X Count Table 12.1: Function table of IC 74LS90 H=High Voltage Level L=Low Voltage Level X=Don t Care Lab procedure 1. Connect the 74194and 74LS90 to the breadboard with appropriate inputs and outputs. 2. Verify the functionality of shift register and counter. 3. Verify the Truth Table and observe the outputs. Prelab questions 1. What is Universal shift Register? 2. What is the necessity for sequence generation? 3. What are the operations performed by a universal shift register? 4. Explain how to convert serial data to parallel and parallel data to serial. 5. What type of register is needed? 6. What is the Difference b/w shift register and universal shift register? 42

43 Post lab questions 1. From which of the outputs Q can we get the data serial output from the register? And how many pulses do we need? 2. Use two ICs of the to build an 8-bit bidirectional register, and verify the functional table for the resultant register. 3. Connect the to the breadboard with appropriate input and outputs and Fill the timing diagram given below. 43

44 13: Simulation Experiments using Logisim Aim To understand how to design and debug combinatorial circuits using the Logisim logic simulator. Procedure Start up Logisim and create a new circuit. Save this file as lab13part1.circ. Then, create a circuit given below. Square boxes are input pins. Their values are being used to compute a value. Circle boxes are output pins, as their values are being computed by the circuit and output to circuitry that wants the result of the circuit. Triangles are not-gates, as they invert whatever their input is. Green lines are wires. Bright green wires are 'on' (true, 1). Dull green wires are 'off' (false, 0). Blue wires are unconnected. We often have blue lines (e.g., when a 5-input AND gate only has 2 inputs connected, the blue input will be ignored). 2) Find truth table values by manually toggling the input values and examining the output values. This is done in Logisim by selecting the hand icon and then clicking on each input. Fill in the rest of the truth table for the circuit manually: A B C Y X

45 3) Next, generate the complete truth table with Logisim by selecting Project->Analyze Circuit from the Project menu and then viewing the table tab. Compare it with the filled table. 4) Save your circuit (File->Save) as r4.circ in your R4 directory. 5) Build a circuit that implements the truth table below, and verify it by checking against the truth table made with Logisim. What kind of circuit does this represent? A B W X Y Z

46 The Guide to Being a Logisim User Logisim is an educational tool for designing and simulating digital logic circuits. With its simple toolbar interface and simulation of circuits as they are built, it is simple enough to facilitate learning the most basic concepts related to logic circuits. With the capacity to build larger circuits from smaller subcircuits, and to draw bundles of wires with a single mouse drag, Logisim can be used (and is used) to design and simulate entire CPUs for educational purposes. Students at colleges and universities around the world use Logisim for a variety of purposes, including: A module in general-education computer science surveys A unit in sophomore-level computer organization courses Over a full semester in upper-division computer architecture courses The Guide to Being a Logisim User, which you are reading now, is the official reference for Logisim's features. Its first part is a sequence of sections introducing the major parts of Logisim. These sections are written so that they can be read ``cover to cover'' to learn about all of the most important features of Logisim. Beginner's tutorial Libraries and attributes Subcircuits Wire bundles Combinational analysis The remaining sections are a motley bunch of reference materials and explanations of some of the lesser corners of Logisim. Menu reference Memory components

47 Logging Application preferences Project options Value propagation JAR libraries About the program Beginner's tutorial Next: Step 0: Orienting yourself Welcome to Logisim! Logisim allows you to design and simulate digital circuits. It is intended as an educational tool, to help you learn how circuits work. To practice using Logisim, let's build a XOR circuit - that is, a circuit that takes two inputs (which we'll call x and y) and outputs 1 if the inputs are the same and 0 if they are different. The following truth table illustrates. We might design such a circuit on paper. But just because it's on paper doesn't mean it's right. To verify our work, we'll draw it in Logisim and test it. As an added bonus, we'll get a circuit that's looks nicer than what you probably would draw by hand. Step 0: Orienting yourself Step 1: Adding gates Step 2: Adding wires Step 3: Adding text Step 4: Testing your circuit Enjoy your circuit-building!

48 Next: Step 2: Adding wires Step 1: Adding gates Recall that we're trying to build the following circuit in Logisim. Building a circuit is easiest by inserting the gates first as a sort of skeleton for connecting wires into the circuit later. The first thing we're going to do is to add the two AND gates. Click on the AND tool in the toolbar (, the next-to-last tool listed). Then click in the editing area where you want the AND gates to go. Be sure to leave plenty of room for stuff on the left. Notice the five dots on the left side of the AND gate. These are spots where wires can be attached. It happens that we'll just use two of them for our XOR circuit; but for other circuits, you may find that having more than two wires going to an AND gate is useful. Now add the other gates. First click on the OR tool ( ); then click where you want it. And select the NOT tool ( ) and put those two gates into the canvas.

49 I left a little space between the NOT gates and the AND gates; if you want to, though, you can put them up against each other and save yourself the effort of drawing a wire in later. Now we want to add the two inputs x and y into the diagram. Select the input pin ( ), and place the pins down. You should also place an output pin ( ) next to the OR gate's output. (Again, though I'm leaving a bit of space between the OR gate and the output pin, you might choose to place them right next to each other.) If you decide you don't like where you placed something, then you can right-click (or control-click) anything in the canvas to view a pop-up menu. Choose Delete. You can also rearrange things using the select tool ( ). Next: Step 2: Adding wires Next: Step 3: Adding text

50 Step 2: Adding wires After you have all the components blocked out on the canvas, you're ready to start adding wires. Select the wiring tool ( ). Then start dragging from one position to another in the canvas area, and a wire will start to appear between the two points. Wires in Logisim must be horizontal or vertical. To connect the upper input to the NOT gate and the AND gate, then, I added three different wires. Logisim automatically connects wires to the gates and to each other. This includes automatically drawing the circle at a T T intersection as above, indicating that the wires are connected. As you draw wires, you may see some blue or gray wires. Blue in Logisim indicates that the value at that point is ``unknown'', and gray indicates that the wire is not connected to anything. This is not a big deal temporarily. But by the time you finish your circuit, none of your wires should be blue or gray. (The unconnected legs of the OR gate will still be blue: That's fine.) If you do have a blue or a gray wire after you think everything ought to be connected, then something is going wrong. It's important that you connect wires to the right places. Logisim draws little dots on the components to indicate where wires ought to connect. As you proceed, you'll see the dots turn from blue to light or dark green. Once you have all the wires connected, all of the wires you inserted will themselves be light or dark green.

51 Next: Step 3: Adding text Next: Step 4: Testing your circuit Step 3: Adding text Adding text to the circuit isn't necessary to make it work; but if you want to show your circuit to somebody (like a teacher), then some labels help to to communicate the purpose of the different pieces of your circuit. Select the text tool ( ). You can click on an input pin and start typing to give it a label. (It's better to click directly on the input pin than to click where you want the text to go, because then the label will move with the pin.) You can do the same for the output pin. Or you could just click any old place and start typing to put a label anywhere else. Next: Step 4: Testing your circuit Next: User's Guide

52 Step 4: Testing your circuit Our final step is to test our circuit to ensure that it really does what we intended. Logisim is already simulating the circuit. Let's look again at where we were. Note that the input pins both contain 0s; and so does the output pin. This already tells us that the circuit already computes a 0 when both inputs are 0. Now to try another combination of inputs. Select the poke tool ( ) and start poking the inputs by clicking on them. Each time you poke an input, its value will toggle. For example, we might first poke the bottom input. When you change the input value, Logisim will show you what values travel down the wires by drawing them light green to indicate a 1 value or dark green (almost black) to indicate a 0 value. You can also see that the output value has changed to 1. So far, we have tested the first two rows of our truth table, and the outputs (0 and 1) match the desired outputs.

53 By poking the switches through different combinations, we can verify the other two rows. If they all match, then we're done: The circuit works! To archive your completed work, you might want to save or print your circuit. The File menu allows this, and of course it also allows you to exit Logisim. But why quit now? Now that you are finished with tutorial, you can experiment with Logisim by building your own circuits. If you want to build circuits with more sophisticated features, then you should navigate through the rest of the help system to see what else you can do. Logisim is a powerful program, allowing you to build up and test huge circuits; this step-by-step process just scratches the surface. Next: User's Guide Libraries and Attributes In this section, we'll examine how to use the other two major regions of the Logisim window, the explorer pane and the attribute table. The explorer pane The attribute table Tool and component attributes Next: The explorer pane.

54 The explorer pane Libraries contain components that can be dropped into circuits. They are displayed as folders in the explorer pane; to access a library's components, you have only to double-click the corresponding folder. Below, I have opened the Gates library and selected the NAND tool from it. You can see that Logisim now stands ready to add NAND gates into the circuit. If you look through the choices in the Gates library, you'll notice that there was no need for us to develop a XOR circuit earlier: It's built into Logisim. When you create a project, it automatically includes the Base and Gates libraries. But Logisim includes many other libraries, too: To load one, go to the Project menu, in the Load Library submenu, and choose Built-in Library... A dialog box will appear allowing you to choose which libraries you want to add. If you choose Plexers, for example, then you will be able to add multiplexers, demultiplexers, and decoders. You can load as many libraries as you like. In the Load Library submenu, you can see that Logisim has three categories of libraries. Built-in libraries are libraries that are distributed with Logisim. These are documented in the Library Reference. Logisim libraries are projects built within Logisim and saved to the disk. You can develop a set of circuits in a single project (as described in the Subcircuits section of this guide) and then use that set of circuits as a library for another projects. JAR libraries are libraries that are developed in Java but not distributed with Logisim. You can download JAR libraries that others have written, or you can write your own as described in the JAR Libraries section of this guide. Developing a JAR library is much more difficult than developing a Logisim library, but the components can be much fancier, including things like attributes and interaction with the user. The built-in libraries (other than Base)

55 were written using the same API as JAR libraries can use, so they aptly demonstrate the range of functionality that the JAR libraries can support. When loading a JAR library, Logisim will prompt you to select the JAR file, and then it will prompt you to type a class name. This class name should be provided by whoever distributed the JAR file to you. To remove a library, choose Unload Library... from the Project menu. Logisim will prevent you from unloading libraries that contain components used in a circuit, that appear in the toolbar, or that are mapped to a mouse button. Incidentally, a library technically contains tools, not components. Thus, in the Base library you'll find the Poke Tool ( ), the Select Tool ( ), and other tools that don't correspond directly to individual components. Most libraries, though, contain only tools for adding individual components; all built-in libraries other than the Base library are like this. Next: The attribute table. The attribute table Many components have attributes, which are properties for configuring how the component behaves or appears. The attribute table is for viewing and displaying a component's attribute values. To select which component's attributes you wish to view, click the component using the Select tool ( ). (You can also right-click (or control-click) the component and choose Show Attributes from the popup menu. Also, manipulating a component via the Poke tool ( ) or the Text tool ( ) will display that component's attributes.) The below screen shot demonstrates what things look like after selecting the upper input of our XOR circuit and scrolling down to view the Label Font attribute.

56 Note the pale teal (i.e., light blue) oval surrounding the pin, called a halo: This indicates whose attributes are displayed in the attribute table. To modify an attribute value, click on the value. The interface for modifying the attribute will depend on which attribute you are changing; in the case of the Label Font attribute, a dialog box will appear for selecting the new font; but some attributes (like Label) will allow you to edit the value as a text field, while others (like Label Location) will display a drop-down menu from which to select the value. Each component type has a different set of attributes; to learn what they mean, go to the relevant documentation in the Library Reference. Some components have attribute values that cannot be changed. One example of this is the AND gate's Gate Size attribute: As soon as you create an AND gate, is size is fixed. If you want an AND gate of a different size, then you'll need to change the attributes for the tool, which we'll discuss next. Next: Tool attributes. Tool attributes Every tool for adding components to a circuit also has a set of attributes, which are imparted to the components created by the tool, although the components' attributes may be changed later without affecting the tool's attributes. When you select a tool, Logisim will change the attribute table to display that tool's attributes. For example, suppose we want to create smaller AND gates. We've already seen that an AND gate's Gate Size attribute is not editable. But the Gate Size attribute is editable for the AND gate tool: To view and edit this attribute, click the tool's icon in the toolbar (or the explorer pane), and change its Gate Size attribute.

57 Now, we can delete the two existing AND gates and add two new AND gates in their place. This time, they will be narrow. (If you chose to reduce the number of inputs to 3, the AND gate would not have vertical extension on the left side. But you'd also have to rewire the circuit so that the wires hit the AND gate's left side.) With some tools, the icon reflects some of the attributes' values. One example of this is with the Pin tool, whose icon faces the same way as its Facing attribute says. The tools in the toolbar each have a separate attribute set from the corresponding tools in the explorer pane. Thus, even though we changed the toolbar's AND tool to create narrow AND gates, the AND tool in the Gates library will still create wide AND gates unless you change its attributes too. In fact, the input pin and output pin tools in the default toolbar are both instances of the Base library's Pin tool, but the three attribute sets are different. The icon for the Pin tool is drawn as a circle or a square depending on the value of its ``Output?'' attribute. Logisim provides a handy shortcut for changing the Facing attribute that controls the direction in which many components face: Typing an arrow key while that tool is selected automatically changes the direction of the component. Next: User's Guide.

58 Subcircuits As you build circuits that are more and more sophisticated, you will want to build smaller circuits that you can use multiple times in larger circuits. In Logisim, such a smaller circuit that is used in a larger circuit is called a subcircuit. If you're familiar with computer programming, you're familiar with the subprogram concept (called subroutines, functions, or methods in different languages). The subcircuit concept is analogous to the concept in computer programming, and it is used for the same purposes: To break a large job into bite-sized pieces, to save the effort of defining the same concept multiple times, and to facilitate debugging. Creating circuits Using subcircuits Debugging subcircuits Logisim libraries Next: Creating circuits. Creating circuits Every Logisim project is actually a library of circuits. In its simplest form, each project has only one circuit (called "main" by default), but it is easy to add more: Select Add Circuit... from the Project menu, and type any name you like for the new circuit you want to create. Suppose we want to build a 1x2 multiplexer named "1x2 MUX." After adding the circuit, Logisim will look like this. In the explorer pane, you can now see that the project now contains two circuits, "main", and "1x2 MUX." Logisim draws a magnifying glass over the icon of the circuit currently being viewed; the current circuit name also appears in the window's title bar.

59 After editing the circuit to appear like a 1x2 multiplexer, we might end up with the following circuit. Next: Using subcircuits. Using subcircuits Now suppose we want to build a 2x4 multiplexer using instances of our 1x2 multiplexer. Of course, we would first create a new circuit, which we'll call "2x4 MUX." To add 1x2 multiplexers into our circuit, we click the 1x2 MUX circuit once in the explorer pane to select it as a tool, and then we can add copies of it, represented as boxes, by clicking within the canvas. If you click the 1x2 MUX circuit twice in the explorer pane, then the window would switch to editing the 1x2 MUX circuit instead. After building up the circuit, we end up with the following.

60 Our circuit for a 2x4 multiplexer uses three copies of the 1x2 multiplexer, each drawn as a box with pins along the side. The pins on this box correspond to the input and output pins in the 1x2 MUX circuit. The two pins on the west side of the box correspond to the two pins that face east in the 1x2 MUX circuit; the pin on the box's east side corresponds to the 1x2 MUX's west-facing pin (which happens to be an output pin); and the pin on the box's south side corresponds to the 1x2 MUX's northfacing pin. The order of the two pins on the box's west side correspond to the same top-down ordering that apears in the subcircuit. (If there were several pins on the box's north or south side, they would correspond to the same left-right order in the subcircuit.) If the pins in the subcircuit's layout have labels associated with them, then Logisim will display that label in a tip (that is, a temporary text box) when the user hovers the mouse over the corresponding location of the subcircuit component. (If you find these tips irritating, you can disable them via the Project Options window's Canvas tab.) Several other components will display these tips, too: For some of the pins of a builtin flip-flop, for example, hovering over it explains what that pin does. Incidentally, every pin to a circuit must be either an input or an output. Many manufactured chips have pins that behave as an input in some situations and as an output in others; you cannot construct such chips within Logisim.

61 Logisim will maintain different state information for all subcircuits appearing in a circuit. For example, if a circuit contains a flip-flop, and that circuit is used as a subcircuit several times, then each subcircuit's flip-flop will have its own value when simulating the larger circuit. Now that we have the 2x4 multiplexer defined, we can now use it in other circuits. Logisim has no limits on how deeply circuits can be nested - though it will object to nesting circuits within themselves! Note: There's nothing wrong with editing a circuit that is being used as a subcircuit; in fact, this is quite common. Be aware, though, that any changes to a circuit's pins (adding, deleting, or moving them) will rearrange them also in the containing circuit. Thus, if you change any pins in a circuit, you will also need to edit any circuits using it as a subcircuit. Next: Debugging subcircuits. Debugging subcircuits As you test larger circuits, you will likely find bugs. To nail down what's going wrong, exploring what's going on in the subcircuits while running the overall circuit can help. From viewing the overall circuit, you can do this by bringing up the subcircuit's popup menu (right-click or control-click its box). Then choose the View option. After choosing this, the view will switch to the subcircuit.

62 Notice that the pins' values in the subcircuit match the values being sent to them in its containing circuit. While in the subcircuit, you can change it however you want; any changes to pins' values will be propagated within the containing circuit. (If you attempt to toggle a pin using the Poke Tool, Logisim will pop up a dialog box asking whether you want to create a new state; responding Yes will divorce the state viewed with the subcircuit from the outer circuit's state, while responding No will cancel the toggle request.) Once you have completed viewing and/or editing the parent circuit either by doubleclicking it in the explorer pane, or via the Go Out To State submenu of the Simulate menu. Next: Logisim libraries. Logisim libraries Every Logisim project is automatically a library that can be loaded into other Logisim projects: Just save it into a file and then load the library within another project. All of the circuits defined in the first project will then be available as subcircuits for the second. This feature allows you to reuse common components across projects and to share favorite components with your friends (or students). Each project has a designated "main circuit," which can be changed to refer to the current circuit via the Set As Main Circuit option in the Project menu. The only significance of this is that the main circuit is the one that is displayed when you first open the project. The default name of the circuit in a newly created file ("main") has no significance at all, and you can feel free to delete or rename that circuit. With a loaded Logisim library, you are allowed to view circuits and manipulate their states, but Logisim will prevent you from altering them. If you want to alter a circuit in a loaded Logisim library, then you need to open it separately within Logisim. As soon as you save it, the other project should

63 automatically load the modified version immediately; but if it does not, you can rightclick the library folder in the explorer pane and select Reload Library. Next: User's Guide. Wire bundles In simple Logisim circuits, most wires carry only one bit; but Logisim also allows you to create wires that bundle together multiple bits. The number of bits traveling along a wire is that wire's bit width. Creating bundles Splitters Wire colors Next: Creating bundles. Creating bundles Every input and output on every component in the circuit has a bit width associated with it. Many of Logisim's built-in components include attributes allowing you to customize the bit widths of their inputs and outputs. The below screen shot illustrates a simple circuit for finding the bitwise AND of two three-bit inputs; each pin has its Bit Width attribute customized for dealing with threebit data, as with the pictured AND gate attributes. Notice that the input and output pins are drawn with three bits, and the output is the bitwise AND of the inputs. For components, all inputs and outputs must have their bit widths defined. In contrast, a wire's bit width is undefined: Instead, the wire's width adapts to the components to which it is attached. If a wire connects two components demanding different bit widths, Logisim will complain of ``Incompatible widths'' and indicate the offending locations in orange. In the below, the output pin's Bit Width attribute has been

64 changed to 1, and so Logisim complains that the wire cannot connect a three-bit value to a one-bit value. Wires that connect incompatible locations (drawn in orange) do not carry values. For single-bit wires, you can see at a glance what value it is carrying because Logisim colors the wire light or dark green depending the value. It does not display values for multi-bit wires: They are simply black. You can, though, probe a wire by clicking it using the poke tool ( ). This probing feature is helpful for debugging circuits using wire bundles. Next: Splitters. Splitters When you work with multi-bit values, you will often want to route different bits in different directions. The Base library's splitter tool ( allows you to accomplish this. For example, suppose we want to build a circuit taking an eight-bit input and outputting the AND of its two nibbles (the upper four bits and the lower four bits). We will have an eight-bit value coming from the input pin, and we want to split that into two four-bit values. In the below circuit, we have used a splitter to accomplish this.

65 In this example, the splitter happens to actually split an incoming value into multiple outgoing values. But splitters can also combine multiple values into a single value. In fact, they are non-directional: They can send values one way at one time and another way later, and they can even do both at the same time, as in the below example where two values are fed rightward and the middle value feeds leftward. The key to understanding splitters is their attributes. In the following, the term split end refers to one of the multiple wires on one side, while the term combined end refers to the single wire on the other side. The Facing attribute tells where the split ends should be relative to the combined end. This cannot be changed once a splitter is dropped into the circuit.

66 The Fan Out attribute specifies how many split ends there are. This also cannot be changed once a splitter is dropped into the circuit. The Bit Width attribute specifies the bit width of the combined end. The Bit x attribute says which split end corresponds to bit x of the combined end. If multiple bits correspond to the same split end, then their relative ordering will be the same as in the combined end. Logisim splitters cannot have a bit from the combined end correspond to multiple split ends. Note that any change to the Fan Out or Bit Width attributes will reset all Bit x attributes so that they will distribute the bits of the combined value as evenly as possible among the split ends. Next: Wire colors. Wire colors We are now in a position to summarize the full rainbow of colors that Logisim wires can take on. The following little circuit illustrates all of them at once. Gray: The wire's bit width is unknown. This occurs because the wire is not attached to any components' inputs and outputs. (All inputs and outputs have a defined bit width.) Blue: The wire is for carrying a one-bit value, but the value it is carrying is not known. In the above example, this is occurring because the NOT gate's input is unknown, and so its output is also unknown. Dark green: The wire is carrying a one-bit 0 value. Bright green: The wire is carrying a one-bit 1 value. Black: The wire is carrying a multi-bit value. Some or all of the bits may not be specified. Red: The wire is carrying an error value. This usually arises because conflicting values on the wire. (The other possibility would be that a library component is programmed to emit an error value for another reason; in the built-in libraries, though, error values arise only from propagating other error values.) In the above example, we have one input pin placing a 0 on the wire and another placing a 1 on the wire, causing a conflict. Multi-bit wires will turn red when any of the bits carried are error values.

67 Orange: The components attached to the wire do not agree in bit width. An orange wire is effectively "broken": It does not carry values between components. Next: User's Guide. Combinational analysis All circuits fall into one of two well-known categories: In a combinational circuit, all circuit outputs are a strict combination of the current circuit inputs, whereas in a sequential circuit, some outputs may depend on past inputs (the sequence of inputs over time). The category of combinational circuits is the simpler of the two. Practitioners use three major techniques for summarizing the behavior of such circuits. logic circuits Boolean expressions, which allow an algebraic representation of how the circuit works truth tables, which list all possible input combinations and the corresponding outputs The Combinational Analysis module of Logisim allows you to convert between these three representations in all directions. It is a particularly handy way of creating and understanding circuits with a handful of one-bit inputs and outputs. Opening Combinational Analysis Editing the truth table

68 Creating expressions Generating a circuit Next: Opening Combinational Analysis. Opening Combinational Analysis The bulk of the Combinational Analysis module is accessed through a single window of that name allowing you to view truth tables and Boolean expressions. This window can be opened in two ways. Via the Window menu Select Combinational Analysis, and the current Combinational Analysis window will appear. If you haven't viewed the window before, the opened window will represent no circuit at all. Only one Combinational Analysis window exists within Logisim, no matter how many projects are open. There is no way to have two different analysis windows open at once. Via the Project menu From a window for editing circuits, you can also request that Logisim analyze the current circuit by selecting the Analyze Circuit option from the Project menu. Before Logisim opens the window, it will compute Boolean expressions and a truth table corresponding to the circuit and place them there for you to view. For the analysis to be successful, each input must be attached to an input pin, and each output must be attached to an output pin. Logisim will only analyze circuits with at most eight of each type, and all should be single-bit pins. Otherwise, you will see an error message and the window will not open. In constructing Boolean expressions corresponding to a circuit, Logisim will first attempt to construct a Boolean expressions corresponding exactly to the gates in the circuit. But if the circuit uses some non-gate components (such as a multiplexer), or if the circuit is more than 100 levels deep (unlikely), then it will pop up a dialog box telling you that deriving Boolean expressions was impossible, and Logisim will instead derive the expressions based on the truth table, which will be derived by quietly trying each combination of inputs and reading the resulting outputs. After analyzing a circuit, there is no continuing relationship between the circuit and the Combinational Analysis window. That is, changes to the circuit will not be reflected in the window, nor will changes to the Boolean expressions and/or truth table in the window be reflected in the circuit. Of course, you are always free to analyze a circuit again; and, as we will see later, you can replace the circuit with a circuit corresponding to what appears in the Combinational Analysis window.

69 Limitations Logisim will not attempt to detect sequential circuits: If you tell it to analyze a sequential circuit, it will still create a truth table and corresponding Boolean expressions, although these will not accurately summarize the circuit behavior. (In fact, detecting sequential circuits is provably impossible, as it would amount to solving the Halting Problem. Of course, you might hope that Logisim would make at least some attempt - perhaps look for flip-flops or cycles in the wires - but it does not.) As a result, the Combinational Analysis system should not be used indiscriminately: Only use it when you are indeed sure that the circuit you are analyzing is indeed combinational! Logisim will make a change to the original circuit that is perhaps unexpected: The Combinational Analysis system requires that each input and output have a unique name that conforming to the rules for Java identifiers. (Roughly, each character must either a letter or a digit, and the first character must be a letter. No spaces allowed!) It attempts to use the pins' existing labels, and to use a list of defaults if no label exists. If an existing label doesn't follow the Java-identifier rule, then Logisim will attempt to extract a valid name from the label if at all possible. Incidentally, the ordering of the inputs in the truth table will match their top-down ordering in the original circuit, with ties being broken in left-right order. (The same applies to the ordering of outputs.) Next: Editing the truth table. Editing the truth table On opening the Combinational Analysis window, you will see that it consists of five tabs.

70 This page describes the first three tabs, Inputs, Outputs, and Table. The next page of the guide describes the last two tabs, Expression and Minimized. The Inputs and Outputs tabs The Inputs tab allows you to view and edit the list of inputs. To add new inputs, type it in the field at the pane's bottom, and click Add. If you want to rename an existing input, select it in the list in the pane's upper left region; then type the name and click Rename. To remove an input, select it from the list and click Remove. You can also reorder the inputs (which affects the order of columns in the truth table and in the generated circuit) using the Move Up or Move Down buttons on an input. All actions affect the truth table immediately. The Outputs tab works in exactly the same way as the Inputs tab, except of course it works with the list of outputs instead. The Table tab The only item under the Table tab is the current truth table, diagrammed in the conventional order, with inputs constituting the columns on the left and outputs constituting the columns on the right. You can edit the current values appearing in the output columns by clicking on the value of interest. The values will cycle through 0, 1, and x (representing a "don't care"). As we'll see on the next page, any don't-care values allow the computation of minimized expressions some flexibility.

71 You can also navigate and edit the truth table using the keyboard. And you can copy and paste values using the clipboard. The clipboard can be transferred to any application supporting tab-delimited text (such as a spreadsheet). If the truth table is based on an existing circuit, you may see some pink squares in the output columns with "!!" in them. These correspond to errors that occurred while calculating the value for that row - either the circuit seemed to be oscillating, or the output value was an error value (which would be pictured as a red wire in the Logisim circuit). Hovering your mouse over the entry should bring up a tool tip describing which type of error it was. Once you click on the error entry, you will be in the 0-1-x cycle; there is no way to go back. Next: Creating expressions. Creating expressions For each output variable, the Combinational Analysis window maintains two structures - the relevant column of the truth table, and a Boolean expression - specifying how each output relates to its input. You can edit either the truth table or the expression; the other will automatically change as necessary to keep them consistent. As we will see on the next page, the Boolean expressions are particularly useful because the Combinational Analysis window will use these when told to build a circuit corresponding to the current state. You can view and edit the expressions using the window's last two tabs, the Expression tab and the Minimized tab.

72 The Expression tab The Expression tab allows you to view and edit the current expression associated with each output variable. You can select the output expression you want to view and edit using the selector labeled "Output:" at the pane's top. Just below the selector will appear the expression formatted in a particularly common notation, where an OR is represented as addition, an AND is represented as multiplication, and a NOT is denoted with a bar above the portion affected by the NOT. The text pane below this displays the same information in ASCII form. Here, a NOT is represented with a tilde ('~'). You can edit the expression in the text pane and click the Enter button to make it take effect; doing this will also update the truth table to make it correspond. The Clear button clears the text pane, and the Revert button changes the pane back to representing the current expression. Note that your edited expression will be lost if you edit the truth table. In addition to multiplication and addition standing for AND and OR, an expression you type may contain any of C/Java logical operators, as well as simply the words themselves. highest precedence ~! NOT (none) & && AND ^ XOR

73 lowest precedence + OR The following examples are all valid representations of the same expression. You could also mix the operators. ~a (b + c)!a && (b c) NOT a AND (b OR c) In general, parentheses within a sequence of ANDs (or ORs or XORs) do not matter. (In particular, when Logisim creates a corresponding circuit, it will ignore such parentheses.) The Minimized tab The final tab displays a minimized sum-of-products expression corresponding to a column of the truth table. You can select which output's minimized expression you want to view using the selector at top. If there are four or fewer inputs, a Karnaugh map corresponding to the variable will appear below the selector. You can click the Karnaugh map to change the corresponding truth table values. The Karnaugh map will also display the currently selected terms for the minimized expression as solid semitransparent rounded rectangles. Below this is the minimized expression itself, formatted as in the Expression tab's display. If there are more than four inputs, the Karnaugh map will not appear; but the minimized expression will still be computed. (Logisim uses the Quine-McCluskey algorithm to compute the minimized expression. This is equivalent to a Karnaugh map, but it applies to any number of input variables.)

74 The Set As Expression button allows you to select the minimized expression as the expression corresponding to the variable. This will generally not be necessary, as edits to the truth table result in using the minimized expression for the changed column; but if you enter an expression through the Expression tab, this can be a convenient way to switch to the corresponding minimized expression. Next: Generating a circuit. Generating a circuit The Build Circuit button will construct a circuit whose gates correspond to the currently chosen expressions for each output. The circuit's inputs and outputs will be displayed in top-down order corresponding to how they appear under the Inputs and Outputs tabs. Generally speaking, the constructed circuit will be attractive; and, indeed, one application of Logisim's Combinational Analysis module is to beautify poorly drawn circuits. Still, as with any automatic formatting, it will not express the structural details that a human-drawn circuit would. When you click the Build Circuit button, a dialog box will appear prompting you to choose which project where you want the circuit and the name you wish to give it. If you type the name of an existing circuit, then that circuit will be replaced (after Logisim prompts you to confirm that you really want to do this). The Build Circuit dialog includes two options. The Use Two-Input Gates Only option specifies that you want all gates constructed to have two inputs. (NOT gates, of course, constitute an exception to this rule.) The Use NAND Gates Only option specifies that you would like it to translate the circuit into one using only NAND gates. You can select both options if you want to use only two-input NAND gates. Logisim cannot construct a NAND-only circuit for an expression containing any XOR operators. This option will therefore be disabled if any outputs' expressions contain XORs. Next: User's Guide. Memory components The RAM and ROM components are two of the more useful components in Logisim's built-in libraries. However, because of the volume of information they can store, they are also two of the most complex components. Documentation about how they work within a circuit can be found on the RAM and ROM pages of the Library Reference. This section of the User's Guide explains the interface allowing the user to view and edit memory contents. Poking memory Pop-up menus and files Logisim's integrated hex editor

75 Next: Poking memory. Poking memory You can manipulate the contents of memory using the Poke Tool, but the interface for this is severely limited by space constraints: For more than the simplest editing, you will probably find the integrated hex editor far more convenient. Nonetheless, to view and edit values within the circuit, the Poke Tool has two modes of operation: You can edit the address displayed, and you can edit an individual value. To edit the address displayed, click outside the display rectangle. Logisim will draw a red rectangle around the top address. Typing hexadecimal digits will change the top address accordingly. Typing the Enter key will scroll down one line. Typing the Backspace key will scroll up one line. Typing the space bar will scroll down one page (four lines). To edit a particular value, click the value within the display rectangle. Logisim will draw a red rectangle around that address. Typing hexadecimal digits will change the value at the address currently being edited. Typing the Enter key will move to editing the value just below it in the display (down one line). Typing the Backspace key will move to editing the value at the previous address. Typing the space bar will move to editing the value at the following address. Next: Pop-up menus and files. Pop-up menus and files The pop-up menu for memory includes four options in addition to the options common to all components: Edit Contents: Bring up a hex editor for editing the contents of memory. Clear Contents: Resets all values in memory to 0. Load Image...: Resets all values in memory based on the values found in a file using the format described below. Save Image...: Stores all values in memory into a file using the format described below. The file format used for image files is intentionally simple; this permits you to write a program, such as an assembler, that generates memory images that can then be loaded into memory. As an example of this file format, if we had a 256-byte memory whose

76 first five bytes were 2, 3, 0, 20, and -1, and all subsequent values were 0, then the image would be the following text file. v2.0 raw ff The first line identifies the file format used (currently, there is only one file format recognized). Subsequent values list the values in hexadecimal, starting from address 0; you can place several such values on the same line. Logisim will assume that any values unlisted in the file are zero. The image file can use run-length encoding; for example, rather than list the value 00 sixteen times in a row, the file can include 16*00 rather than repeat 00 sixteen times. Notice than the number of repetitions is written in base 10. Files produced by Logisim will use run-length encoding for runs of at least four values. Next: Hex editor. Hex editor Logisim includes an integrated hex editor for viewing and editing the contents of memory. To access it, bring up a pop-menu for the memory component and select Edit Contents... For ROM components, which have the memory contents as part of the attribute value, you can alternatively access the hex editor by clicking the corresponding attribute value. The numbers in italics at left display memory addresses, written in hexadecimal. The other numbers display values starting from that memory address; the hex editor may display four, eight, or sixteen values per line, depending on what fits in the window. To help with counting, each group of four values has a larger space between. You can navigate through memory using the scroll bar or using the keyboard (the arrow keys, home, end, page up, and page down). Typing hexadecimal characters will alter the currently selected value. You can select a range of values by dragging the mouse, shift-clicking the mouse, or navigating through memory with the keyboard while depressing the shift key. Values

77 may be copied and pasted using the Edit menu; the clipboard can also be transferred into other applications. Next: User's Guide. Logging In testing a large circuit, and for documenting a circuit's behavior, a log of past circuit behavior. This is the purpose for Logisim's logging module, which allows you to select components whose values should be logged; optionally, you can specify a file into which the log should be placed. Note: The logging module is in alpha phase; it may be buggy, and it is subject to significant changes in the future. While bug reports and suggestions are welcome for all of Logisim, they are particularly welcome concerning this relatively new feature. If you do not send comments, then it will likely not change. You can enter the logging module via the Logging... option from the Simulate menu. It brings up a window with three tabs. We will discuss each of these tabs separately. The Selection tab The Table tab The File tab Each project has only one logging window; when you switch to viewing another circuit within the project, the logging window switches automatically to logging the

78 other circuit instead. That is, it does this unless you are moving up or down within the same simulation, in which case the logging module does not change. Note that when the logging module switches to logging another simulation, it will cease any logging into a file. Should you switch back to the simulation again, it will remember the configuration for that simulation, but you will need to re-enable the file logging manually. Next: The Selection tab. The Selection tab The Selection tab allows you to select which values should be included in the log. The window below corresponds to the following circuit. The tab is divided into three vertical areas. The first (leftmost) is a list of all components in the circuit whose values can be logged. Among the built-in libraries, the following types of components support logging.

79 Base library: Pin, Probe, and Clock components Memory library: All components For components with labels associated with them, their names correspond to the labels; other components' names specify their type and their location within the circuit. Any subcircuits will also appear in the list; they cannot be selected for logging, but eligible components within them can be. Note that the RAM component requires you to choose which memory address(es) should be logged; it allows logging only for the first 256 addresses. The last (rightmost) vertical area lists those components that have been selected. Also, it indicates the radix (base) in which the component's multi-bit values will be logged; the radix does not have a significant effect on one-bit values. The middle column of buttons allows the manipulation of the items within the selection. Add adds the currently selected item(s) on the left side into the selection. Change Radix cycles the radix for the currently selected component in the selection between 2 (binary), 10 (decimal), and 16 (hexadecimal). Move Up moves the currently selected component in the selection forward one spot. Move Down moves the currently selected component in the selection back one spot. Remove removes the currently selected component in the selection. Next: The Table tab. The Table tab The Table tab displays the current log graphically.

80 The table contains a column for each component in the selection. Each row in the selection displays a snapshot of the simulation after a propagation of values has completed. Any duplicate rows are not added into the log. Note that only the most recent 400 rows are displayed. Some rows may have empty entries if the corresponding component was not in the selection at the time that the row was computed. The displayed table is for review only; it is not interactive. Next: The File tab. The File tab The File tab allows you to specify a file into which the log should be placed.

81 At the top is an indicator of whether file logging is in progress and a button for enabling or disabling it. (Note that you cannot enable it until a file is selected below.) The button allows you to pause and restart file entry. When you switch in the project window to viewing another simulation, the file logging is automatically halted; if you return to the original one and want logging to continue, you will need to re-enable the file logging manually using the button at top. In the middle is an indicator of what file is being logged to. To change it, use the Select... button. On selecting a file, file logging will automatically start. If you select a pre-existing file, Logisim will ask whether you want to overwrite the file or append the new entries onto the end. At bottom you can control whether a header line should be placed into the file indicating which items are in the selection. If header lines are added, then a new header line will be placed into the file whenever the selection changes. File format Entries are placed into the file in tab-delimited format corresponding closely to what appears under the Table tab. (One difference is that any header lines will give the full path to components lying in subcircuits.) The format is intentionally simple so that you can feed it into another program for processing, such as a Python/Perl script or a spreadsheet program. So that a script can process the file at the same time as Logisim is running, Logisim will flush the new records onto the disk every 500 ms. Note that Logisim may also intermittently close and later re-open the file during the simulation, particularly if several seconds have elapsed without any new records being added.