UNIVERSITI MALAYSIA PERLIS DKT DIGITAL SYSTEMS II. Lab 2 : Counter Design

Transcription

1 UNIVERSITI MALAYSIA PERLIS DKT 212/3 : DIGITAL SYSTEM II Lab 2 : Counter Design Name : Matrix No. : Program : Date :

2 OBJECTIVE 1. To understand state diagram in sequential circuit. 2. To build Karnaugh Map for a J-K flip-flops. 3. To design a Synchronous counter using J-K flip-flops. 4. To develop Synchronous counter in schematic diagram. 5. To construct Synchronous counter with connect to Sevent Segment Display. EQUIPMENT/COMPONENTS Power Supply of 5V DC output Function generator Multimeter Bread Board Logic Gate IC : 7408 (1pc), 7447 (1pc), 7476 (2pcs), 7432 (1pc) Seven Segment Display (1pc) Resistors : 330Ω (1pc) Toggle Switch (1pc) LED (3pcs) INTRODUCTION Counters are classified into two broad categories according to the way they are clocked: asynchronous and synchronous. In asynchronous counters, the first flip-flop is clocked by the external clock pulse, and then each successive flip-flop is clocked by the output of the preceding flip-flop. However, in synchronous counters, all flip-flops will be connected to the same clock input so that they are clocked simultaneously. Our focus is to design the synchronous counter. Synchronous counter design is also known as sequential circuit design. Figure 2.1 illustrates the general idea of clocked sequential circuit. It can be noticed that there is a clock input to the memory section. Figure 2.1: General Clocked for Sequential Circuit Block Diagram

3 Several methods exist for designing counters that follow arbitrary sequences. One common method is using J-K flip-flop in a synchronous counter configuration. The basic idea is to design the logic circuits that decode the various states of the counter to supply the logic levels to each J and K input by applying the transition table as shown in Table 2.1 (J-K Flip Flops Transition Table). Output Transitions FF Inputs Q(t) Q(t+1) J K X 1 X X 1 X 0 Table 2.1: J-K flip-flop excitation table As usual, you will be given a design problem. It is an advantage for you to master the synchronous counter design technique using J-K flip-flop before attending the lab session.

4 PROCEDURE Flip-flop Counter Design 1. Design a binary counter with sequence shown on the state transition diagram in Figure Figure 2.2: Counting Sequence 2. You will need to determine the following : a. Create the circuit excitation table as in Table 2.2 based on the given state transitions in Table 2.1 above. b. Create your Karnaugh Map for a J-K flip-flop to generate the required inputs for the flip-flops. (Don t care states can be placed in the corresponding invalid cells.) c. Draw the circuit diagram to implement the expressions derived from your K- Map. 3. Construct the circuit you have drawn. Put a Switch A to your CLR/RESET pin for all your flip-flops. (procedure no 8) (Make sure your PRE pins are set to HI to disable the PRE/SET function). 4. Assign a clock pulse (square waveform) from a pattern generator with a frequency of 1 Hz to your counter. 5. Demonstrate the output result into LED1 (Q0), LED2 (Q1) and LED3 (Q2). 6. Construct the schematic circuit with connect to 7-Segment Display by using Logic IC 7447 (BCD to 7-Segment Decoder). Please refer Data Sheet for right connection. (procedure no 9) 7. Justify your design and demonstrate to your lecturer for verification.

5 DKT 212 DIGITAL SYSTEM II LAB 2 : COUNTER DESIGN NAME: MATRIX NO.: COURSE: TABLE NO.: (A) COUNTER DESIGN 1) Specify the counter sequence and draw the state diagram ) Derive the Next-state table from State Diagram. Decimal Present Value OUTPUT VALUES Binary Present Binary State Next State Q2 Q1 Q0 Q2 Q1 Q0

6 3) Developed Transition Table for a J-K flip-flop. 4) Complete the Table 2.2: JK Flip-flop Counter Excitation Table. Decimal Present Value OUTPUT VALUES Binary Present Binary State Next State INPUT VALUES Flip-flop 2 Flip-flop 1 Flip-flop 0 Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Table 2.2: JK Flip-flop Counter Excitation Table

7 5) Developed Karnaugh Map from JK Flip-flop Counter Excitation Table. 6) Simplify Boolean Expressions for Flip-Flops input. J2 =, K2 = J1 =, K1 = J0 =, K0 =

8 7) Draw the circuit diagram based on Logic Expression. 8) Draw the Counter Circuit Diagram with connect to Logic IC 7476

9 9) Complete the Counter Circuit Diagram with connect to Logic IC 7447 and 7-Segment Display. (B) DEMO 1. Success demonstrate for LED1 (Q0), LED2 (Q1) and LED3 (Q2) output. 2. Success counter operational shown on right sequence for 7-Segment display. Remarks: