# Counters. Non-synchronous (asynchronous) counters A 2-bit asynchronous binary counter High

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1 Counters Learning objectives Understanding the operation and characteristics of asynchronous and synchronous counters Analyze counter circuits and counter timing diagrams Determine the sequence of a counter Determine the modulus of a counter Analyze various types of counters Construct of up/down synchronous counters Design of sequential systems Design of sequential counters with specified sequences Counter decoding by use of logic gates Applications of synchronous counter design stepper motor control A counter is an electronic circuit that is able to count the number of pulses applied to its input terminals. Essentially, a counter consists of cascade connection of a number of flip-flops, usually of either the J-K type or the D type which may be operated either synchronously or non-synchronously. With synchronous operation all the flip-flops making up the counter operate at the same instant in time under the control of a clock pulse. In the case of non-synchronous operation each flip-flop operates in turn. The first flip-flop is clocked by the external clock pulse and then successive flip-flop is clocked by the output of the preceding flip-flop. This means that each stage must change state before the following stage can do so. As a result, synchronous operation is much faster and the use of a non-synchronous counter is acceptable only when the speed of operation is not of particular importance. The possible applications for counters are many. They are often used for the direct counting of objects in industrial processes and of voltage pulses in digital circuits such as digital voltmeters. Counters can be used as frequency dividers and for the measurement of frequency and time. Non-synchronous (asynchronous) counters A 2-bit asynchronous binary counter High J FF Q J K The clock () is applied only to the clock input of, which is always the least significant bit (LSB). FF is triggered by the Q output of. change state at the positive-going edge of each clock pulse, but FF changes only when triggered by a positive-going transition of the Q output of

2 . Because of the propagation delay through a flip-flop, the counter operation is asynchronous. The timing diagram Outputs { Q(LSB) Q(MSB) For simplicity, the transitions of, Q, and the clock pulses are shown as simultaneous even though this is an asynchronous counter. Binary state sequence for the 2-bit asynchronous binary counter Clock pulse Q Initially (recycles) The term recycle is commonly applied to counter operation; it refers to the transition of the counter from its final state back to its original state. A 3-bit asynchronous binary counter High J FF Q J Q K FF2 J 2 K 2 The basic operation is the same as that of the 2-bit counter, except that the 3-bit counter has eight states, due to its three flip-flops. The 3-bit counter progress through a binary counter of zero through 7 and then recycles to the zero state. Asynchronous counters are also called ripple counters as an input clock pulse ripples through the counter, experiencing propagation delays, to reach the last flip-flop. Asynchronous decade counters The modulus of a counter is the number of unique states that the counter will sequence through. The

3 maximum modulus of a counter is 2 n, where n is the number of flip-flops in the counter. Counters can be designed to have a number of states in their sequence that is less than 2 n. The resulting sequence is called a truncated sequence. One common modulus for counters with truncated sequence is ten. Counters with ten states in their sequence are called decade counters. A decade counter with a count sequence of zero () through nine () is a BCD decade counter. This type of counter is useful in display applications in which BCD is required for conversion to a decimal readout. CLR High J FF Q J FF2 J 2 FF3 Q 3 J 3 K K 2 K 3 CLR CLR CLR CLR One way to make the counter recycle after the count of nine () is to decode count ten () with a NAND gate and connect the output of the NAND gate to the clear (CLR ) inputs of the flip-flops. Question: How many states does a modulus-4 counter have? What is the minimum number of flip-flops required? Synchronous counters The term synchronous refers to events that have a fixed time relationship with each other. A 2-bit synchronous binary counter High FF Q J J Q K Assume that the counter is initially in the binary state; that both flip-flops are RESET. When the positive edge of the first clock pulse is applied, will toggle and will therefore go HIGH. What happens to FF at the positive-going edge of? At first, inputs J and K are both LOW because of. Remember, there is a propagation delay from the triggering edge of the clock pulse until the Q output actually makes a transition. So, J = and K = when the leading edge of the first clock pulse

4 is applied. FF does not change state. After, =, Q =. When the leading edge of 2 occurs, will toggle and will go LOW. Since FF has a HIGH on J and K inputs at the triggering edge of this clock pulse, the flip-flop toggles and Q goes HIGH. Timing diagram Q * For simplicity, the propagation delay is not demonstrated. A 3-bit synchronous binary counter HIGH FF Q FF2 Q J J J 2 K K 2 Timing diagram Q Questions In an asynchronous counter, all filp-flops change states at the same time, true or false? How does a synchronous counter differ from an asynchronous counter? Comparison of synchronous and asynchronous counters A synchronous counter can operate at a much higher input frequency. However, the circuitry of the synchronous counter is more complex than that of the asynchronous counter.

5 Up/Down synchronous counters An up/down counter is one that is capable of progressing in either direction through a certain sequence. An up/down counter is sometimes called a bidirectional counter, can have any specified sequence of states. In general, most up/down counters can be reversed at any point in their sequence. Up {,, 2, 3, 4, 5, 4, 3, 2, 3, 4, 5, 6, 7, 6, 5, etc. { Up { { Down Down Up/Down sequence for a 3 bit binary counter Clock Pulse Next State Q An examination of for both the up and down sequence shows that toggles on each clock pulse. Thus, J = = For the up sequence, Q changes state on the next clock pulse when =. For the down sequence, Q changes state on the next clock pulse when =. Thus, the J and K inputs of FF must equal under the conditions expressed by the following equation: J = K = ( Q iup) + ( Q i DOWN) For the up sequence, changes state on the next clock pulse when = Q =. For the down sequence, changes state on the next clock pulse when = Q =. Thus, the J 2 and K 2 inputs of FF2 must equal under the conditions expressed by the following equation: J = K = ( Q iq iup) + ( Q iq i DOWN) 2 2 Each of the conditions for the J and K inputs of each flip-flop produces a toggle at the appropriate point in the counter sequence.

6 High UP QUP FF FF2 UP/DOWN J J Q J 2 K Q K 2 DOWN QDOWN UP/DOWN control input is HIGH for UP and LOW for DOWN Question What is the difference between the counting sequence of an up counter and a down counter? Design of synchronous sequential systems A general sequential system consists of a combinational logic section and a memory section (flip-flops). The design of sequential systems typically starts with a problem statement, a verbal description of the intended behavior of the system. The goal is to develop a block diagram of the system utilizing the available components and meeting the design objectives and constrains. Design example State table Q n Q n+ z x = x = A A B B A C C A D D A D B/ A/ C/ A state diagram D/ A state table shows for each input and present state what the output is and what the next state is. A state diagram is a graphical representation of the behavior of the system, showing for each input and present state what the output is and what the next state is. One possible state assignment Q Q A B C D

7 From either the state diagram or the state table, we can construct the design truth table for the next state. Q x Q n n Q,n+,n+ A B C D A B C D We can now map Q,n+,,n+, and z QQ 2 QQ 2 Q z Q,n+,n+ We thus have the state equations Q = xq + xq, n+ 2n n Q = xq + xq 2, n+ 2 z = Q Q n 2n For the D flip-flop, the design table Q n Q n+ D The equations Implementation using D flip-flop D = xq + xq 2n n D = xq + xq 2 2

8 x D Q z Q D Question How many sections does a sequential system consist of? What is the state diagram? Design of synchronous counters Step : State diagram A counter is first described by a state diagram, which shows the progression of states through which the counter advances when it is clocked. Step 2: Next-state table Once the sequential circuit is defined by a state diagram, the next step is to derive a next-state table, which lists each state of the counter (present state) along with the corresponding next state. The next state is the state that the counter goes to from its present state upon application of a clock pulse. The next state is derived from the state diagram. Present State Next State Q Q

9 Step 3: Flip-flop transition table All possible output transitions are listed by showing the Q output of the flip-flop going from present states to next states. Q n is the present state of the flip-flop (before a clock pulse) and Q n+ is the next state (after a clock pulse). For each output transition, the J and K inputs that will cause the transition to occur are listed. The s indicate a don t care (the input can be either or ). Output Transition Flip-Flop Inputs Q n Q n+ J K To design the counter, the transition table is applied to each of the flip-flops in the counter, based on the next-state table. Step 4: Karnaugh maps Karnaugh maps can be used to determine the logic required for the J and K inputs of each flip-flop in the counter. There is a Karnaugh map for the J input and a Karnaugh map for the K input of each flip-flop. Example of Karnaugh map procedure: J map K map Q Q The completed Karnaugh maps for all three flip-flops

10 Q QQ QQ 2 J map 2 Q J map Q J map Q Q Q Q Q Q QQ K 2 map K map Q K map Q Step 5: Logic expression for flip-flop inputs From the completed Karnaugh maps for all three flip-flops, the following expressions for the J and K inputs of each flip-flop can be obtained: J = Q Q + Q Q = Q Q K = Q Q + Q Q = Q Q J = Q Q K = Q Q 2 2 J = QQ K = QQ 2 2 Step 6: Counter implementation The final step is to implement the combinational logic from the expressions for the J and K inputs and connect the flip-flops to form the complete 3-bit counter. J FF Q J FF2 J 2 Q K K 2 A summary of steps (can be applied to any sequential circuit):. Specify the counter sequence and draw a state diagram. 2. Derive a next-state table from the state diagram. 3. Develop a transition table showing the flip-flop inputs required for each transition. The transition

11 table is always the same for a given type of flip-flop. 4. Transfer the J and K states from transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop. 5. Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input. 6. Implement the expressions with combinational logic, and combine with the flip-flop to create the counter. Example Design a counter with the irregular binary count sequence shown in the state diagram as shown. Use J-K flip-flops. () (7) (2) (5) Solution Step : A 3-bit counter is required to implement this sequence. The invalid states (, 3, 4, 6) can be treated as don t cares in the design. However, if the counter should erroneously get into an invalid state, we must make sure that it goes back to a valid state. Step 2: The next-state table is developed from the state diagram. Present State Next State Q Q Step 3: The transition table for the J-K flip-flop is shown. Output Transition Flip-Flop Inputs Q n Q n+ J K Step 4: The J and K inputs are plotted on the present-state Karnaugh maps. Also don t cares can be placed in the cells corresponding to the invalid states of,,, and, as indicated by the red s.

12 Q J 2 map Q Q J map Q J map Q Q Q Q K map 2 K map K map Step 5: Group the s, taking the advantage of as many of the don t care states as possible for maximum simplification. The expression for each J and K input taken from the maps is as follows: J =, K = Q 2 J = K = J = K = Q 2 2 Step 6: The implementation of the counter is as shown. HIGH HIGH FF Q FF2 J J J 2 K K 2 An analysis shows that if the counter, by accident, gets into one of the invalid states (, 3, 4, 6), it will always return to a valid state according to the following sequence: 3 4 7, and 6. Counters with nonstandard sequences One convention that makes the design process easier is to list the present states, including unused states, even if the circuit does not count in binary order. Since the synchronous input functions are Boolean functions of the present state variables, keeping them in truth table order allows us easily to use familiar techniques of simplification, such as K-maps. Example Design a synchronous sequential circuit that will produce the biquinary sequence shown in the state diagram. Test the unused states to ensure that they enter the main sequence in one or more clock pulses.

13 Solution State table for a Biquinary Sequence Counter Present state Q D Q C Q B Q A Next state Q D Q C Q B Q A J D K D J C K C J B K B J A K A The J and K inputs indicated in the above table are loaded into Karnaugh maps as shown in the following figure.

14 QQ D C Q B Q A QQ D C Q B Q A Q C Q C J D K D QQ B A QQ D C QQ QQ B A QQ D C B A J C K C QQ B A QQ D C QQ B A QQ D C Q A Q A J B K B QQ B A QQ D C Q C QQ B A QQ D C J A K A This yields the following Boolean equations for the synchronous inputs: J = Q K = Q J = Q Q K = D C, D C, C B A, C J = Q K = Q J = Q, K = B A, B A, A C A The counter derived from these Boolean equations. J A Q A J B Q B J C Q C J 2 Q D K A K B K C Q C K 2

15 There are six unused states in the count sequence. Each of them is tested as shown in the following table. Present state Q D Q C Q B Q A J D K D J C K C J B K B J A K A Next state Q D Q C Q B Q A The revised state diagram is shown in the following figure, including the six unused states. Questions What determine the counter sequence for a counter circuit? The synchronous counter design procedure can be used for the following sequence:,,,,,,, and repeat, true or false? Counter Decoding In many applications, it is necessary that some or all of the counter states be decoded. The decoding of a counter involves using decoders or logic gates to determine when the counter is in a certain binary state in its sequence. To decode binary state 6 () of a 3-bit binary counter, when =, Q =, =, a HIGH appears on the output of the decoding gate, indicating that the counter is at state 6. This is called active-high decoding.

16 High J FF J Q K LSB Decoded 6 QQQ 2 Q FF2 J 2 Example Implement the decoding of binary state 2 and binary state 7 of a 3-bit synchronous counter. Show the entire counter timing diagram and the output waveforms of the decoding gates. Binary 2 = QQQ, and 2 binary 7 = Q. Solution High Q LSB J FF Q J K 2 MSB FF2 MSB J 2 K K Q Decoded outputs { 2 7 Applications of synchronous counter design -- stepper motor control A stepper motor is a motor that rotates in steps, typically 5 per step, rather than in a continuous motion. Magnetic coils or windings within the motor must be energized and deenergized in a specific sequence in order to produce this stepping action. Digital signals are normally used to control the current in each of the motor s coils. Stepper motors are used extensively in situation s where precise position control is needed, such as in positioning of read/write head on magnetic disks, in controlling

17 print heads in printers and in robots. D (Direction input) Synch Counter A A B B Coil Current amplifiers Coil CW 4 Step (clock) 2 CCW 3 Stepper motor For the motor to rotate properly, coils and 2 must always be in opposite states; that is, when coil is energized, coil 2 is not, and vice versa. Likewise, coil 3 and coil 4 must always be in opposite states. The outputs of a two-bit synchronous counter are used to control the current in the four coils; A and A control coils and 2, and B and B control coils 3 and 4. The current amplifiers are needed because the Flip-flop outputs cannot supply the amount of current that the coils require. Because this stepper motor can rotate either clockwise (CW) or counter-clockwise (CCW), we have a Direction input, D, which is used to control the direction of rotation. The state diagram For CW rotation to occur, we must have D =, and the state of the counter BA, must follow the sequence,,,,,,, and so on, as it is clocked by the Step input signal. For CCW rotation, D =, and the counter must follow the sequence,,,,,,,, and so on. CW rotation D = CCW rotation D = Next state and transition table Present State D B A Next state B A Control inputs J B K B J A K A

18 K maps D BA D BA D BA D BA J B K B J A K A J = DA+ DA= D A, K = DA+ DA= D A B J = DB+ DB= D B, K = DB+ DB= D B A Synchronous counter implementation from the J, K equations B A B B To current amplifiers A A To current amplifiers J B B J A A K B B K A A Step D (direction) Review Questions What is a counter? How many states does a modulus- counter have? What is a state diagram? What is the next-state table? What is the procedure for designing a synchronous counter? A certain J-K flip-flop has propagation delay of 2 ns. What is the largest modulus of the counter that can be constructed from these flip-flops and still operate up to MHz? True or false: The synchronous counter design procedure can be used for the following sequence:,,,,,, and repeat.

19 Exercises. By analyzing the J and K inputs to each flip-flop prior to each clock pulse, prove that the decade counter in the following figure progresses through a BCD sequence. Explain how these conditions in each case cause the counter to go to the next proper state. High J J Q Q2 Q 3 J J 3 Q 3 K FF K FF2 K 3 FF3 2. Determine the sequence of the counter in the following figure. Begin with the counter cleared. High J J Q J J 3 Q 3 K K K 3 FF FF2 FF3 3. Analyze the sequential circuit as shown in the following figure. Write down the input equation, next state equation and output equation and draw the output waveforms of Q, and Y for the 4 consecutive clock pulses. Assume that Q and are initially Reset. D Q D D Y Q 4. Design a counter to give the necessary states from (state ) through to (state 7). Use D-type flip-flops. 5. Write the logic expression of a mod-6 binary up-counter using J-K type flip-flops.

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