BISTABLE LATCHES AND FLIPFLOPS


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1 ELET 3156 DL  Laboratory #3 BISTABLE LATCHES AND FLIPFLOPS No preliminary lab design work is required for this experiment. Introduction: This experiment will demonstrate the properties and illustrate some of the applications of digital switching circuits through the design, implementation and exercise of example bistable latches and flipflops. These circuits are the building blocks of logic switching circuits, and an understanding of them can assist the engineer or technologist in the design and application of a wide variety of clocked and gated systems. The basic switching circuit is the bistable flipflop of Figure 3.1. This circuit makes use of an inverted feedback loop to establish a stable logical state throughout the loop. Recall the NAND function indicated in Table 3.1. A B A NAND B Table 3.1 NAND Logic Figure 3.1 SetReset FlipFlop The output of a NAND logic gate is a logical1 unless both if its inputs are TRUE (logical 1). Only when all inputs to a NAND gate are a logical1 is its output false, (a logical 0.) PART ONE. The SetReset FlipFlop. Step 1: Construct the circuit of Figure 3.1 using an SN7400 or similar family device. The pinout of the IC is indicated on page 6. Using the debounced logic switches to stimulate the SET and RESET inputs, complete the timing diagram of Figure 3.2 below by indicating the resulting outputs of the flipflop. After completing Figure 3.2, obtain the instructor s signature before continuing. Figure 3.2 Timing Diagram of the NANDType SetReset FlipFlop Page  1
2 PART TWO. The Gated SetReset FlipFlop. Figure 3.3 illustrates the addition of an inverting buffer to the input of the SetReset FlipFlop of the previous example. Note that this buffer executes two functions, first it enables the SET and RESET signals to obtain access to the flipflop, and second, it inverts the signal as it passes it through. This changes the activelow input stimulus of the previous flipflop to an activehigh stimulus. Figure 3.3 Gated SetReset FlipFlop Step 2: Construct the circuit of Figure 3.3 using an SN7400 or similar family device. The pinout of the IC is indicated on page 6. Using the debounced logic switches to stimulate the SET and RESET inputs, and a third switch to stimulate the GATE input, complete the timing diagram of Figure 3.4 below by indicating the resulting outputs of the flipflop. After completing Figure 3.4, obtain the instructor s signature before continuing. Figure 3.4 Timing Diagram of a Gated SetReset FlipFlop Page  2
3 PART THREE. The Clocked SetReset FlipFlop. Figure 3.5 illustrates the addition of an inverter to the GATE input of a second cascaded SetReset FlipFlop. Note that this inverter enables alternating flipflops as a function of the CLOCK input. That is, when the CLOCK input is a logical1, the first flipflop is enabled, and when the clock input is a logical0, the second flipflop is enabled. Figure 3.5 Clocked SetReset FlipFlop Step 3: Construct the circuit of Figure 3.5 using two SN7400s or a similar family device. You can use one of the unused NAND gates as an inverter by tying its two inputs together. The pinout of the IC is indicated on page 6. Using the debounced logic switches to stimulate the SET and RESET inputs, and a third switch to stimulate the CLOCK input, complete the timing diagram of Figure 3.6 below by indicating the resulting outputs of the flipflop. After completing Figure 3.6, obtain the instructor s signature before continuing. FIGURE 3.6 Timing Diagram of a Clocked SetReset FlipFlop Page  3
4 PART FOUR. The Clocked DType FlipFlop. Figure 3.7 illustrates the elimination of a stimulus input of the previous circuit through the insertion of an inverter between the SET input and the RESET input of the first flipflop. This will cause the two inputs to always oppose each other. The first flipflop will follow the data on the D input while the second is disabled. When the clock is enabled, the second flipflop will latch with the data from the first stage. Figure 3.7 Clocked DType FlipFlop Construct the circuit of Figure 3.7 using two SN7400s or a similar family device. You can use the unused NAND gates as an inverter by tying its two inputs together. The pinout of the IC is indicated on page 6. Using the debounced logic switches to stimulate the D and CLOCK inputs, complete the timing diagram of Figure 3.8 below by indicating the resulting outputs of the flipflop. After completing Figure 3.8, obtain the instructor s signature before continuing. Figure 3.8 Timing Diagram of a Clocked DType FlipFlop Page  4
5 PART FIVE. The Clocked JKType FlipFlop. Figure 3.9 illustrates yet another modification of the clocked flipflop. Note that the opposing outputs are tied back to the input buffer of the first stage. The effect is to cause the output to change state on the clock edge if both the J and K inputs are high. Other than this, the operation of the flipflop is similar to the SetReset type. Figure 3.9 Clocked JKType FlipFlop Construct the circuit of Figure 3.9 using two SN7400s or a similar family device. You can use the unused NAND gates as an inverter by tying its two inputs together. An SN7410 can be used for the two logic gates on the input buffer. The pinout diagram for the SN7410 is on page 6. Using the debounced logic switches to stimulate the CK input, and two other logic switches to simulate the J and K inputs, complete the timing diagram of Figure 3.10 below by indicating the resulting outputs of the flipflop. After completing Figure 3.10, obtain the instructor s signature before continuing. FIGURE 2.10 Timing Diagram of a Clocked JKType FlipFlop Page  5
6 Based upon your previous knowledge and the results of this experiment, what conclusions can you make about the operation of the Gated SetReset FlipFlop as a result of the data recorded in Figure 3.3? Based upon your previous knowledge and the results of this experiment, what conclusions can you make about the operation of the Clocked SetReset FlipFlop as a result of the data recorded in Figure 3.5? Based upon your previous knowledge and the results of this experiment, what conclusions can you make about the operation of the Clocked DType FlipFlop as a result of the data recorded in Figure 3.7? Based upon your previous knowledge and the results of this experiment, what conclusions can you make about the operation of the Clocked JKType FlipFlop as a result of the data recorded in Figure 3.9? Include your conclusions of the operation of each circuit in the Summary section of your report. NOTES: Parts List: (1) Logic Trainer (2) SN7400 Quad 2Input NAND gate. (1) SN7410 Triple 3Input NAND gate. Page  6
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