# BISTABLE LATCHES AND FLIP-FLOPS

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1 ELET 3156 DL - Laboratory #3 BISTABLE LATCHES AND FLIP-FLOPS No preliminary lab design work is required for this experiment. Introduction: This experiment will demonstrate the properties and illustrate some of the applications of digital switching circuits through the design, implementation and exercise of example bistable latches and flip-flops. These circuits are the building blocks of logic switching circuits, and an understanding of them can assist the engineer or technologist in the design and application of a wide variety of clocked and gated systems. The basic switching circuit is the bistable flip-flop of Figure 3.1. This circuit makes use of an inverted feed-back loop to establish a stable logical state throughout the loop. Recall the NAND function indicated in Table 3.1. A B A NAND B Table 3.1 NAND Logic Figure 3.1 Set-Reset Flip-Flop The output of a NAND logic gate is a logical-1 unless both if its inputs are TRUE (logical 1). Only when all inputs to a NAND gate are a logical-1 is its output false, (a logical 0.) PART ONE. The Set-Reset Flip-Flop. Step 1: Construct the circuit of Figure 3.1 using an SN7400 or similar family device. The pin-out of the IC is indicated on page 6. Using the debounced logic switches to stimulate the SET and RESET inputs, complete the timing diagram of Figure 3.2 below by indicating the resulting outputs of the flip-flop. After completing Figure 3.2, obtain the instructor s signature before continuing. Figure 3.2 Timing Diagram of the NAND-Type Set-Reset Flip-Flop Page - 1

2 PART TWO. The Gated Set-Reset Flip-Flop. Figure 3.3 illustrates the addition of an inverting buffer to the input of the Set-Reset Flip-Flop of the previous example. Note that this buffer executes two functions, first it enables the SET and RESET signals to obtain access to the flip-flop, and second, it inverts the signal as it passes it through. This changes the active-low input stimulus of the previous flip-flop to an active-high stimulus. Figure 3.3 Gated Set-Reset Flip-Flop Step 2: Construct the circuit of Figure 3.3 using an SN7400 or similar family device. The pin-out of the IC is indicated on page 6. Using the debounced logic switches to stimulate the SET and RESET inputs, and a third switch to stimulate the GATE input, complete the timing diagram of Figure 3.4 below by indicating the resulting outputs of the flip-flop. After completing Figure 3.4, obtain the instructor s signature before continuing. Figure 3.4 Timing Diagram of a Gated Set-Reset Flip-Flop Page - 2

3 PART THREE. The Clocked Set-Reset Flip-Flop. Figure 3.5 illustrates the addition of an inverter to the GATE input of a second cascaded Set-Reset Flip-Flop. Note that this inverter enables alternating flip-flops as a function of the CLOCK input. That is, when the CLOCK input is a logical-1, the first flip-flop is enabled, and when the clock input is a logical-0, the second flipflop is enabled. Figure 3.5 Clocked Set-Reset Flip-Flop Step 3: Construct the circuit of Figure 3.5 using two SN7400s or a similar family device. You can use one of the unused NAND gates as an inverter by tying its two inputs together. The pin-out of the IC is indicated on page 6. Using the debounced logic switches to stimulate the SET and RESET inputs, and a third switch to stimulate the CLOCK input, complete the timing diagram of Figure 3.6 below by indicating the resulting outputs of the flip-flop. After completing Figure 3.6, obtain the instructor s signature before continuing. FIGURE 3.6 Timing Diagram of a Clocked Set-Reset Flip-Flop Page - 3

4 PART FOUR. The Clocked D-Type Flip-Flop. Figure 3.7 illustrates the elimination of a stimulus input of the previous circuit through the insertion of an inverter between the SET input and the RESET input of the first flip-flop. This will cause the two inputs to always oppose each other. The first flip-flop will follow the data on the D input while the second is disabled. When the clock is enabled, the second flip-flop will latch with the data from the first stage. Figure 3.7 Clocked D-Type Flip-Flop Construct the circuit of Figure 3.7 using two SN7400s or a similar family device. You can use the unused NAND gates as an inverter by tying its two inputs together. The pin-out of the IC is indicated on page 6. Using the debounced logic switches to stimulate the D and CLOCK inputs, complete the timing diagram of Figure 3.8 below by indicating the resulting outputs of the flip-flop. After completing Figure 3.8, obtain the instructor s signature before continuing. Figure 3.8 Timing Diagram of a Clocked D-Type Flip-Flop Page - 4

5 PART FIVE. The Clocked JK-Type Flip-Flop. Figure 3.9 illustrates yet another modification of the clocked flip-flop. Note that the opposing outputs are tied back to the input buffer of the first stage. The effect is to cause the output to change state on the clock edge if both the J and K inputs are high. Other than this, the operation of the flip-flop is similar to the Set-Reset type. Figure 3.9 Clocked JK-Type Flip-Flop Construct the circuit of Figure 3.9 using two SN7400s or a similar family device. You can use the unused NAND gates as an inverter by tying its two inputs together. An SN7410 can be used for the two logic gates on the input buffer. The pin-out diagram for the SN7410 is on page 6. Using the debounced logic switches to stimulate the CK input, and two other logic switches to simulate the J and K inputs, complete the timing diagram of Figure 3.10 below by indicating the resulting outputs of the flip-flop. After completing Figure 3.10, obtain the instructor s signature before continuing. FIGURE 2.10 Timing Diagram of a Clocked JK-Type Flip-Flop Page - 5

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