How To Design A Combinational Circuit In A Computer Program

Transcription

1 Combinational Circuits in Computers (Examples) Combinational Logic Translates a set of Boolean n input variables ( or ) by a mapping function (using Boolean operations) to produce a set of Boolean m output variables ( or ). i f = F (i,i,, i n- ) i f = F (i,i,, i n- ) F i n- f m- = F m- (i,i,, i n- ) CS 6 Ward CS 6 Ward 2 esign of Combinational Circuits etermine input, output and the relationships connecting them Build truth table evelop K-map & simplify lter/simplify as necessary or desired erive Boolean function and circuit diagram CC esign Example F = if (BC) 2 3, otherwise Truth Table: B C F K-map: BC F = + BC B C F CS 6 Ward 3 CS 6 Ward 4

2 Multiplexers Eight-Input -Bit Multiplexer Multiplexer: combinational circuit with 2 n data inputs, n control inputs that select one of the data inputs as output Usage example: Loading the PC (Program Counter) from binary counter or instruction register or output from LU Example multiplexer: Eight-input multiplexer has 3 control inputs and 8 data inputs can be packaged in a 4-pin chip: 8 data inputs, 3 control inputs, output, ground, power F = BC + BC + BC 2 + BC 3 + BC 4 + BC 5 + BC 6 + BC 7 CS 6 Ward 5 CS 6 Ward 6 6-bit ddress PC Eight-Input -Bit Multiplexer F = BC + BC + BC 2 + BC 3 + BC 4 + BC 5 + BC 6 + BC 7 MUX can implement any Boolean function! CS 6 Ward 7 CS 6 Ward 8

3 MUX Implementation of F For example: F(,B,C,) = m (,4,5,8,,2,3) B C F B C F ecoders ecoder: a combinational circuit that takes an n-bit number as input and uses it to select one of 2 n output lines Usage example: To select one of many memory chips (see slide 2) CS 6 Ward 9 CS 6 Ward 3 8 Bit ecoder K-Byte ROM Memory = BC = BC 2-4 decoder controlling references to a memory consisting of four 256 x 8-bit RM chips: 2 = BC 3 = BC 4 = BC 5 = BC 6 = BC 7 = BC CS 6 Ward CS 6 Ward 2

4 8-Bit Shifter [] rithmetic circuit: 8-bit shifter with 8 data inputs ( - 7 ), one control input (shift left or right?, C) and 8 outputs. Right shift: becomes Left shift: becomes When C is shift right, C is shift left 8-Bit Shifter [2] Uses = & = & + = CS 6 Ward 3 CS 6 Ward 4 Comparator Circuit Comparator is a combinational circuit that compares 2 input words and produces if they are equal and if not Example circuit is a 4-bit comparator and uses 4 XOR gates and NOR Cost = 4 XOR, NOR, 2 inputs = 7 Half-dder rithmetic circuit: -bit half adder (doesn t have a carry as input) Can be used as basic block of a full-adder and chained together to create 8, 6, bit adders Sum = B CS 6 Ward 5 CS 6 Ward 6

5 Full-dder esign rithmetic circuit: -bit full-adder SUM: BC S = BC + BC + BC + BC Full-dder From SOP rithmetic circuit: -bit full-adder from Truth Table & K-Map Cost = 4 N, OR, 6 inputs = 2 C o : BC C o = B + C + BC Cost = 3 N, OR, 9 inputs = 3 CS 6 Ward 7 CS 6 Ward 8 Full-dder (2 Half-dders) rithmetic circuit: -bit full-adder (2 halfadders with carry in) Multi-Bit Ripple-Carry dder rithmetic circuit: (e.g., 4-bit adder) S = BC + BC + BC + BC = (B + B)C + (B + B)C = ( B)C + ( B)C = ( B) C Cost = 2 XOR, 2 N, OR, inputs = 5 C o = B + C + BC = B + (B+B)C + (+)BC = B + BC + BC + BC = B(+C) + (B + B)C = B + ( B)C CS 6 Ward 9 CS 6 Ward 2

6 Multi-Bit Carry-Select dder rithmetic circuits: (e.g., 32-bit adder) 3 6-bit adders, lower-half and 2 upperhalves (U, U) fed into U, fed into U. The correct upper half selected from lower half answer (one computation is wasted but it s still faster than ripple-carry adder) Replicate parallelism (have many upper halves) to get more speed (and more wasted computations) Multi-Bit Carry-Lookahead dder rithmetic circuits: Compute carry bits without reference to carry bits of previous stages C = B (no carry in) C = B + C + B C = B + B + B B C 2 = 2 B B + 2 B + 2 B B + B 2 B + B 2 B + B 2 B B Complexity and compute time increase as additional bits are added Typically done in 4-8 bit units CS 6 Ward 2 CS 6 Ward bit dder Using Four 8-Bit dders Simplified rithmetic Logic Unit (LU) rithmetic circuit: LU (rithmetic Logic Unit) Can compute N B, OR B, B, + B (add) Has 2 data inputs (, B), 2 control inputs (F, F ) to select of four functions above (N, OR, NOT, addition). So, 2 bit LU. In circuit on next slide, assume INV (inverse of ) is, EN (enable input ) and ENB (enable input B) are. CS 6 Ward 23 CS 6 Ward 24

7 Simplified LU Circuit CS 6 Ward 25