# Multipliers. Introduction

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1 Multipliers Introduction Multipliers play an important role in today s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various high speed, low power and compact VLSI implementation. The common multiplication method is add and shift algorithm. In parallel multipliers number of partial products to be added is the main parameter that determines the performance of the multiplier. To reduce the number of partial products to be added, Modified Booth algorithm is one of the most popular algorithms. To achieve speed improvements Wallace Tree algorithm can be used to reduce the number of sequential adding stages. urther by combining both Modified Booth algorithm and Wallace Tree technique we can see advantage of both algorithms in one multiplier. However with increasing parallelism, the amount of shifts between the partial products and intermediate sums to be added will increase which may result in reduced speed, increase in silicon area due to irregularity of structure and also increased power consumption due to increase in interconnect resulting from complex routing. On the other hand serial-parallel multipliers compromise speed to achieve better performance for area and power consumption. The selection of a parallel or serial multiplier actually depends on the nature of application. In this lecture we introduce the multiplication algorithms and architecture and compare them in terms of speed, area, power and combination of these metrics. Page of 39

2 Multiplication lgorithm The multiplication algorithm for an N bit multiplicand by N bit multiplier is shown below: Y= Y n- Y n-...y Y Y Multiplicand X= X n- X n-... X X X Multiplier Generally Yn-X Yn-X Yn-3X YX YX Yn-X Yn-X Yn-3X YX YX Yn-X Yn-X Yn-3X YX YX..... Yn-Xn- Yn-X n- Yn-3X n- Y= Y n- Y n-...y Y Y X= X n- X n-... X X X ================================================= YXn- YXn- Yn-Xn- Yn-Xn- Yn-3Xn- YXn- YXn Pn- Pn- Pn-3 P P P Example 4-bits 4-bits Page of 39

3 ND gates are used to generate the Partial Products, PP, If the multiplicand is N-bits and the Multiplier is M-bits then there is N* M partial product. The way that the partial products are generated or summed up is the difference between the different architectures of various multipliers. Multiplication of binary numbers can be decomposed into additions. Consider the multiplication of two 8-bit numbers and B to generate the 6 bit product P X B7 B6 B5 B4 B3 B B B B 6.B 5.B 4.B 3.B.B.B.B 7.B 6.B 5.B 4.B 3.B.B.B.B 7.B 6.B 5.B 4.B 3.B.B.B.B 7.B3 6.B3 5.B3 4.B3 3.B3.B3.B3.B3 7.B4 6.B4 5.B4 4.B4 3.B4.B4.B4.B4 7.B5 6.B5 5.B5 4.B5 3.B5.B5.B5.B5 7.B6 6.B6 5.B6 4.B6 3.B6.B6.B6.B6 7.B7 6.B7 5.B7 4.B7 3.B7.B7.B7.B7 Patial Products to be added P5 P4 P3 P P P P9 P8 P7 P6 P5 P4 P3 P P P The equation for the addition is: P(m n) (m)b(n) m n i j i j a. ib j Multiplication lgorithm If the LSB of Multiplier is, then add the multiplicand into an accumulator. Shift the multiplier one bit to the right and multiplicand one bit to the left. Stop when all bits of the multiplier are zero. rom above it is clear that the multiplication has been changed to addition of numbers. If the Partial Products are added serially then a serial adder is used with least hardware. It is possible to add all the partial products with one combinational circuit using a parallel multiplier. However it is possible also, to use compression technique then the number of partial products can be reduced before addition.is performed. Page 3 of 39

4 Serial Multiplier Where area and power is of utmost importance and delay can be tolerated the serial multiplier is used. This circuit uses one adder to add the m * n partial products. The circuit is shown in the fig. below for m=n=4. Multiplicand and Multiplier inputs have to be arranged in a special manner synchronized with circuit behavior as shown on the figure. The inputs could be presented at different rates depending on the length of the multiplicand and the multiplier. Two clocks are used, one to clock the data and one for the reset. first order approximation of the delay is O (m,n). With this circuit arrangement the delay is given as D =[ (m)n ] t fa. X: X: x 3 x x 3 x x x x x Y:y Y:y 3 y 3 y y y y y Input Input Sequence Sequence for for G: G: x x 3 x 3 x x x x x x 3 x x 3 x x x x x x x 3 x 3 x x x x x x x 3 x 3 x x x x x y y 3 y 3 3 y y 3 3 y y 3 3 y y 3 y y y y y y y y y y y y y y y y y y y y y y y Reset: Reset: Reset= G CLK d -bit REG q x y G x y x y Serial Register CLK CLK/(N) Slide 3 s shown the individual PP is formed individually. The addition of the PPs are performed as the intermediate values of PPs addition are stored in the D, circulated and added together with the newly formed PP. This approach is not suitable for large values of M or N. or snapshots of data movements please see the course website/slides of lecture 3. Page 4 of 39

5 Serial/Parallel Multiplier The general architecture of the serial/parallel multiplier is shown in the figure below. One operand is fed to the circuit in parallel while the other is serial. N partial products are formed each cycle. On successive cycles, each cycle does the addition of one column of the multiplication table of M*N PPs. The final results are stored in the output register after NM cycles. While the area required is N- for M=N. or snapshots of data transfer through this multiplier please see the course website/slides of lecture y y y y 3 x 3 x x x S S S S S pipelined version of an 8 bit multiplier is shown below. Page 5 of 39

6 Shift and dd Multiplier The general architecture of the shift and add multiplier is shown in the figure below for a 3 bit multiplication. Depending on the value of multiplier LSB bit, a value of the multiplicand is added and accumulated. t each clock cycle the multiplier is shifted one bit to the right and its value is tested. If it is a, then only a shift operation is performed. If the value is a, then the multiplicand is added to the accumulator and is shifted by one bit to the right. fter all the multiplier bits have been tested the product is in the accumulator. The accumulator is N (MN) in size and initially the N, LSBs contains the Multiplier. The delay is N cycles maximum. This circuit has several advantages in asynchronous circuits. To view data movements please see course website/slides of lecture 3. rray Multiplier Page 6 of 39

7 rray Multipliers rray multiplier is well known due to its regular structure. Multiplier circuit is based on add and shift algorithm. Each partial product is generated by the multiplication of the multiplicand with one multiplier bit. The partial product are shifted according to their bit orders and then added. The addition can be performed with normal carry propagate adder. N- adders are required where N is the multiplier length. 3 x B3 B B B C B x 3 B x B x B x B x 3 B x B x B x C sum sum sum sum B x 3 B x B x B x C sum sum sum sum B3 x 3 B3 x B3 x B3 x Inputs Internal Signals C sum sum sum sum Y7 Y6 Y5 Y4 Y3 Y Y Y Outputs Page 7 of 39

8 n example of 4-bit multiplication method is shown below: a 3 a a a = a 3 a a a b B = b 3 b b b a 3 a a a b C out our-bit dder C i n a 3 a a a b C out our-bit dder C in a 3 a a a b 3 C out our-bit dder C in Product (*B) lthough the method is simple as it can be seen from this example, the addition is done serially as well as in parallel. To improve on the delay and area the CRs are replaced with Carry Save dders, in which every carry and sum signal is passed to the adders of the next stage. inal product is obtained in a final adder by any fast adder (usually carry ripple adder). In array multiplication we need to add, as many partial products as there are multiplier bits. This arrangements is shown in the figure below Page 8 of 39

9 3 P 3 P P P P P P **P ij = i B j Total of 6 gates j B i B B C i. S i C i. S i C i. S i i 3 j 3 B B 3 P 3 P P P... P ij C i S i C i S i C i S i P 3 P 3 P 3 P 3... C i S i C i S i C i S i P C i S i C i S i C i S i R 7 R 6 R 5 R 4 R3 R R R Total rea = (N-) * M * rea Delay= (M-) Now as both multiplicand and multiplier may be positive or negative, s complement number system is used to represent them. If the multiplier operand is positive then essentially the same technique can be used but care must be taken for sign bit extension. Page 9 of 39

11 DD INVERT LL SIGN BITS * * * * * Ŝ X X X X X * * * * Ŝ X X X X X * * * Ŝ 3 X X X X X * * Ŝ 4 X X X X X * Ŝ 5 X X X X X Ŝ 6 X X X X X It is possible however to simplify this further and use the following template. Extend the sign of the first partial product row by bit and invert this bit. Invert all other sign bits of all partial products as shown below Extend sign bit and invert Invert all other sign bits * * * * Ŝ S XX X X X * * * * Ŝ X X X X X * * * Ŝ 3 X X X X X * * Ŝ 4 X X X X X * Ŝ 5 X X X X X Ŝ 6 X X X X X Page of 39

12 Below are some examples of this method Example - = * 3 = -6 = This is s Complement of 6 By sign extension method - = * 3 = * -6 Now, according to the algorithm, Sign bits This is s Complement of 6 Extended sign bit and inverted Inverted sign bits * This is s Complement of 6 The Diagram below shows the architecture of a 3 bit array adder. (Please note that the design is modified to take care of s complement numbers) Page of 39

13 rray Multiplier for a 3 bit number ( s complement numbers) Booth Multipliers It is a powerful algorithm for signed-number multiplication, which treats both positive and negative numbers uniformly. Page 3 of 39

15 then a is placed to the right most bit which gives the 3 digits are selected at a time with overlapping left most bit as follows: Table. Radix-4 Booth recoding X i X X i- Z i/ or example, an unsigned number can be converted into a signed-digit number radix 4: ( ) = ( ) 4 The Multiplier bit-pair recoding is shown in Table. Table Multiplier recoding *multiplicand *multiplicand Page 5 of 39

16 *multiplicand *multiplicand -*multiplicand -*multiplicand -*multiplicand -*multiplicand Here *multiplicand is actually the s complement of the multiplicand with an equivalent left shift of one bit position. lso, *multiplicand is the multiplicand shifted left one bit position which is equivalent to multiplying by. To enter *multiplicand into the adder, an (n)-bit adder is required. In this case, the multiplicand is offset one bit to the left to enter into the adder while for the low-order multiplicand position a is added. Each time the partial product is shifted two bit positions to the right and the sign is extended to the left. During each add-shift cycle, different versions of the multiplicand are added to the new partial product depends on the equation derived from the bit-pair recoding table above. Let s see some examples: Example : (3) (9) - (87) Example : Page 6 of 39

17 s complement of multiplicand Example 3: Shifted s complement (-3) (9) - (-87) (-3) (-9) - - (87) Comparison of Booth and shift and add methods Hardware implementation of Booth Once the partial products are generated then the addition process is very similar to the array multiplier. Usually carry save adders are used with the final sum added using a CR. Page 7 of 39

18 Since the Booth Method applies to s complement arithmetic, care must be taken to insure sign extensions are in place as shown in red dots in the following diagram. Several techniques exist that reduces this task with ready made templates. Once the table of the partial products are drawn, all the rows of the partial products have to be arithmetically extended to *N, where N is the length of the multiplicand. This is necessary to obtain correct results but it increases the capacitive load, the area and the computational time. Instead the template above can be used (Copied from book: dvanced Computer rithmetic Design, by M.J. lynn, S. Oberman, Wiley) to reduce the calculation. In the above template, there are 6 bit numbers. nd the 7 th bit is the sign bit. lso, the partial products on each row are entered as complement numbers. If complement numbers are used then the S entries Page 8 of 39

19 on the right side can be removed. Please note that the S bit is the sign bit of the booth encoding of that row) B B S S S S S S S S S S S S S S S S S 3 S 3 S 3 S 3 S 4 P Sign template P Sign extension Example of using the template: Let us multiply 5 * -35. sign bit = 5 B= -35 Now decode the multiplier - - Check these values B= - * 4 3 * 4 - * 4 * 4 = 35 Page 9 of 39

20 * * - * * - This is a ve number. Convert it = 875 Now in order to reduce computation and extra computing units, all the capacitances use the provided template as below Using the Template 5 * -35 Sign bit dd SS dd inverted S dd Inverted sign and add * dd Inverted sign bit * - * No sign bit * - This is a ve number. Convert it = 875 Page of 39

21 s - s s P 7 P 6 P 5 P 4 P 3 P P P P 9 P 8 P 7 P 6 P 5 P 4 P 3 P P P s - P 7 P 6 P 5 P 4 P 3 P P P P 9 P 8 P 7 P 6 P 5 P 4 P 3 P P P s s - P 7 P 6 P 5 P 4 P 3 P P P P 9 P 8 P 7 P 6 P 5 P 4 P 3 P P P s s - 3 P 7 3 P 6 3 P 5 3 P 4 3 P 3 3 P 3 P 3 P 3 P 9 3 P 8 3 P 7 3 P 6 3 P 5 3 P 4 3 P 3 3 P 3 P 3 P 3 s s - 4 P 7 4 P 6 4 P 5 4 P 4 4 P 3 4 P 4 P 4 P 4 P 9 4 P 8 4 P 7 4 P 6 4 P 5 4 P 4 4 P 3 4 P 4 P 4 P 4 s 3 s - 5 P 7 5 P 6 5 P 5 5 P 4 5 P 3 5 P 5 P 5 P 5 P 9 5 P 8 5 P 7 5 P 6 5 P 5 5 P 4 5 P 3 5 P 5 P 5 P 5 s 4 s - 6 P 7 6 P 6 6 P 5 6 P 4 6 P 3 6 P 6 P 6 P 6 P 9 6 P 8 6 P 7 6 P 6 6 P 5 6 P 4 6 P 3 6 P 6 P 6 P 6 s 5 s - 7 P 7 7 P 6 7 P 5 7 P 4 7 P 3 7 P 7 P 7 P 7 P 9 7 P 8 7 P 7 7 P 6 7 P 5 7 P 4 7 P 3 7 P 7 P 7 s 6 P 7 8 P 6 8 P 5 8 P 4 8 P 3 8 P 8 P 8 P 8 P 9 8 P 8 8 P 7 8 P 6 8 P 5 8 P 4 8 P 3 8 P 8 P 8 P 8 6 x 6 multiplier array with Booth encoding and sign-generation general example of 6x 6 bit multiplier using the given template is shown above. s 7 Optimized Wallace Tree Multiplier Several popular and well-known schemes, with the objective of improving the speed of the parallel multiplier, have been developed in past. Wallace introduced a very important iterative realization of parallel multiplier. This advantage becomes more pronounced for multipliers of bigger than 6 bits. In Wallace tree architecture, all the bits of all of the partial products in each column are added together by a set of counters in parallel without propagating any carries. nother set of counters then reduces this new matrix and so on, until a two-row matrix is generated. The most common counter used is the 3: counter which is a ull dder.. The final results are added using usually carry propagate adder. The advantage of Wallace tree is speed because the addition of partial products is now O (logn). block diagram of 4 bit Wallace Tree multiplier is shown in below. s seen from the block diagram partial products are added in Wallace tree block. The result of these additions is the final product bits and sum and carry bits which are added in the final fast adder (CR). Page of 39

22 x 4 y 4 x 3 y 4 x 4 y 3 x y 4 x 3 y 3 x 4 y x y 4 x y 3 x 3 y x 4 y x y 4 x y 3 x y x 3 y x 4 y x y 3 x y x y x 3 y x y x y x y x y x y x y P 9 P 8 P 7 P 6 P 5 P 4 P 3 P P P Since Wallace Tree is a summation method, it can be used in conjunction with array multiplier of any kind including Booth array. The diagram below shows the implementation of 8 bit squarer using the Wallace tree for compressing the addition process. Page of 39

23 n7 n6 n5 n4 n3 n n n n7 n6 n5 n4 n3 n n n n7n n6n n5n n4n n3n nn nn nn n7n n6n n5n n4n n3n nn nn nn n7n n6n n5n n4n n3n nn nn nn n7n3 n6n3 n5n3 n4n3 n3n3 nn3 nn3 nn3 n7n4 n6n4 n5n4 n4n4 n3n4 nn4 nn nn4 n7n5 n6n5 n5n5 n4n5 n3n5 nn5 nn5 nn5 n7n6 n6n6 n5n6 n4n6 n3n6 nn6 nn6 nn6 n7n7 n6n7 n5n7 n4n7 n3n7 nn7 nn7 nn7 C out n7n6 n7n5 n7n4 n7n3 n7n n7n n7n n6n n5n n4n n3n nn nn n n7 n6n5 n6n4 n6n3 n6n n6n n5n n4n n3n nn n n6 n5n4 n5n3 n5n n4n n3n n n5 n4n3 n3 n4 igure 4. Operation of 8 bit square Page 3 of 39

24 n7n4 n6n5 n6 n7n n6n3 n5n4 n7n n6n n5n3 n7n n6n n5n n6n n5n n4n n5n n4n n3n n3n nn n nn n n H C9 C C6 C4 n7n3 n6n4 n5 ms C6 n4n3 ms6 7 C9 5 3 n4n n3n C nn C 8 ms4 3 ms9 ms4 ms ms H C ms3 C C3 8 n3 C4 ms C 6 4 ms ms7 H C7 C7 4 C3 3 ms ms3 H n4 C 6 C5 4 ms5 H C4 9 C8 5 ms8 H C 6 H C5 7 C8 C 5 C3 7 n7n5 C5 9 n7n6 n7 C6 C7 S5 S4 S3 S S S S9 S8 S7 S6 S5 S4 S3 S S S igure 5. Wallace Tree structure of 8 bit square Page 4 of 39

25 3 bit multiplication using Booth and Wallace tree. Page 5 of 39

26 Summary In this section performance measures of multipliers discussed so far are summarized and compared. These results were obtained after synthesizing individual architectures targeting Xilinx PG 45XL-HQ4C. ll comparisons are based on the synthesis reports keeping one common base for comparison. We summarize rea (Total number of CLBs required), Delay and Power Consumption and also calculate Delay Power (DP), rea Power (P), rea Speed (T) and rea Speed (T ) product. rom the Table we can see that delay of Wallace tree multiplier and Combined Booth-Wallace tree multiplier is almost the same and is the least. Hence they are fastest among five multipliers. DP product is also the least for the above two multiplier and are a good choice for this performance measure. Serial Parallel multiplier is a best choice when speed is not important but reduced area and power consumption is of more interest and also for P and T product Serial Parallel multiplier is a good choice. However, one of the most important performance parameter is T. rom the table we see that Modified Booth-Wallace Tree multiplier is the best choice as far as T is concerned. The Serial Parallel multiplier which is a good choice for P and T product has worst performance for T. rray Multi plier Modified Booth Multiplier Wallace Tree Multiplier Modified Booth -Wallace Tree Multiplier rea Total CLB s (#) Maximum Delay D (ns) Twin Pipe Serial-Parallel Multiplier (7.56) * Power(mW) (at highest speed) Power P (mw) when delay = 7.56ns Delay Power Product (DP) (ns mw) (at88 ns) 3.36 (at 4ns) 3.95 (.4ns) 3.86 (at.43ns).89 (at 7.56ns) rea Power Product (P) (# mw) rea Delay Product (D) (# ns) rea Delay Product(D ) (# ns ) x x 5.67 x x 3 * 8 x x x.747 x x 6 * x 6 6 Page 6 of 39

27 _ ppendix Signed Number Multiplication. Introduction Direct two's complement array multiplication can perform "direct" multiplication of two's complement numbers without requiring the complementing stages, significantly speeds up the multiplication process. This appendix will discuss two direct two's complement multiplication algorithms and their implementation. These two direct two's complement multiplication algorithms are: ) Tri-section modified Pezaris two's complement multiplication ) Baugh-Wooley two's complement multiplication These two algorithms are generally used in systems where the operands are less than 6-bit. They are relatively simpler than Booth multiplier whose structure is based on recoding the 's complement operand in order to reduce the number of partial products to be added.. Tri-section modified Pezaris two's complement multiplier: _ In 's complement number representation, the most significant bit (MSB) is weighted negatively. In realizing such a system, Pezaris generalizes the full adders into four types. In type, which represents a normal adder, all three inputs x, y, z are weighted positively and the result lies in the range {,3}. This result is represented by a -bit binary number C S where C and S are also weighted positively. In the other three types there are some signals, indicated by the dots, that are weighted negatively. Listed below are four arithmetic equations that describe the input/output relationships of the four types of generalized full adders. Type : C S = X Y Z Type : C (-S) = X Y (-Z) Type : (-C) S = (-X) (-Y) Z Type 3: (-C) (-S) = (-X) (-Y) (-Z) These four arithmetic equations lead to the truth-table descriptions of the four generalized full adders given in the following table. Table: Truth Table Describing the our Types of Generalized ull dders ull dder Weighted Inputs Weighted Outputs Type X Y Z C S Type 3 - X - Y - Z - C - S Page 7 of 39

28 Truth Table Type X Y - Z C - S Type - X - Y Z - C S Truth Table One can easily derive the Boolean equations governing the four types of full adders from the table entries. Type or Type 3: S = X'Y'Z X'YZ' XY'Z' XYZ C = XY YZ ZX Type or Type : S = X'Y'Z X'YZ' XY'Z' XYZ C = XY YZ' Z'X Pezaris two's complement multiplier use mixture types of full adders. The schematic circuit diagram of a 5-by-5 Pezaris array multiplier is shown below: Page 8 of 39

29 X (a4) a3 a a a (b4) b3 b b b B (a4b) a3b ab ab ab (a4b) a3b ab ab ab (a4b) a3b ab ab ab a4b a3b ab ab ab (a4b3) a3b3 ab3 ab3 ab3 a4b4 (a4b3)(a4b)(a4b)(a4b) a4b a3b ab ab ab p9 p8 p7 p6 p5 p4 p3 p p p P a4b a3b ab ab ab a3b3 ab3 ab3 ab3 a4b3 a4 b4 a3b4 ab4 ab4 ab4 P9 P8 P7 P6 P5 P4 P3 P P P The schematic logic circuit diagram of a 5-by-5 Tri-section modified Pezaris two s complement array multiplier The examples of 5-by-5 Pezaris are shown below: multiplicand positive negative positive negative multiplier negative positive positive negative Page 9 of 39

30 X () () =3 = -5 () () a4b a3b ab ab ab () () () () () () = -65 a4b a4b a3b a3b ab ab ab ab ab ab a4b3 a3b3 ab3 ab3 ab3 a4 b4 a3b4 ab4 ab4 ab4 P9 P8 P7 P6 P5 P4 P3 P P P () X () () () = -5 =3 a4b a3b ab ab ab () () () () () () = -65 a4b a4b a3b a3b ab ab ab ab ab ab a4b3 a3b3 ab3 ab3 ab3 a4 b4 a3b4 ab4 ab4 ab4 P9 P8 P7 P6 P5 P4 P3 P P P Example of Tri-section modified Pezaris Two s Complement Multiplication Page 3 of 39

31 X () () =3 = 5 () () a4b a3b ab ab ab () () () () () () = 65 a4b a4b a3b a3b ab ab ab ab ab ab a4b3 a3b3 ab3 ab3 ab3 a4 b4 a3b4 ab4 ab4 ab4 P9 P8 P7 P6 P5 P4 P3 P P P () X () = -5 = -3 () () a4b a3b ab ab ab () () () () () () = 65 a4b a4b a3b a3b ab ab ab ab ab ab a4b3 a3b3 ab3 ab3 ab3 a4 b4 a3b4 ab4 ab4 ab4 P9 P8 P7 P6 P5 P4 P3 P P P Example of Tri-section modified Pezaris Two s Complement Multiplication 3. Baugh-Wooley two's complement multiplier: Baugh and Wooley have proposed an algorithm for direct two's complement array multiplication. The principal advantage of their algorithm is that the signs of all summands are positive, thus allowing the array to be constructed entirely with the conventional Type full adders. This uniform structure is very attractive for VLSI. The schematic circuit diagram of a 5-by-5 Baugh-Wooley array multiplier is shown below: Page 3 of 39

32 a4b' ab a3b ab ab a4b' a3b ab ab ab a4b' a3b ab ab ab a4b3' a3b3 ab3 ab3 ab3 a4' b4' a4b4 a3'b4 a'b4 a'b4 a'b4 a4 b4 P9 P8 P7 P6 P5 P4 P3 P P P The schematic logic circuit diagram of a 5-by-5 Baugh-Wooley two s complement array multiplier The examples of 5-by-5 Baugh-Wooley are shown below: multiplicand positive negative positive negative multiplier negative positive positive negative X a4 a3 a a a b4 b3 b b b B a4b' a3b ab ab ab a4b' a3b ab ab ab a4b' a3b ab ab ab a4b4 a4b3' a3b3 ab3 ab3 ab3 a4' a3'b4 a'b4 a'b4 a'b4 b4' a4 b4 p9 p8 p7 p6 p5 p4 p3 p p p P X =3 = -5 = -5 X =3 = -65 = -65 =3 = -3 X = 5 X = -5 = 65 = 65 Example of Baugh-Wooley Two s Complement Multiplication Page 3 of 39

33 4. Comparison ull dder Used Table: Direct two's complement multiplication n * n two's Complement rray Multiplier Tri-section Pezaris Baugh-Wooley dvantage Regular format array Irregular format array, two more rows Disadvantage Three type full adder uesd Only one type full adder uesd Type (n - 3n ) / n - n 3 Type (n - 3n ) / Type n - Type 3 Total n - n n - n 3 Total time delay (Multiply time) 4 nδ- Δ 4 nδ * Δ is the unit gate delay. 5. VHDL coding: s an example a 5-bit two's complement multiplication of Tri-section modified Pezaris and Baugh-Wooley are implemented by VHDL code and part of the simulation result are shown below: Page 33 of 39

34 6. PG Implementation: Implement Multipliers in Xilinx Virtex II PGs. Then indicate the critical path, compare the performance, area and power consumption. References: [] Kai Hwang Computer rithmetic: Principles, rchitecture, and Design John Wiley & Sons 979 [] S. D. Pezaris " 4-ns 7-Bit by 7-Bit rray Multiplier", IEEE Trans. on Computers, pp ,.br. 97 [3] C. Baugh y. Wooley " Two's Complement Parallel rray Multiplication lgorithm". IEEE Trans.on Computer, Vol.C-, Nº. Dic.973. ppendix B Examples of signed multiplication (When multiplier operand is positive) Example. - - = X 4 4 = -4 By Sign Extension method, X -4 Page 34 of 39

35 ccording to the extend and invert algorithm, X ns is -4 Ex -5-5 = X 4 4 = - By Sign Extension method, X s complement of - ccording to the algorithm of extend and invert method, Page 35 of 39

36 X in s complement Ex = X 3 3 = - By Sign Extension method, X ccording to the sign extend and invert algorithm, - in s complement X - in s complement Page 36 of 39

37 Ex = X = -44 By Sign Extension method, X -44 ccording to the sign extend and invert algorithm, X - 44 Page 37 of 39

38 Examples of Bth multiplication Example Using Booth algorithm multiply and B. = B=3 = Please note that both numbers are extended to cover or B and the B= sign bit (whichever is larger). * B = = = 4 = - = Now performing the addition we have - B= = (6) Now let us try B * = B= = Page 38 of 39

39 i S C 3 P. Now performing the addition we have = (6) Page 39 of 39

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