Questions 1. half adder sum. x y

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1 uestions uestion 4. : (Solution, p 4) raw two truth tales illustrating the outputs of a half-adder, one tale for the output and the other for the output. uestion 4. 2: (Solution, p 4) Fill in the truth tale at right for the following circuit. Ignore rows not included in the tale. a c half adder carry sum half adder carry sum x y uestion 4. 3: (Solution, p 4) What distinguishes the meanings of a half adder s inputs and outputs from a full-adder s? uestion 4. 4: (Solution, p 4) Using only four-it adders, construct an eight-it adder. Each four-it adder has two four-it inputs and one five-it output. Your eight-it adder should have two eight-it inputs and a one eight-it output (don t worry aotu the ninth output it). uestion 4.2 : (Solution, p 4) How is a flip-flop s ehavior different from a latch s ehavior? uestion 4.2 2: (Solution, p 4) The elow circuit at left includes two flip-flops. Recall that a flipflop s stored state remains unchanged as long as =. At the instant that switches to, its stored it switches to, and it retains this value until changes to again. c o a Say a user enters the sequence of inputs given in the tale at right, one after the other. Lael what the output of the circuit will settle into after each of the user s inputs.??????? uestion 4.2 3: (Solution, p 4) Suppose the upper flip-flop in the elow circuit were holding and the lower flip-flop held, while the input were. Then someody toggles the input five times (to, then, then, then, then ). Complete the tale to show how the output values would change.

2 uestions 2 x uestion 5. : (Solution, p 5) efine the fetch-execute cycle as it relates to a computer processing a program. Your definition should descrie the primary purpose of each phase. uestion 5. 2: (Solution, p 5) Explain in detail what HYMN does during the fetch phase of the fetchexecute cycle. uestion 5. 3: (Solution, p 5) Translate each of the following HYMN instructions into machine code. Express your answers in inary. a. HALT. A 4 c. LOA 2 d. JUMP 3 uestion 5. 4: (Solution, p 5) Suppose our computer starts with the following in memory. LOA A SUB STORE HALT HALT a. Show the hexadecimal values taken on y the registers as this program executes. (Stop once the computer executes a HALT instruction.) IR PC AC. What memory locations, if any, change? What values are stored in these locations? uestion 5.2 : (Solution, p 5) Suppose we were to start the computer with the following in memory. LOA STORE A STORE A STORE HALT

3 uestions 3 If the user typed multiples of 25 starting at 25 (25, then 5, then 75,... ) when prompted, what would the computer display? uestion 5.2 2: (Solution, p 5) Suppose we were to start the computer with the following in memory. If we repeatedly type the numer 32 computer halts? LOA A JPOS HALT when prompted, how many times would we type it efore the uestion 5.2 3: (Solution, p 5) What should we place into the computer s memory so that, when started, the computer displays the powers of two from to 64 efore halting?

4 Solutions 4 Solution 4. : (uestion, p ) Solution 4. 2: (uestion, p ) Solution 4. 3: (uestion, p ) A half adder has two inputs and outputs the sum of these two its, while a full adder has three inputs and outputs the sum of these three its. Solution 4. 4: (uestion, p ) The design of this circuit is similar in structure to the design of a full adder using half adders. a -3-3 a it adder 4-it adder 4-it adder out -3 out 4-7 Solution 4.2 : (uestion, p ) In a flip-flop, the memory value changes only at that instant that the input ecomes. In a latch, however, the memory value continues adopting any values given as long as its input is. (In a flip-flop, if the input changes while remains, the rememered value doesn t change. In a latch, however, the input changing while is results in a change to the rememered value.) Solution 4.2 2: (uestion, p ) Solution 4.2 3: (uestion, p )

5 Solutions 5 Solution 5. : (uestion, p 2) The fetch-execute cycle is the process y which a classical computer executes instructions. In the fetch phase, the computer determines the next instruction to e completed y fetching the instruction from memory. In the execute phase, the computer executes this instruction. Solution 5. 2: (uestion, p 2) It loads from memory from the address contained in the PC, storing the data found there into the IR. Solution 5. 3: (uestion, p 2) a.. c. d. Solution 5. 4: (uestion, p 2) a. IR 84 C5 E4 A5 PC AC 5 B 6. Memory location changes to hold 6 Solution 5.2 : (uestion, p 2).? 25 25? 5 75? 75-6 (This last output is somewhat tricky: In the last A instruction, the CPU computes, ut this exceeds the maximum eight-it two s-complement numer. So the computer wraps around ends up at.) Solution 5.2 2: (uestion, p 3) It would read from the user four times efore halting (with the AC progressing from to to to ). Solution 5.2 3: (uestion, p 3) Here is one possile solution. (Of course there are others.) LOA STOR STOR A JPOS HALT