UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #4 Solutions EECS141 PROBLEM 1: Shoot-Through Current In this problem, we will use the simplified transistor model we explored in Problem #4 of Homework #3 along with the parameters found in Table 3.2 of the text to perform a rough characterization of the shoot-through current (also known as short-circuit or crowbar current) of an inverter. Recall that in the simplified transistor model, the transistor s drain current is proportional to (V GS V T *). Note that while your final answers to this problem will be numerical (or plots with numbers on them), you should provide us with all of the equations you used to calculate your results. a) Ignoring output conductance (i.e., λ n = λ p = 0), plot the shoot-through (or shortcircuit) current as V IN is swept from 0 to V DD (=2.5V) of an inverter with W P = 2µm, W N = 1µm, and L =.24µm. The short-circuit current I is simply the smaller of I DP and I DN ; in a transient state, if one transistor has more current than the other, its excess current would flow into the load capacitance and charge/discharge the output. b) Now we are going to see how I vs. V IN changes as we alter the inverter s β ratio. For this problem, as you change β, you should leave the total transistor width constant (i.e., W P + W N = 3µm). All on the same plot, sketch I vs. V IN for β = 1, β = 2, and β = 3. c) If V DD = 2.5V and a 200MHz clock with rise and fall times of 200ps is applied to the input of the inverter, how much power is consumed by the shoot-through current? In comparison, if the total capacitance at the output of the inverter is 25fF, how much power is consumed by switching this capacitance? You can assume that the clock waveform is a purely linear ramp during the transition (i.e., for 0<t<t r, Vin = k r t).

2 Solutions: a) Using Matlab The shoot-through current in the graph above is the bolded portion where we find min(i N,I P ). b) Using Matlab

3 c) P = 2 E f where P is shoot-through power, E is shoot-through energy dissipated on every transition (the factor of 2 comes from the fact that the clock transitions twice every cycle), and f is the frequency of the clock. We calculate the shoot-through energy (which is the same on the rising and falling transitions) as follows: 200 ps E 0 ps i () t V DD dt Since i is a function of V in, we need to write V in as a function of time in order to compute the integral. V in = k r t + V in (0) Boundary conditions: V in (0) = 0, and V in = 2.5V at t = 200ps V in = (0.0125V/pS)t i NMOS (t) = k n W/L * (0.0125t V * tn )V VSATN i PMOS (t) = k p W/L * ( t V * tp )V VSATP Given the shape of the short-circuit current (seen in part a), there are three voltages (and times) of interest in computing this integral: 1) The input voltage and time at which the NMOS turns on (V tn *, t n_on ) 2) The input voltage and time at which the NMOS and PMOS currents are equal (V equal, t equal ) 3) The input voltage and time at which the PMOS turns off (V DD -V tp *, t p_off ) Calculating these times and voltages: t n_on = V tn */k r =.745V / V/ps = 59.6pS k n (W n /L) (V equal -V tn *) V vsatn = k p W p /L (V DD -V equal -V tp *) V vsatp V equal = V t equal = V equal /k r = V / V/ps = pS t p_off = (VDD - V tp *)/k r = 1.6V / V/ps = 128pS For t<t n_on and t>t p_off, the short-circuit current is zero. For t n_on <t<t equal, the current is set by the NMOS device, and for t equal <t<t p_off, the current is set by the PMOS device. So, the integral becomes: E ps 128ps = V DD [ i ( t) dt i ( t) dt] 59.6 ps NMOS ps PMOS Since the shoot-through current has a linear relationship with time, both integrals can be computed by calculating the area of the triangles they represent:

4 ps 1 i t dt ps ps i NMAX ps NMOS ( ) = ( ) ps 1 i t dt ps ps i PMAX ps PMOS ( ) = ( ) ' W i n ( * NMAX = i PMAX = kn Vequal Vtn) V VSATN = µ A L n From these areas we can now compute the shoot-through Energy. E 1 1 = 2 V DD [ ( )* ( )* ] 20 2 ps ps µ A + 2 ps ps µ A fj P = E * f = 4µ W E C 2 L V DD fj CL = = P CL = E CL * f = 31.25µ W ( P / P CL )*100 = 12.8% PROBLEM 2: Transistor Capacitances Throughout this problem, you should assume that the total gate capacitance of a minimum length transistor follows the curve shown on the top of the next page (all of the transistors in this problem are minimum length). However, keep in mind that as the transistor changes regions of operation, the way that the total capacitance is divided between the other terminals (source, drain, and body) changes. Note that all of the transistors in this problem are minimum channel length, and that V DD = 2.5V. All of your answers to this problem should be provided in terms of C ov, C ox, V T, and V DD. a) How much charge does it take to raise the gate of the transistor below from 0V to V DD?

5 b) How much charge is pulled through the gate to lower the drain of the transistor below from V DD to V DD /2? (Hint: using the unified model, what region of operation is the transistor in?) c) How much charge is pulled through the gate down to the source in order to lower the source of the transistor below from V DD to 0V? (Again, you should look for what region of operation the transistor is in where does most of the gate capacitance go to?) Solutions: a) Since we wish to find the charge given a capacitance vs. voltage characteristic, we use the following formula: dq = C dv In order to find the voltage and capacitance levels that contribute to the charge on the gate, we simply look at the function and find the area under the C G vs. V GS curve from a voltage of 0 to V DD. Keeping in mind that W = 1um: Q = (2C OV )(V T ) + (2C OV +C OX )(V DD -V T ) = 2C OV V DD + C OX (V DD -V T ) b) Now we examine the charge on the gate due to the gate-drain capacitance (C GD ). Since the value of C GD is dependent on the region of operation, we must determine what regions of operation are entered as the drain goes from V DD to V DD /2. In this case, min(v GT, V DS, V VSAT ) = V VSAT for all values of interest and we can use our velocity saturated region of operation for calculations. Remember that in velocity saturation the channel charge is not really controlled by the drain

6 voltage, and thus there is no contribution of C OX to C GD. The answer is thus as follows: Q = C GD (V DD -V DD /2) = C OV *V DD /2 c) Now we examine the charge on the gate as a function of the gate-source capacitance (C GS ). Examining the region of operation we see that we will always be in cutoff since V GS <= 0 < V T. Since in cutoff there is no channel charge there is no C OX contribution to C GS all of Cox is effective connected to the body of the transistor. So, the charge pulled through the gate down to the source is due only to the overlap capacitance: Q = C GS *V DD = C OV *V DD PROBLEM 3: Transistors With 2X Channel Length In this problem, we are going to see how doubling the channel length of a transistor affects various transistor parameters. You should use the unified transistor model from Lecture 5 and the parameters found in Table 3.2 of the text for this problem. For parts a) and b), your final answers should be numerical, but you should show all of the equations you use to arrive at these numbers. For parts c) and d), you should turn in the SPICE deck(s) you used for your simulation(s). a) If the transistor s channel length were doubled, what is the new V VSAT? b) What is the ratio of currents between a 2x Length NMOS and a 1x Length NMOS in the linear, saturated, and velocity saturated regimes? In the velocity saturated regime, what is the ratio of current when V GS = V DD = 2.5V? How about the ratio of currents between a 2x Length PMOS and a 1x Length PMOS? c) Using HSPICE and the capacitance calibration procedure described in the lecture, please find the linear input capacitance per µm that best matches the delay of an inverter with minimum channel length transistors (use W n = 1µm, W p = 2µm for the inverter). The discussion sessions will cover the syntax needed to perform optimizations in HSPICE (to find the best fit capacitance), so be sure to attend if you have not used this HSPICE feature before. d) Still using HSPICE and the same procedure, what is the linear input capacitance per µm that best matches the delay of an inverter made up of transistors with 2x the minimum channel length (but still with W n = 1µm and W p = 2µm)? Solutions: a) Our equation (as an approximation) of V VSAT is as follows:

7 V VSAT = L*E C If we double our channel length we can easily see that our V VSAT will be doubled. V VSAT-NEW /V VSAT-OLD = (2L)*E C /(L*E C ) = 2. Using parameters found in Table 3.2 we see that V VSATP = -2V and V VSATN = 1.26V b) Since there are 3 different current equations depending on region of operation we must see what doubling length will do to each region: Linear: NMOS Ratio: [kw/(2l)*(v GT -V DS /2)V DS ]/[kw/l*(v GT -V DS /2)V DS ] = 0.5 PMOS Ratio: same as NMOS => 0.5 Saturation: Just like the linear region, no other parameters depend on length so we have same results: NMOS Ratio = PMOS Ratio = 0.5 Velocity Saturation: Since V VSAT is affected (2x greater) with the change in channel length, we must look closely at how doubling channel length affects current in the velocity saturation regime. NMOS Ratio= [kw/(2l)*(v GT -(2V VSAT )/2)(2V VSAT ) ]/[kw/l*(v GT - V VSAT /2) V VSAT ] = [V GT V VSAT ]/(V GT -V VSAT /2) = (V GT 0.63)/(V GT ) When V GS = V DD = 2.5V, this ratio is PMOS Ratio= same symbolically as NMOS = [V GT V VSAT ]/(V GT - V VSAT /2) = (V GT 1)/(V GT - 0.5) When V GS = V DD = 2.5V, this ratio is c) and d) Below is the spice deck that allows you to find best-fit linear input capacitance per µm of an inverter. Using this deck, the results are: Best Fit Lin Cap with 1x L = fF/µm Best Fit Lin Cap with 2x L = fF/µm ** Homework #4 Problem 3 ***.LIB '/home/ff/ee141/models/g25.mod' TT.param length=0.24u * Change this parameter to 0.48u for 2x length inverter.param Supply=2.5

8 * Inverter SUBCKT Definition.SUBCKT inv in out vdd gnd M1 out in vdd vdd pmos W=2u L='length' M2 out in gnd gnd nmos W=1u L='length'.ENDS *Voltage Sources VVDD vdd 0 'Supply' VSTEP vstep 0 PULSE ( p 1p 1p 5n 10n) ***Main Deck**** Xstage1 vstep out1 vdd 0 inv M=1 Xstage2 out1 out2 vdd 0 inv M=4 Xstage3 out2 out3 vdd 0 inv M=16 Xstage4 out3 out4 vdd 0 inv M=64 Xcalstage1 vstep capout1 vdd 0 inv M=1 Xcalstage2 capout1 capout2 vdd 0 inv M=4 CL capout2 0 'CperMicron*3*16' **Measure Statements.measure invr + TRIG v(out1) VAL='Supply/2' FALL=1 TARG v(out2) VAL='Supply/2' RISE=1.measure capr + TRIG v(capout1) VAL='Supply/2' FALL=1 TARG v(capout2) VAL='Supply/2' + RISE=1.measure invf + TRIG v(out1) VAL='Supply/2' RISE=1 TARG v(out2) VAL='Supply/2' FALL=1.measure capf + TRIG v(capout1) VAL='Supply/2' RISE=1 TARG v(capout2) VAL='Supply/2' + FALL=1.measure errorr param='invr - capr' goal=0.measure errorf param='invf - capf' goal=0 * Analysis.param CperMicron=optrange(2f, 1f, 3.5f).model optmod opt itropt=30.tran 1p 20n SWEEP OPTIMIZE = optrange RESULTS=errorR,errorF MODEL=optmod.measure CperMic param = 'CperMicron'.end

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