THE INVERTER DYNAMICS

Transcription

1 Dynamic Behavior THE IVERTER DYAMIC Propagation Delay, T p Defines how quickly output is affected by input Measured between 5% transition from input to output t plh defines delay for output going from low to high t phl defines delay for output going from high to low Overall delay, t p, defined as the of t plh and t phl [Adapted from Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] Dynamic Behavior Delay Definitions Rise and fall time, T r and T f Defines slope of the signal Defined between the % and 9% of the signal swing Propagation delay and rise and fall times affected by the fan-out due to larger capacitance loads 5% t phl t plh t 9% 5% % t t f t r The Ring Oscillator Ring Oscillator A standard method is needed to measure the gate delay It is based on the ring oscillator t p >> t f + t r for proper operation v v v v v4 v5 v v v5 T = t p

2 Power Dissipation Power Dissipation Power consumption determines heat dissipation and energy consumption Power influences design decisions: packaging and cooling width of supply lines power-supply capacity # of transistors integrated on a single chip Power requirements make high density bipolar ICs impossible (feasibility, cost, reliability) upply-line sizing Battery drain, cooling Power Dissipation Power Dissipation P peak = static power + dynamic power Dynamic power: (dis)charging capacitors temporary paths from VDD to V proportional to switching frequency tatic power: static conductive paths between rails leakage increases with temperature Propagation delay is related to power consumption t p determined by speed of charge transfer fast charge transfer => fast gate fast gate => more power consumption Power-delay product (PDP) quality measure for switching device PDP= energy consumed /gate / switching event measured using ring oscillator Power Dissipation CMO Inverter: teady tate Response upply-line sizing Battery drain, cooling Energy consumed /gate /switching event CMO technology: o path exists between VDD and V in steady state o static power consumption! (ideally) Main reason why CMO replaced MO in early 8 s MO technology: Has MO pull-up device that is always O Creates voltage divider when pull-down is O Power consumption puts upper bound on (# devices / chip)

3 CMO Inverter Load Characteristics Voltage Transfer Characteristic G D D V out G PMO Load Lines CMO Inverter Load Lines I Dn Vin = +VGp I Dn = - I Dp = +V Dp G D PMO X.5-4 = V MO =.5V I Dp VGp=- V Gp=-5 V Dp = = = +V Gp I Dn = - I Dp G I Dn D I Dn Vin = = V Dp = +V Dp I Dn (A) =.5V.5 =.V =.V =.5V = V =.5V = V Vin =.5V.5 =.5V =.V =.V =.5V =.5V = V (V).5um, /L n =.5, /L p = 4.5, =.5V, V Tn =.4V, V Tp = -.4V (V) CMO Inverter VTC MO off PMO res MO sat PMO res MO sat PMO sat MO res PMO sat MO res PMO off (V) pmo nmo Cutoff - = V G > V T = V G < V T Regions of operations For nmo and pmo In CMO inverter Linear - =V G < V T - =V GD < V T =V G > V T - =V GD > V T G G D D aturation - =V G > V T - =V GD >V T =V G > V T - =V GD < V T

4 CMO Inverter Load Characteristics For valid dc operating points: current through MO = current through PMO => dc operating points are the intersection of load lines All operating points located at high or low output levels => VTC has narrow transition zone high gain of transistors during switching transistors in saturation high transconductance (g m ) high output resistance (voltage controlled current source) Voltage Transfer Characteristic witching Threshold V M where = (both PMO and MO in saturation since V D = V G ) V M r /( + r) where r = k p V DATp /k n V DATn witching threshold set by the ratio r, which compares the relative driving strengths of the PMO and MO transistors ant V M = / (to have comparable high and low noise margins), so want r (/L) p k n V DATn (V M -V Tn -V DATn /) = (/L) n k p V DATp ( -V M +V Tp +V DATp /) witch Threshold Example In.5 µm CMO process, using parameters from table, =.5V, and minimum size MO ((/L) n of.5) V T (V) γ(v.5 ) V DAT (V) k (A/V ) MO x -6 PMO x -6 λ(v - ).6 -. (/L) p 5 x -6.6 (.5.4.6/) = x x (/L) n - x -6 =.5 -. (.5.4./) (/L) p =.5 x.5 = 5.5 for a V M of.5v V M (V) imulated Inverter V M ~.4 (/L) p /(/L) n ote: x- axis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to,.5 and gives V M s of.v,.8v, and.v Increasing the width of the PMO moves V M towards V OL = GD oise Margins Determining V IH and V IL V OH = VIL V M A piece-wise linear approximation of VTC VIH By definition, V IH and V IL are where d /d = - (= gain) M H = - V IH M L = V IL - GD Approximating: V IH = V M - V M /g V IL = V M + ( - V M )/g o high gain in the transition region is very desirable 4

5 CMO Inverter VTC from imulation Gain Determinates (V) (V).5um, (/L) p /(/L) n =.4 (/L) n =.5 (min size) =.5V V M.5V, g = -7.5 V IL =.V, V IH =.V M L = M H =. (actual values are V IL =.V, V IH =.45V M L =.V & M H =.5V) Output resistance low-output =.4kΩ high-output =.kω gain Gain is a strong function of the slopes of the currents in the saturation region, for = V M (+r) g (V M -V Tn -V DATn /)(λ n - λ p ) Determined by technology parameters, especially λ. Only designer influence through supply voltageand V M (transistor sizing). Impact of Process Variation caling the upply Voltage (V) Bad PMO Good MO (V) Good PMO Bad MO ominal process variations (mostly) cause a shift in the switching threshold (V),5,5,5,5 Gain=-,5,,5,,5,5,5 (V) (V) Device threshold voltages are kept (virtually) constant (V),,5, Device threshold voltages are kept (virtually) constant witch Model of Dynamic Behavior Propagation Delay R p R n = = Gate response time is determined by the time to charge through R p (discharge through R n ) 5

6 hat is the Inverter Driving? CMO Inverter Propagation Delay Approach M C db C g4 M4 t phl = V swing / C gd I av M C db C w Interconnect C g M I av ~ k n Fanout implified Model = CMO Inverter Propagation Delay Approach CMO Inverter: Transient Response t phl = f(r on.) How can the designer build a fast gate? t phl = f(r on * ) =.69 R on Keep output capacitance,, small low fan-out R on.5.6 V out ln(.5) = V t /( R on ) OH e keep interconnections short (floor-plan your layout!) Decrease on-resistance of transistor increase /L ratio make good contacts (slight effect) = R on t MO Transistor mall ignal Model Determining V IH and V IL G v gs + - g m v gs r o D Define V IH and V IL are based on derivative of VTC equal to - 6

7 (V).5.5? Transient Response t t phl plh t (sec) x - t p =.69 (R eqn +R eqp )/ (V) Inverter Transient Response tphl t f x - t (sec) t plh t r =.5V.5µm /L n =.5 /L p = 4.5 R eqn = kω (.5) R eqp = kω ( 4.5) t phl = 6 psec t plh = 9 psec so t p =.5 psec From simulation: t phl = 9.9 psec and t plh =.7 psec t p (normalized) Delay as a function of V (V) DD t p (sec) x izing Impacts on Delay for a fixed load The majority of the improvement is already obtained for = 5. izing factors larger than barely yield any extra gain (and cost significantly more area). self-loading effect (intrinsic capacitance dominates) PMO/MO Ratio Effects Input ignal Rise/Fall Time t p (sec) x 5 - t plh 4,5 4,5 t phl t p 4 5 β = (/L p )/(/L n ) β of.4 (= kω/ kω) gives symmetrical response β of.6 to.9 gives optimal performance In reality, the input signal changes gradually (and both PMO and MO conduct for a brief time). This affects the current available for charging/discharging and impacts propagation delay. t p increases linearly with increasing input rise time, t r, once t r > t p t r is due to the limited driving capability of the preceding gate t p (sec) x t s (sec) 8 for a minimum -size inverter with a fan-out of a single gate x - 7

8 CMO Inverter: Four Views Inverter izing V dd Gnd Logic Transistor Layout Physical CMO Inverter izing Inverter Delay metal metal pdiff metal-diff via Out In metal-poly via polysilicon PMO (4/.4 = 6/) MO (/.4 = 8/) Minimum length devices, L=.5µm Assume that for P = = same pull-up and pull-down currents approx. equal resistances R = R P approx. equal rise t plh and fall t phl delays Analyze as an RC network P R P = Runit Runit = R = R unit unit GD ndiff metal-metal via Delay (D): t phl = (ln ) R t plh = (ln ) R P Load for the next stage: C gin = Cunit unit Inverter with Load Inverter with Load Delay C P = C unit Delay R C int R Load ( ) C = C unit Load t p = k R k is a constant, equal to.69 Assumptions: no load -> zero delay unit = Delay = kr (C int + ) = kr C int + kr = kr C int (+ /C int ) = Delay (Internal) + Delay (Load) 8

9 Delay ~ R t p = kr Delay Formula C int ( C + C ) int ( ) ( ) + C L L / C int = t p C int = γc gin withγ f = /C gin - effective fanout R = R unit / ; C int =C unit t p =.69R unit C unit + f / γ Inverter Chain Real goal is to minimize the delay through an inverter chain In C g, the delay of the j-th inverter stage is t p,j = t p ( + C g,j+ /(γc g,j )) = t p ( + f j / γ) and t p = t p + t p t p so t p = t p,j = t p ( + C g,j+ /(γc g,j )) If is given» How should the inverters be sized?» How many stages are needed to minimize the delay? Out Apply to Inverter Chain In Out t p = t p + t p + + t p C gin, j + t pj ~ RunitCunit + γcgin, j C gin, j+ t p = t p j t, = p Cgin + + = C j i C,, = = γ gin, j L Optimum Delay and umber of tages hen each stage is sized by f and has same eff. fanout f: f = F = C Effective fanout of each stage: Minimum path delay p f = F t = t + p L / Cgin, ( F /γ ) Example Optimal umber of Inverters In C f f Out = 8 C hat is the optimal value for given F (=f )?» if the number of stages is too large, the intrinsic delay dominates» if the number of stages is too small, the effective fanout dominates /C has to be evenly distributed across = stages: f = 8 = The optimum is found by differentiating the minimum delay divided by the number of stages and setting the result to, For γ = (ignoring self -loading) = ln (F) and the effective-fan out becomes f = e =.788 9

10 t Optimum umber of tages Optimum Effective Fan-Out 5 7 For a given load, and given input capacitance C in Find optimal sizing f t = t p C = F C = f C p t p f L t ln F ( ) + = f / p γ F / γ + γ ln f ln f t = p For γ =, f = e, = lnf in lnf with = ln f ln F ln f γ γ ln f in f = f = exp+ ( γ f ) F op γ Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area).» Common practice to use f = 4 (for γ = )» But too manystages has a substantial negative impact on delay normalized delay f Example of Inverter (Buffer) taging Impact of Buffer taging for Large C g, = = 64 C g, 8 C g, = = 64 C g, 4 6 C g, = = 64 C g, C g, = = 64 C g, f t p F (g = ),, Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads. Unbuffered, Two tage Chain Opt. Inverter Chain Design Challenge Keep signal rise times smaller than or equal to the gate propagation delays.» good for performance» good for power consumption Power Dissipation Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in high-performance designs - slope engineering.

11 Dynamic Power Dissipation Modification for Circuits with Reduced wing Vdd V dd V dd Vin Vout V dd -V t Energy/transition = CL * Vdd Power = Energy/transition * f = CL * Vdd * f E = V dd ( V dd V t ) ot a function of transistor sizes! eed to reduce CL, Vdd, and f to reduce power. Can exploit reduced swing to lower power (e.g., reduced bit-line swing in memory) ode Transition Activity and Power hort Circuit Currents Consider switching a CMO gate for clock cycles Vdd E = V dd n ( ) Vin Vout E : the energy consumed for clock cycles n( ): the number of -> transition in clock cycles CL E P avg = lim f n ( ) clk lim = C V dd f clk L α n = lim ( ) IVDD (ma ).5..5 P avg = α C L V dd f clk.... Vin (V) How to keep hort-circuit Currents Low? Minimizing hort-circuit Power Vdd =. 5 4 P norm Vdd =.5 Vdd = t sin /t sout hort circuit current goes to zero if t fall >> t rise, but can t do this for cascade logic, so...

12 Leakage Reverse-Biased Diode Leakage Vdd GATE Vout Drain Junction Leakage ub-threshold Current ub-threshold current one of most compelling issues in low-energy circuit design! p + p+ + - V dd I DL = J A Reverse Leakage Current J = - pa/m m at 5 deg C for.5m m CMO J doubles for every 9 deg C! ubthreshold Leakage Component tatic Power Consumption Vdd I stat =5V Pstat = P(In=).V dd. Istat asted energy hould be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps) Principles for Power Reduction Prime choice: Reduce voltage!» Recent years have seen an acceleration in supply voltage reduction» Design at very low voltages still open question (.6.9 V by!) Reduce switching activity Reduce physical capacitance» Device izing: for F= f opt (energy)=.5, f opt (performance)=4.47 Impact of Technology caling

13 Goals of Technology caling Technology caling Make things cheaper:» ant to sell more functions (transistors) per chip for the same money» Build same products cheaper, sell the same part for less money» Price of a transistor has to be reduced But also want to be faster, smaller, lower power Goals of scaling the dimensions by %:» Reduce gate delay by % (increase operating frequency by 4%)» Double transistor density» Reduce energy per transition by 65% (5% power 4% increase in frequency Die size used to increase by 4% per generation Technology generation spans - years Technology Generations Technology Evolution ( data) International Technology Roadmap for emiconductors Year of Introduction Technology node [nm] upply [V] iring levels Max frequency [GHz],Local-Global Max m P power [] Bat. power [] ode years: 7/65nm, /45nm, /nm, 6/nm Technology Evolution (999) ITR Technology Roadmap Acceleration Continues

14 Technology caling () Technology caling () Minimum Feature ize (micron) Year Minimum Feature ize umber of components per chip Technology caling () Technology caling Models t p decreases by %/year 5% every 5 years! Full caling (Constant Electrical Field) ideal model dimensions and voltage scale together by the same factor Fixed Voltage caling most common model until recently only dimensions scale, voltages remain constant Propagation Delay General caling most realistic for todays situation voltages and dimensions scale with different factors caling Relationships for Long Channel Devices Transistor caling (velocity-saturated devices) 4

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