Lecture 250 Measurement and Simulation of Op amps (3/28/10) Page 250-1

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1 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 LECTURE 5 SIMULATION AND MEASUREMENT OF OP AMPS LECTURE ORGANIZATION Outline Introduction Open Loop Gain CMRR and PSRR A general method of measuring A vd, CMRR, and PSRR Other op amp measurements Simulation of a TwoStage Op Amp Op amp macromodels Summary CMOS Analog Circuit Design, nd Edition Reference Pages 4 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 INTRODUCTION Simulation and Measurement Considerations Objectives: The objective of simulation is to verify and optimize the design. The objective of measurement is to experimentally confirm the specifications. Similarity between Simulation and Measurement: Same goals Same approach or technique Differences between Simulation and Measurement: Simulation can idealize a circuit All transistor electrical parameters are ideally matched Ideal stimuli Measurement must consider all nonidealities Physical and electrical parameter mismatches Nonideal stimuli Parasistics

2 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 OPEN LOOP GAIN Simulating or Measuring the OpenLoop Transfer Function of the Op Amp Circuit (Darkened op amp identifies the op amp under test): Simulation: This circuit will give the voltage transfer function curve. This curve should identify:.) The linear range of operation.) The gain in the linear range.) The output limits 4.) The systematic input offset voltage 5.) DC operating conditions, power dissipation v V OS IN v OUT Fig. 4 6.) When biased in the linear range, the smallsignal frequency response can be obtained 7.) From the openloop frequency response, the phase margin can be obtained (F = ) Measurement: This circuit probably will not work unless the op amp gain is very low. Lecture 5 Measurement and Simulation of Op amps (/8/) Page 54 A More Robust Method of Measuring the OpenLoop Frequency Response Circuit: v IN v OUT C R Resulting ClosedLoop Frequency Response: db Av() Fig. 4 Op Amp Open Loop Frequency Response db RC Av() RC Make the RC product as large as possible. log (w) Fig. 4

3 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 55 CMRR AND PSRR Simulation of the CommonMode Voltage Gain V OS v out v cm Fig Make sure that the output voltage of the op amp is in the linear region. Divide (subtract db) the result into the openloop gain to get CMRR. Lecture 5 Measurement and Simulation of Op amps (/8/) Page 56 Simulation of CMRR of an Op Amp None of the above methods are really suitable for simulation of CMRR. Consider the following: V cm V V cm V V V A v (V V ) V cm V cm ±A c V cm V V = A v (V V ) ±A cm = AvV out ± A cm V cm Fig = ±A cm A V cm ±A cm v A V cm v CMRR = A v A cm = V cm

4 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 57 Direct Simulation of PSRR Circuit: V dd V V A v (V V ) V V ss = V ss V ±A dd V dd Fig = A v (V V ) ±A dd V dd = Av ± A dd V dd = ±A dd A v V dd ±A dd A v V dd PSRR = A v A dd = V dd and PSRR = A v A ss = V ss Works well as long as CMRR is much greater than. Lecture 5 Measurement and Simulation of Op amps (/8/) Page 58 A GENERAL METHOD OF MEASURING A VD, CMRR, AND PSRR General Principle of the Measurement Circuit: v OS kω kω kω v SET kω kω v OUT = v SET Ω v I v OUT v SET "Op Amp" "Op Amp" 749 The amplifier under test is shown as the darkened op amp. Principle: Apply the stimulus to the output of the op amp under test and see how the input responds. Note that: v OUT = v SET and v I v OS

5 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 59 Measurement of OpenLoop Gain Measurement configuration: kω V os kω kω A vd = V id = V i V os V i Ω V i 67 Therefore, A vd = V os Sweep as a function of frequency, invert the result and multiply by to get A vd (j ). Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 Measurement of CMRR Measurement Configuration: Note that the whole amplifier is stimulated by V icm while the input responds to this change. The definition of the commonmode rejection ratio is CMRR = A vd A cm = (v out/v id ) (v out /v icm ) However, in the above circuit the value of v out Ω is the same so that we get CMRR = v icm v id But v id = v i and v os v i = v id v id = v os Substituting in the previous expression gives, CMRR = v icm v os = v icm v os Make a frequency sweep of V icm, invert the result and multiply by to get CMRR. v os kω v i kω kω v OUT v icm v icm Fig. 48

6 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 Measurement of PSRR Measurement Configuration: The definition of the positive power supply rejection ratio is PSRR = A vd A cm = (/V id ) ( /V dd ) However, in the above circuit the value of is the same so that we get PSRR = V dd V id But V id = V i and V os V i = V id V id = V os Substituting in the previous expression gives, PSRR = V dd V os = V dd V os Make a frequency sweep of V dd, invert the result and multiply by to get PSRR. (Same procedure holds for PSRR.) V os kω Ω V i 749 kω kω V dd V ss Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 OTHER OP AMP MEASUREMENTS Simulation or Measurement of ICMR v OUT v IN I DD C I L SS v OUT ICMR v IN Also, monitor I DD or I SS. Fig.4 Initial jump in sweep is due to the turnon of M5. Should also plot the current in the input stage (or the power supply current).

7 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 Measurement or Simulation of Slew Rate and Settling Time v in I DD v out Volts vin Peak Overshoot SR SR Settling Time Feedthrough Settling Error Tolerance vout t Fig. 44 If the slew rate influences the small signal response, then make the input step size small enough to avoid slew rate (i.e. less than.5v for MOS). Lecture 5 Measurement and Simulation of Op amps (/8/) Page 54 Phase Margin and Peak Overshoot Relationship It can be shown (Appendix C of the text) that: Phase Margin (Degrees) = cos[ 4 4 ] Overshoot (%) = exp 8 7 For example, a 5% overshoot corresponds to a phase margin of approximately 64. Phase Margin (Degrees) Phase Margin Overshoot 5. Overshoot (%) ζ= 749 Q

8 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 55 SIMULATION OF A TWOSTAGE CMOS OP AMP Example 5 Simulation of a TwoStage CMOS Op Amp An op amp designed using the procedure described in Lecture is to be simulated by SPICE. The device parameters to be used are those of Tables. and. of the textbook CMOS Analog Circuit Design. μa 4.5μm μm v in M8 5μm μm M M μm μm M5 =.5V M4 5μm μm μm μm μa 4.5μm μm M =.5V C c = pf 95μA M6 M7 94μm μm 4μm μm v out = pf Fig. 46 The specifications of this op amp are as follows where the channel length is to be μm and the load capacitor is = pf: Av > V/V =.5V =.5V GB = 5MHz SR > V/μs 6 phase margin range = ±V ICMR = to V P diss mw Lecture 5 Measurement and Simulation of Op amps (/8/) Page 56 Example 5 Continued Bulk Capacitance Calculation: If the values of the area and perimeter of the drain and source of each transistor are known, then the simulator will calculate the values of C BD and C Bs. Since there is no layout yet, we estimate the values of the area and perimeter of the drain and source of each transistor as: AS = AD W[L L L] PS = PD W [L L L] where L is the minimum allowable distance between the polysilicon and a contact in the moat (μm), L is the length of a minimumsize square contact to moat (μm), and L is the minimum allowable distance between a contact to moat and the edge of the moat (μm). (These values will be found from the physical design rules for the technology). For example consider M: AS = AD = (μm)x(μmμmμm) = 8μm PS = PD = xμm x6μm = 9μm

9 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 57 Example 5 Continued Op Amp Subcircuit: v in 8 6 v out 9 Fig. 47.SUBCKT OPAMP M 4 NMOS W=U L=U AD=8P AS=8P PD=8U PS=8U M 5 NMOS W=U L=U AD=8P AS=8P PD=8U PS=8U M PMOS W=5U L=U AD=9P AS=9P PD=4U PS=4U M PMOS W=5U L=U AD=9P AS=9P PD=4U PS=4U M NMOS W=4.5U L=U AD=7P AS=7P PD=U PS=U M PMOS W=94U L=U AD=564P AS=564P PD=U PS=U M NMOS W=4U L=U AD=84P AS=84P PD=4U PS=4U M NMOS W=4.5U L=U AD=7P AS=7P PD=U PS=U CC 5 6.P.MODEL NMOS NMOS VTO=.7 KP=U GAMMA=.4 LAMBDA=.4 PHI=.7 MJ=.5 MJSW=.8 CGBO=7P CGSO=P CGDO=P CJ=77U CJSW=8P LD=.6U TOX=4N.MODEL PMOS PMOS VTO=.7 KP=5U GAMMA=..57 LAMBDA=.5 PHI=.8 MJ=.5 MJSW=.5 CGBO=7P CGSO=P CGDO=P CJ=56U CJSW=5P LD=.4U TOX=4N IBIAS 8 7 U.ENDS Lecture 5 Measurement and Simulation of Op amps (/8/) Page 58 Example 5 Continued PSPICE Input File for the OpenLoop Configuration: EXAMPLE 5 OPEN LOOP CONFIGURATION.OPTION LIMPTS= VIN DC AC. VDD 4 DC.5 VSS 5 DC.5 VIN DC CL P X 4 5 OPAMP. (Subcircuit of previous slide)..op.tf V() VIN.DC VIN.5.5 U.PRINT DC V().AC DEC MEG.PRINT AC VDB() VP().PROBE (This entry is unique to PSPICE).END

10 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 59 Example 5 Continued Openloop transfer characteristic:.5 V OS vout(v) v IN (mv) Fig. 48 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 Example 5 Continued Openloop transfer frequency response: 8 Magnitude (db) Phase Margin GB GB Frequency (Hz) Frequency (Hz) Fig Phase Shift (Degrees)

11 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 Example 5 Continued Input common mode range: EXAMPLE 5 UNITY GAIN CONFIGURATION..OPTION LIMPTS=5 VIN PWL( N N U.U 4U 4.U. 6U. 6. U. 8U. 8.U. U.) VDD 4 DC.5 AC. VSS 5 DC.5 CL P X 4 5 OPAMP 4. (Subcircuit of Table 6.6)..DC VIN.5.5..PRINT DC V().TRAN.5U U N.PRINT TRAN V() V().AC DEC MEG.PRINT AC VDB() VP().PROBE (This entry is unique to PSPICE).END Note the usefulness of monitoring the current in the input stage to determine the lower limit of the ICMR. vout (V) v in ID(M5) Subckt. 4 5 Input CMR v out Fig. 6.66A v IN (V) Fig. 4 4 ID(M5) μa Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 Example 5 Continued Positive PSRR: PSRR(jω) db Arg[PSRR(jω)] (Degrees) Frequency (Hz) Frequency (Hz) Fig. 4 This PSRR is poor because of the Miller capacitor. The degree of PSRR deterioration will be better shown when compared with the PSRR.

12 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 Example 5 Continued Negative PSRR: PSRR(jω) db 8 6 PSRR Frequency (Hz) Arg[PSRR(jω)] (Degrees) Frequency (Hz) Fig. 4 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 54 Example 5 Continued Largesignal and smallsignal transient response:.5.5. v in (t) Volts.5 v out (t) Volts.5 v out (t).5 v in (t) Time (Microseconds) Why the negative overshoot on the slew rate? If M7 cannot sink sufficient current then the output stage slews and only responds to changes at the output via the feedback path which involves a delay. Note that dv out /dt V/.μs = 6.67V/μs. For a pf capacitor this requires 66.7μA and only 95μA66.7μA = 8μA is available for C c. For the positive slew rate, M6 can provide whatever current is required by the capacitors and can immediately respond to changes at the output Time (Microseconds) Fig. 44 VBias C c M6 i Cc i CL v dv out out dt 95μA M7 Fig. 45

13 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 55 Example 5 Continued Comparison of the Simulation Results with the Specifications of Example 5: Specification (Power supply = ±.5V) Design Simulation Open Loop Gain >5, GB (MHz) 5 MHz 5 MHz Input CMR (Volts) V to V. V to.4 V, Slew Rate (V/μsec) > (V/μsec), 7(V/μsec) Pdiss (mw) < mw.65mw Vout range (V) ±V.V,.V PSRR () (db) 87 PSRR () (db) 6 Phase margin (degrees) 6 65 Output Resistance (k ).5k Lecture 5 Measurement and Simulation of Op amps (/8/) Page 56 Relative Overshoots of Ex. 5 Why is the negativegoing overshoot larger than the positivegoing overshoot on the smallsignal transient response of the last slide? Consider the following circuit and waveform: M6 i Cc V During the rise time, SS =.5V i CL = (dv out /dt )= pf(.v/.μs) = μa and i Cc = pf(v/μs) = 6μA i 6 = 95μA μa 6μA = μa g m6 = 66μS (nominal was 94.5μS) During the fall time, i CL = (dv out /dt) = pf(.v/.μs) = μa and i Cc = pf(v/μs) = 6μA V Bias =.5V C c 95μA 94/ i 6 i CL.V i 6 = 95μA μa 6μA = 69μA g m6 = 85μS The dominant pole is p (R I gm6r II C c ) but the GB is g mi /C c = 94.5μS/pF =.4x6 rads/sec and stays constant. Thus we must look elsewhere for the reason. Recall that p g m6 / which explains the difference. p (95μA) = 94.5x6 rads/sec, p (μa) = 6.6 x6 rads/sec, and p (69μA) = 8.5 x6 rads/sec. Thus, the phase margin is less during the fall time than the rise time. M7 v out.v.μs.μs Fig. 46 t

14 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 57 OP AMP MACROMODELS What is a Macromodel? A macromodel uses resistors, capacitors, inductors, controlled sources, and some active devices (mostly diodes) to capture the essence of the performance of a complex circuit like an op amp without modeling every internal component of the op amp. Small Signal, Frequency Independent Op Amp Macromodel v v v R v o o o A R id A vd (v v ) R id v v 4 v v A vd R o (v v ) (a.) (b.) (c.) Fig. Figure (a.) Op amp symbol. (b.) Thevenin form. (c.) Norton form. R ic R ic R id Avd (v v ) R o A vc v R o A vc v R o Linear Op Amp Macromodel R o Fig. Figure Simple op amp model including differential and common mode behavior. v o R o v o Lecture 5 Measurement and Simulation of Op amps (/8/) Page 58 Small Signal, Frequency Dependent Op Amp Macromodel A vd () A vd (s) = (s/ ) where = R C (dominant pole) Model Using Passive Components: v v R id A vd () R (v v ) R C v o Fig. 4 Figure Macromodel for the op amp including the frequency response of A vd. Model Using Passive Components with Constant Output Resistance: v v R id A vd () R (v v ) v R C R R o o Fig. 5 Figure 4 Frequency dependent model with constant output resistance. 4 v o

15 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 59 Large Signal, Frequency Independent Op Amp Macromodel R ic 6 7 V IH V IL R id IM 5 R ic IM 4 D D V IH D D4 8 V IL 9 A vd R o (v 4 v 5 ) Nonlinear Op Amp Macromodel A vc v 4 A vc v 5 D5 D6 R o R o R o v o V OH V OL Fig. Figure 5 Op amp macromodel that limits the input and output voltages. I o I o v 4 D D I o D D I o R id D5 D6 I Limit D4 D I Limit D D4 I Limit A R 7 o vd I o I v (v R v ) I Limit 6 o V OH V OL o Fig. Fig. Figure 6 Technique for current limiting and a macromodel for output voltage and current limiting. 5 8 v o Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 Large Signal, Frequency Dependent Op Amp Macromodel Slew Rate: dv o dt = ±I SR C = Slew Rate v v R id Avd () R (v v ) R C D D4 6 D D 7 v 4 v 5 R o Fig. 5 Figure 7 Slew rate macromodel for an op amp. Results for a unity gain op amp in slew: V 4 5 I SR R o v o 5V V Output Voltage 5V Input Voltage V μs μs 4μs 6μs 8μs μs Time Fig. 6

16 Lecture 5 Measurement and Simulation of Op amps (/8/) Page 5 SUMMARY Simulation and measurement of op amps has both similarities and differences Measurement of open loop gain is very challenging the key is to keep the quiescent point output of the op amp well defined The method of stimulating the output of the op amp or power supplies and letting the input respond results in a robust method of measuring open loop gain, CMRR, and PSRR Carefully investigate any deviations or aberrations from expected behavior in the simulation and experimental results Macromodels are useful for modeling the op amp without including every individual transistor