EE 110 Practice Problems for Exam 2: Solutions, Fall 2007

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1 EE 110 Practice Problems for Exam 2: Solutions, Fall Circle T (true) or F (false) for each of these Boolean equations. (a). T FO An 8-to-1 multiplexer requires 2 select lines. (An 8-to-1 multiplexer requires 3 select lines). (b). T FO A half adder has a carry input. (A half adder has no carry input). (c). TO F Even parity means the data has an even number of bits that are 1. (d). T FO If a decoder has 16 outputs, it requires 3 inputs to choose all possible outputs. (A 16-output decoder requires 4 inputs to choose all outputs). (e). T FO Latches are edge-triggered memory devices. (Latches are level-triggered memory devices). 2. Signed Arithmetic: 2(a). Find using two s complement format with 8-bit numbers. Then convert your result back to decimal is positive. In 8-bit two s complement format, = is negative. In 8-bit two s complement format, = ; flip the bits and add 1 to get two s complement of a negative number = = Add and together in two s complement format: = Convert to decimal: in two s complement is a negative number, so flip the bits and add 1 to find its magnitude = = = The solution is = = (b). Find using one s complement format with 8-bit numbers. Then convert your result back to decimal is positive, so in one s complement, = is negative; = , so in one s complement format flips the bits of

2 EE 110 Practice Problems for Exam 2: Solutions, Fall = = = carry bit. One s complement uses an end-around carry if the carry bit is 1, which means add 1 to the sum: = = Convert to decimal to check your answer: = = = = = (c). Add 5F 16 + C2 16, assuming you are limited to 8-bit signed numbers, and that these hex numbers are a compact representation of two s complement binary numbers. Convert your answer to decimal. Is your answer correct? Why or why not? Convert the hex numbers to binary and add the two s complement binary numbers together. It is possible to directly add the numbers in hex, but we will perform the addition in binary. Convert 5F 16 to binary: 5F 16 = Convert C2 16 to binary: C2 16 = Add together: = , drop the carry bit. The answer is positive, as the MSB=0, so we can convert directly to decimal = = Is this answer correct? Let s convert the binary equivalents of the hex numbers to decimal: 5F 16 = = = ; C2 16 has MSB=1, so it is a negative two s complement number. Therefore, we must find its magnitude by taking the two s complement again. C2 16 = Flipping all bits, we obtain , and adding 1, we get Converting to decimal, we find that the magnitude of C2 16 = = 62 10, and thus C2 16 = Our answer is 33 10, and = So our answer is correct. The answer is correct because it falls within the range of 8-bit two s complement representation; 8-bit two s complement numbers can accurately represent any number from +127 to Since we are adding a positive number which must be between 0 and 127 to a negative number that must be between -1 and -128, our answer must fall in the range from +126 to This is within the range of 8-bit two s complement accuracy. Note that if we add two negative numbers, or add two positive numbers, the answer could be outside the range of accurate representation; whether it is or not depends on the magnitude of the numbers being added.

3 EE 110 Practice Problems for Exam 2: Solutions, Fall Combinational Logic: Design a circuit that counts the number of 1 s present in 3 inputs A, B and C. Its output is a two-bit number X 1 X 0, representing that count in binary. Assume active-high logic. 3(a). Write the truth table for this circuit. A B C X 1 X (b). Find the minimized logic equations for outputs X 1 and X 0 ; use a K-map if needed. A K-map for X 0 is not very helpful, as it results in 4 isolated minterms, A B C + A B C + A B C + ABC. However, we may recall from the binary adder lab that this equation can be factored further using the XOR operator. Factor out A and A from their respective terms to obtain: X 0 = A(BC + BC) + A(B C + BC) = A(B C) + A(B C) = A (B C). X0 = A B C K-Map for X 1 : BC A SOP expression for X1: blue vertical pair=bc green horizontal pair=ac, red horizontal pair=ab X1 = AB + AC + BC

4 EE 110 Practice Problems for Exam 2: Solutions, Fall (c). Draw the corresponding logic diagram for this circuit. Label all inputs and outputs. A B C AND OR OR X 1 AND AND XOR XOR X 0 4. Combinational Logic: Multiplexers and Encoders 4(a). Draw a block diagram of a 4-to-1 multiplexer. Do not use a gate-level diagram. Label all inputs and outputs. A 0 A 1 A 2 A 3 Y S 1 S 0 4(b). Draw a block diagram of a 4-to-2 encoder. Label all inputs and outputs. How is the 4-to-2 encoder different from a 4-to-1 multiplexer? A 0 A 1 A 2 A 3 Y 1 Y 0

5 EE 110 Practice Problems for Exam 2: Solutions, Fall The 4-to-2 encoder has 4 input lines and 2 output lines. Only one input line should be active at a time. The 2 output lines send the 2-bit binary number corresponding to which input line is active. So if line A 1 is active, the output Y 1 Y 0 will be 01. The 4-to-1 multiplexer has 4 input lines, and 2 select lines. The 2 bits from the select lines choose the input line which will be used as output, so the data sent on that input line will be output. So if the select lines S 1 S 0 = 01, whatever data is on input line A 1 will be output on Y. 4(c). Write the truth table for a 4-to-2 priority encoder. Write a simplified truth table for a 4-to-1 multiplexer (hint: your multiplexer truth table should have 2 inputs). Truth Table for 4-to-2 priority encoder: A 3 A 2 A 1 A 0 Y 1 Y Truth Table for 4-to-1 multiplexer: S 1 S 0 Y 0 0 A A A A 3

6 EE 110 Practice Problems for Exam 2: Solutions, Fall Combinational Logic: Binary Adders You wish to add two 4-bit numbers. You have half adders and full adders available to use as components. 5(a). Draw a block diagram of your 4-bit adder, using half and full adders. Do not draw a gate-level diagram. Show and label all inputs and outputs. X 3 Y 3 C 2 X 2 Y 2 C 1 X 1 Y 1 C 0 X 0 Y 0 Full Adder Full Adder Full Adder Half Adder C 3 C 2 Z 3 C 0 Z 2 C 1 Z 1 Z 0 5(b). Assume that a half adder has a maximum propagation delay of, and a full adder has a maximum propagation delay of 2. What is the maximum propagation delay for your 4-bit adder, from LSB input to MSB output? You have 3 full adders and 1 half adders in your 4-bit adder design, so the maximum propagation delay from the LSB input at the half adder to the MSB output at the last full adder must go through all adder components. The maximum propagation delay is = 7.

7 EE 110 Practice Problems for Exam 2: Solutions, Fall Sequential Logic: Latches and Flip-flops 6(a). Draw a block diagram (not a gate-level diagram) of a D latch and a D flip-flop. Show and label all inputs and outputs. Block Diagram of a D Latch: D Q EN or C Q Block Diagram of a D Flip-Flop: D Q CLK Q 6(b). Write the truth tables for both a D latch and a D flip-flop. Truth Table for a D Latch: (note: Q is the next state of Q) C D Q 0 0 Q (Hold) 0 1 Q (Hold) (Reset) (Set) Truth Table for a D Flip-Flop: CLK D Q 0 0 (Reset) 1 1 (Set) 0 X Q (Hold) 1 X Q (Hold) X Q (Hold)

8 EE 110 Practice Problems for Exam 2: Solutions, Fall (c). On the following graph, inputs CLK and D are shown. They are inputs to both a D latch and a D flip-flop. CLK goes into the EN or C input of the D latch. Write the output of the D latch as Q DL on the graph. Then write the output of the D flip-flop as Q DFF on the graph. Ignore setup and hold time requirements (assume T SU = T H = 0). Both outputs are initially 0 at the start of the graph, as shown. Do the two outputs differ, and if so, why? CLK D Q DL Q DFF The output of the D latch, Q DL, and the output of the D flip-flop, Q DFF, do differ. They are different because the D latch is level-triggered, acting when the clock is high, while the D flip-flop is edge-triggered, and only acts on a rising edge of the clock. Thus the D latch output can change value at any time when CLK = H if the input D changes value. The D flip-flop can only change value on the rising edge of CLK. 7. Sequential Logic: Counters 7(a). Design a 3-bit binary synchronous counter using J-K flip-flops. First, draw the state bubble diagram, showing the 3-bit outputs as the state

9 EE 110 Practice Problems for Exam 2: Solutions, Fall (b). Draw the circuit diagram, using flip-flops as blocks (don t draw the individual gates in each flip-flop). Show and label all inputs and outputs. A 3-bit binary counter requires 3 flip-flops, as each flip-flop provides one bit with its output Q. The counter is synchronous, which means all flip-flops are connected to the same clock. However, before we can draw the counter, we need to determine how to connect the J-K inputs to produce the state bubble diagram of 7.a. Remember that the truth table for a J-K flip-flop is: J K Q 0 0 Q (Hold) (Reset) (Set) 1 1 Q (Toggle) Write a truth table showing the present state Q, next state Q and all required J-K input values to achieve the required transition from present to next state. Present State Next State Inputs Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 J 2 K 2 J 1 K 1 J 0 K X X X X X X 1 X X X X X X 1 X 1 X 1 Note that J 0 and K 0 are either 1 or X (don t care), so they may be set high; J 0 = K 0 = 1. Also note that J 1 and K 1 are 1 or X whenever Q 0 = 1. Thus J 1 = K 1 = Q 0. This could also be determined from a 3-variable K-map of J 1, with variables Q 2, Q 1 and Q 0. Similarly, note that J 2 and K 2 are 1 or X whenever both Q 1 and Q 0 are 1. Their equation is found as J 2 = K 2 = Q 1 Q 0. Again, this could also be found from a 3-variable K-map of J 2, with variables Q 2, Q 1 and Q 0. Now that we have equations for all the J-K inputs, we can draw the circuit diagram for the 3-bit synchronous counter.

10 EE 110 Practice Problems for Exam 2: Solutions, Fall V AND CLK PRE J 2 Q 2 K 2 CLR PRE J 1 Q 1 K 1 CLR PRE J 0 Q 0 K 0 CLR Q 2 Q 1 Q 0 7(c). For an output cycle of 10 clock pulses, draw the 3 outputs X 0, X 1 and X 2 of the synchronous counter on the grid below. State which output is the MSB and which is the LSB. Assume that you start in the all-zeros state (000) as shown below. CLK MSB=X 2 X 1 LSB=X 0 Note that the counter is counting from X 2 X 1 X 0 = 000 to up to 111 and then starts over again at 000, exactly as the state bubble diagram of 7.a. describes.

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