COMPUTER ENGINEERING PROGRAM

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1 Learning Objectives COMPUTER ENGINEERING PROGRAM California Polytechnic State University CPE 169 Experiment 8 Basic Binary Counter Design Using Sequential Logic 1. Digital Systems Design To design and implement several sequential binary arithmetic circuits 2. Xilinx Design Methodology and VHDL To gain more experience with VHDL structural modeling To use VHDL to design basic sequential circuits To use the iterative modular design technique to construct a complex sequential circuit To gain more experience using the Logic Analyzer Introduction and Overview This experiment introduces the most basic element of sequential circuits: the flip-flop. Flip-flops are commonly used in the design of binary counters. In this experiment you will use VHDL behavioral modeling to design a basic flip-flop. This design is then extended using the iterative modular design approach and VHDL structural modeling to generate a 4-bit binary counter. This binary counter is tested using two methods: 1) visual inspection based on the outputs of the 7-segment display and, 2) by directly viewing its outputs on the logic analyzer. Latches and flip-flops are the fundamental building blocks of sequential circuits. The outputs of sequential circuits depend on both the current circuit outputs as well as the circuit s inputs. The current outputs of a sequential circuit are fed back to the input circuitry which uses them in combination with the current inputs to generate a new output. Sequential circuits are often referred to as state machines which allow certain outputs of the circuit to be referred to as the current state of the machine. The state of the machine is stored in the bit-storage elements of the circuit, namely the flip-flops. Examples of other common sequential circuits include registers, counters, finite state machines (FSMs), and semiconductor-based memory. Latches and flip-flops are available as discrete components (e.g., 74xx series parts) or as part of a programmable logic device (e.g., the Xilinx FPGA we use in lab). There are four standard flip-flops: the D data flip-flop, the T toggle flip-flop, the JK (Rowling??) flip-flop, and the SR set-reset flip-flop. Each different flip-flop has its own set of behavioral characteristics. The manner in which a flip-flop behaves, i.e., how the next output is affected by the current state and current inputs, is described by its characteristic equation. The characteristic equations of the four standard flip-flops are shown in Table 1. Flip-flop D T Characteristic Equation + Q = D Q + = Q T JK SR Q Q + + = J Q + K Q = S + R Q Table 1: The characteristic equations for the common types of flip-flops. 3/1/

2 It is worth noting that you can implement any standard flip-flop using any other type of flip-flop with the help of some additional logic gates. Therefore, virtually all PLDs on the market today only provide D flipflops as their on-board storage elements. The other three flip-flops are more typically found in custom chips (ASICs) as they tend to minimize next-state and output logic for sequential logic circuits, due to the fact that different operating characteristics are embedded in the behavior of the flip-flop itself. For example, in today s lab, you ll design a T flip-flop in VHDL and use this building block (iterative modular design again) to design and implement a 4-bit binary counter. The toggling behavior of the T flip-flop makes it particularly well suited for creating binary counters (whose output bits toggle in coordinated ways at different rates). Using VHDL for Sequential Circuits All the circuits we ve implemented up until now have been combinational logic circuits. In other words, none of the circuits we ve examined so far were able to store information. This section describes some of the various methods used to describe simple sequential circuits. You ll later extend this knowledge in the procedural portion of this experiment. This discussion is limited to VHDL behavioral models for several different flavors of D flip-flops. The approaches to designing flip-flops shown in this section cover just about all the possible functionality you could imagine adding to a D flip-flop. Once you understand these basics, you ll be on your way to understanding how to use VHDL to design interesting circuits such as counters and Finite State Machines. Simple Storage Elements Using VHDL The general approach to learning about storage elements is to study the properties of the basic crosscoupled cell. The cross-coupled cell is able to store one bit of data and is often referred to as a latch. Although latches are highly useful, increased functionality from the latch is obtained by adding some type of control signal. This control signal, which is usually some type of clock signal, is further modified by limiting the window of time in which a change in the cell s inputs can cause a change in the cell s output. The addition of pulse narrowing circuitry to the clock, or the arrangement of two latches in a masterslave configuration, has the effect of transmogrifying the lowly latch into the illustrious flip-flop. Flipflops, due to their added control and functionality, are much more common than latches in typical real world digital circuits. The following notes on VHDL for storage elements starts at the simplest form of an edge-triggered D flipflop. The VHDL examples that follow present the basic edge-triggered D flip-flop with an assortment of added functionality. EXAMPLE 1 Write the VHDL code that describes a D flip-flop shown to the right. Use a behavioral model in your description. Solution: The solution to EXAMPLE 1 is shown in Figure 1. Listed below are a few interesting things to note about the solution. The given architecture body describes the my_d_ff version of the d_ff entity. Because the example requested the use of a behavioral model, the architecture body is comprised of a process statement. The statements within the process are executed sequentially. The process is executed each time a change is detected in any of the signals in the process s sensitivity list. In this case, the statements within the process are executed each time there is a change in logic level of the D or CLK signals. 3/1/

3 The rising_edge() is a system-defined function that is used in the if statement to indicate that changes in the circuit output can occur only on the rising edge of the CLK input. The way the if statement is written makes this circuit synchronous since changes are synchronized with the rising edge of the clock signal. In this case, the action is a transfer of the logic level on the D input to the Q output. The D flip-flop is best known and loved for its ability to store (save, remember) a single bit of information. The way that the VHDL code listed in Figure 1 is able to store a bit, however, is not obvious. The bitstorage capability in the VHDL is not explicitly stated; but is implied by both the VHDL code statements and the way the VHDL code is interpreted. The implied storage results from the if statement not providing any indication of what should happen when the listed if condition is not met. In other words, if the if condition is not met (does not evaluate as true ), the device does not change the current value of Q and therefore must remember that current value (so it can be maintained on the output). The remembering of the current value of Q, or the current state, constitutes the advertised bit-storage quality of a flip-flop. Consider reading this again; it s vitally important in all digital circuit design. Providing an action to be performed when the if condition is not met is generally done by using an else clause in the VHDL code. Therefore, if no else clause appears for an if statement, you can count on the VHDL compiler creating some bit-storage circuitry as a result. entity d_ff is port ( end d_ff; D : in std_logic; CLK : in std_logic; Q : out std_logic); architecture my_d_ff of d_ff is dff: process (D, CLK) if (rising_edge(clk)) then Q <= D; end process dff; end my_d_ff; Figure 1: Solution to EXAMPLE 1. EXAMPLE 2 Write the VHDL code that describes the D flip-flop shown. Use a behavioral model in your description. Consider the S input to be an activelow, synchronous input that sets the D flip-flop output to 1 when asserted. Solution: The solution to EXAMPLE 2 is shown in Figure 2. There are a few things of interest regarding this solution. The S input to the flip-flop is made synchronous by only allowing it to affect the operation of the flip-flop on the rising edge of the system clock. On the rising edge of the clock, the S input takes precedence over the D input based upon the appearance of these statements in the source code. In other words, the signal on the D input is transferred to the output only on the rising edge of the clock and only if the S input is not asserted. Since the flip-flop output can only change coincident with an edge of the CLK signal (including any response to the synchronous set input S), the CLK signal is actually the only one that must appear in the process s sensitivity list. The D and S inputs in this list are not essential in this case. 3/1/

4 entity d_ff_ns is port ( end d_ff_ns; D,S,CLK : in std_logic; Q : out std_logic); architecture my_d_ff_ns of d_ff_ns is dff: process (D,S,CLK) if (rising_edge(clk)) then if (S = 0 ) then Q <= 1 ; else Q <= D; end process dff; end my_d_ff_ns; Figure 2: Solution to EXAMPLE 2. EXAMPLE 3 Write the VHDL code that describes the negative edge-triggered D flip-flop shown to the right. Use a behavioral model in your description. Consider the R input to be an active-high, asynchronous input that resets the D flip-flop outputs when asserted. Also consider the R input to have precedence over the CLK and D inputs. Solution: The solution to EXAMPLE 3 is shown in Figure 3. You can probably glean the most information about asynchronous and synchronous inputs by comparing the solutions to EXAMPLE 2 and EXAMPLE 3. The major differences you should observe include: The reset input is independent of the clock and takes priority over the clock. This is done by making the reset condition the first condition in the if statement. Evaluation of the other conditions continues only if the R input does not evaluate to a 1. Since the flip-flop output can now respond directly to the asynchronous reset input, the R input signal must now appear in the process s sensitivity list. The falling_edge( ) function is now used to achieve the desired negative (falling) edgetriggered clocking behavior for the device. entity d_ff_r is port ( end d_ff_r; D,R,CLK : in std_logic; Q : out std_logic); architecture my_d_ff_r of d_ff_r is dff: process (D,R,CLK) if (R = 1 ) then Q <= 0 ; elsif (falling_edge(clk)) then Q <= D; end process dff; end my_d_ff_r; Figure 3: Solution to EXAMPLE 3. The solutions of EXAMPLE 2 and EXAMPLE 3 represent what can be considered the standard VHDL approaches to handling synchronous and asynchronous inputs, respectively. The general forms of these solutions are actually considered templates for synchronous and asynchronous inputs by several VHDL references. As you ll see later, these solutions form the foundation to finite state machine design using VHDL. 3/1/

5 Output Signals Used as Inputs Note in Figure 3 that there is no need to use any of the entity output signals as an input in an equation. (Recall that input signals appear on the right side of the signal assignment operator while output signals appear on the left side). The reason that this worked out so nicely was that in the original excitation equations for the flip-flops given in Table 1, there are no Q s on the right side of the signal assignment operator for the D flip-flop. For this experiment, you ll be building a T flip-flop (which is not so fortunate), so you ll need to take appropriate action. The key to your success on this is to use intermediate signals to temporarily hold the output values when they are assigned inside the process statement, and then to reassign these intermediate signals to the appropriate entity output signals using concurrent signal assignments outside of the process. Since a process statement is also a concurrent signal assignment, you ve not added any new hardware. You ve simply performed a standard work-around of this fairly typical VHDL dilemma. For your pleasure and enjoyment, Figure 4 shows an example of what is being described here with words. The cool thing to note here is that the intermediate signals, unlike the signals appearing in the entity, do not have mode specifiers (such as in or out) associated with them. Keep in mind that entity signals with modes of output can not appear on the right side of the signal assignment operator. (Entity outputs can not be used as inputs to the logic for other signals.) However, intermediate signals can be used on either side of an assignment statement. (Good thing for us!) entity my_thang is port ( CLK : in std_logic; Y1,Y2 : out std_logic); end my_thang; architecture my_thangy of my_thang is signal t_y1,t_y2 : std_logic; -- intermediate signals process (CLK,t_y1,t_y2) if (rising_edge(clk)) then -- assignment to the intermediate signals; note that -- t_y1 & t_y2 appear on right side of <= t_y1 <= t_y1 and (not t_y2); -- f(t_y1,t_y2) t_y2 <= (not t_y2) or t_y1; -- f(t_y1,t_y2) end process; Y1 <= t_y1; -- assignment to external interface variables Y2 <= t_y2; end my_thangy; Figure 4: An example showing clever way to use output as input. Procedure Procedure Overview: In this experiment, you ll design two modules which are later integrated into one circuit. An outline of the procedure is listed below. 1) Design and simulate a T flip-flop. 2) Design, simulate, and test a 4-bit binary counter using four T flip-flops and structural modeling. 3) Visually test the 4-bit counter by using it to drive a BCD to 7-segment decoder (Experiment 6). 4) Verify the outputs of the counter using the Logic Analyzer. 3/1/

6 Procedure 1: Implementation of a T Flip-Flop 1. Design a rising-edge triggered (RET) T flip-flop in VHDL by entering the characteristic equation of the T flip-flop using VHDL syntax. This flip-flop should contain an enable input EN that controls when and if the flip-flop toggles its present state. A description of the T flip-flop is provided in Figure 5. Include a black-box diagram for your flip-flop and include it in your report along with your VHDL code. EN CLK T Q Q 1 0 Q 1 1 Q Figure 5: Black-box diagram and operational characteristics of the T flip-flop. 2. Verify the operation of your flip-flop using ModelSim and include an annotated printout of the simulation with your lab report. Note that since this is a synchronous circuit that uses a clock (CLK), you should set the Clock Information in the Initial Timing and Clock Wizard to Single Clock instead of Combinatorial, when creating the new Testbench Waveform source. Note also that the simulator often generates an unknown output level for sequential circuits such as flip-flops. If this is the case, assign an initial value to your intermediate signal as follows: signal t_q : std_logic := 0 ; -- signal initialization Procedure 2: 4-bit Counter with Enable 1. Using the T flip-flop you designed in Procedure 1, design a 4-bit counter. A black-box diagram of this counter is shown in Figure 6 and should be included in your lab report. a. The output of the counter increments on the rising edge of the clock signal (clk). b. This counter should contain an enable input (en), which when asserted allows the counter to count up in a normal binary sequence. If the enable input is not asserted, the counter does not change state (meaning it does not count). c. Individual T flip-flops provide each of the 4 output count bits. (Each count bit is the output of a different T flip-flop.) NOTE: Implementing this counter requires that additional logic be included in addition to the T flip-flops. In determining the necessary logic, keep in mind that any bit position toggles only when all lower-order bits are 1 and the enable signal is asserted. There are multiple ways to design this counter. Think about the basic characteristics of a T flip-flop and how that would relate to the individual bit values in a binary count sequence. Your lab report should also contain a block diagram showing the underlying logic you used to generate the 4-bit counter. Figure 6: Black-box diagram of the 4-bit counter. 3/1/

7 2. Implement the 4-bit counter using VHDL structural modeling using individual T flip-flops as components that provide each of the 4 output count bits. Include any additional glue logic required to make it count in a normal binary sequence. Create your VHDL source module for the counter in the same Project as the T flip-flop. 3. Test your counter using ModelSim to verify its proper operation. Include an annotated printout of the simulation in your lab report. Procedure 3: Visual Testing of 4-Bit Counter 1. Using VHDL structural modeling, create a new circuit comprised of the 4-bit counter designed in Procedure 2 and the BCD-to-7-segment decoder that you designed in Experiment 6. Connect the output of the counter so that it displays the count value on a 7-segment display. This circuit allows for visual testing of your 4-bit counter. Block diagrams of this circuit and its connection to the 7-segment display are shown in Figure 7. Note that if you re using a Nexys board, you need to include and integrate the CLK_DIV module into your circuit in order to slow down the clock that is incrementing the counter. The VHDL code for the CLK_DIV module is found on the CPE 169 course website. Be sure to include a block diagram of your circuit that matches your VHDL structural design in your lab report. 2. Import your BCD-to-7-Segment Display module source code into the project and connect the output of the counter so that it displays the count value on a 7-segment display. 3. Implement your 4-bit counter with output display on your Development Board and demonstrate it to your instructor. Figure 7: Circuit used for visually testing the 4-bit counter on the Nexys board. Procedure 4: Logic Analyzer Testing of Counter (Optional Check with your lab instructor) 1. Complete an FPGA pin assignment (Assign Package Pins) and create a configuration file for your counter circuit from Procedure 2. Refer to the Reference Manual for your development board to determine FPGA pin assignments needed to connect the counter output bits to signals that are wired to an Expansion connector, to make the signals available to the Logic Analyzer. 2. Following the same procedure as detailed in Experiment 5, connect the 4-bit counter designed in Procedure 2 to the Logic Analyzer POD and view the count output on the screen. 3. Demonstrate to your instructor that the Logic Analyzer is correctly displaying the counter s output. Include a printout of the waveform from the Logic Analyzer (if available) in your report. 3/1/

8 Questions 1. How would you implement a T flip-flop using a D flip-flop and some additional logic gates? Use discrete logic for your solution and draw the circuit in your report. 2. How would you implement a D flip-flop using a T flip-flop and some additional logic gates? Use discrete logic for your solution and draw the circuit in your report. 3. What were the operational characteristics of the circuit used in Procedure 2? In other words, completely describe the operation of the 4-bit counter used in this procedure. What output values were expected? How often would each output change? What controlled whether or not and when the outputs updated? What determined the particular sequence of values seen on the output? 4. The 4-bit counter implemented in this experiment was designed using T flip-flops and structural modeling. There was one major drawback of this design approach. What was that drawback? Is there a better method of designing counters using VHDL? (Hint: Check the VHDL source code for the CLK_DIV module provided.) 5. The BCD to 7-segment decoder used in this experiment was reused from a previous experiment. The original device, however, was not designed to be as generic as it could have been; but was designed specifically to work with the displays on your particular development board. Describe an approach to designing and applying a BCD to 7-segment decoder design that is more generic. 6. In the final test circuit, what was displayed on the output when the count value is greater than nine? Why is this? Is this a problem? 7. Completely describe the operation of the circuit used in Procedure 3. What should be observed if it is functioning correctly? What initiates or stops the behavior observed? What controls the rate of updates in the observed outputs? What is the function of each device used, and how does it contribute to the overall functioning of the system? 8. The Nexys Board includes a Xilinx XCF02S Flash PROM that can more permanently store the FPGA's configuration program so that it does not have to be downloaded every time the board is powered up. This is the other device that keeps showing up in the Scan Chain along with the FPGA whenever you program the Nexys board using the Digilent ExPORT tool. A Flash PROM is a reprogrammable, nonvolatile memory device; which means that it will "remember" its programming even when there is no power supplied to it (nonvolatile); and it can be erased and programmed more than once (reprogrammable). In a typical "real world" design with an FPGA, a nonvolatile memory like a Flash PROM is interconnected with the FPGA so that the FPGA program will be loaded from the PROM automatically when the system is powered up or reset; thus making it appear that the FPGA is nonvolatile. For the specific Flash PROM used on the Nexys board, how long can a particular FPGA configuration be reliably stored (retained) in the Flash PROM once it has been programmed? How many times can the configuration information be reprogrammed in the Flash PROM? (Check out the data sheets for this device.) 3/1/