Lecture 1: Circuits & Layout

Transcription

1 Introduction to CMOS VLSI Design Lecture : Circuits & Layout David Harris Harvey Mudd College Spring 24

2 Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams Slide 2

3 A Brief History 958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments 23 Intel Pentium 4 µprocessor (55 million transistors) 52 Mbit DRAM (>.5 billion transistors) 53% compound annual growth rate over 45 years No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society Slide 3

4 Annual Sales 8 transistors manufactured in 23 million for every human on the planet Global Semiconductor Billings (Billions of US$) Year Slide 4

5 Invention of the Transistor Vacuum tubes ruled in first half of 2 th century Large, expensive, power-hungry, unreliable 947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs Read Crystal Fire By Riordan, Hoddeson Slide 5

6 Transistor Types Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nmos and pmos MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration Slide 6

7 MOS Integrated Circuits 97 s processes usually had only nmos transistors Inexpensive, but consume power while idle Intel 256-bit SRAM Intel 44 4-bit µproc 98s-present: CMOS processes for low idle power Slide 7

8 Moore s Law 965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months Transistors,,,,,,,,,, 8286 Intel386 Intel486 Pentium 4 Pentium III Pentium II Pentium Pro Pentium Integration Levels SSI: gates MSI: gates 886,, LSI:, gates Year VLSI: > k gates Slide 8

9 Corollaries Many other factors grow exponentially Ex: clock frequency, processor performance,, 44 Clock Speed (MHz) Intel386 Intel486 Pentium Pentium Pro/II/III Pentium Year Slide 9

10 CMOS Gate Design Activity: Sketch a 4-input CMOS NAND gate Slide

11 CMOS Gate Design Activity: Sketch a 4-input CMOS NOR gate A B C D Y Slide

12 Complementary CMOS Complementary CMOS logic gates nmos pull-down network pmos pull-up network a.k.a. static CMOS inputs pmos pull-up network output Pull-down OFF Pull-up OFF Z (float) Pull-up ON nmos pull-down network Pull-down ON X (crowbar) Slide 2

13 Series and Parallel nmos: = ON pmos: = ON g g2 a b a b a b a b a b Series: both must be ON Parallel: either can be ON (a) g g2 a b OFF OFF OFF ON a a a a b b b b (b) ON OFF OFF OFF a a a a a g g2 b b b b b (c) OFF ON ON ON a a a a a g g2 b b b b b (d) ON ON ON OFF Slide 3

14 Conduction Complement Complementary CMOS gates always produce or Ex: NAND gate Series nmos: Y= when both inputs are Thus Y= when either input is Requires parallel pmos Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel A B Y Slide 4

15 Compound Gates Compound gates can do any inverting function Ex: Y = AB i + CD i (AND-AND-OR-INVERT, AOI22) A C A C B D B D (a) (b) (c) A B C D (d) C A D B C A A B D B C D Y A B C D (f) Y (e) Slide 5

16 Y = ( A+ B+ C) id Example: O3AI Slide 6

17 Y = ( A+ B+ C) id Example: O3AI A A B C B D D C Y Slide 7

18 Signal Strength Strength of signal How close it approximates ideal voltage source V DD and GND rails are strongest and nmos pass strong But degraded or weak pmos pass strong But degraded or weak Thus nmos are best for pull-down network Slide 8

19 Pass Transistors Transistors can be used as switches g s d g s d Slide 9

20 Pass Transistors Transistors can be used as switches s g d s s g = g = d d Input g = Output strong g = degraded s g d s s g = g = d d Input g = Output degraded g = strong Slide 2

21 Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both and well Slide 2

22 Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both and well a g gb b g =, gb = a b g =, gb = a b Input Output g =, gb = strong g =, gb = strong a g b a g b a g b gb gb gb Slide 22

23 Tristates Tristate buffer produces Z when not enabled EN A Y A EN Y A EN Y EN Slide 23

24 Tristates Tristate buffer produces Z when not enabled EN A Y Z Z A EN Y A EN Y EN Slide 24

25 Nonrestoring Tristate Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y EN A Y EN Slide 25

26 Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output A EN EN Y Slide 26

27 Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output A A A EN EN Y Y Y EN = Y = 'Z' EN = Y = A Slide 27

28 Multiplexers 2: multiplexer chooses between two inputs S D D Y S X X X D D Y X Slide 28

29 Multiplexers 2: multiplexer chooses between two inputs S D D Y S X X X D D Y X Slide 29

30 Gate-Level Mux Design Y = SD + SD (too many transistors) How many transistors are needed? Slide 3

31 Gate-Level Mux Design Y = SD + SD (too many transistors) How many transistors are needed? 2 D S D Y D S D Y Slide 3

32 Transmission Gate Mux Nonrestoring mux uses two transmission gates Slide 32

33 Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors D S S Y D S Slide 33

34 Inverting Mux Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter D S S S D S Y D S S D S S Y D D S Y Slide 34

35 4: Multiplexer 4: mux chooses one of 4 inputs using two selects Slide 35

36 4: Multiplexer 4: mux chooses one of 4 inputs using two selects Two levels of 2: muxes Or four tristates SS SS SS SS D S S D D D2 Y D D2 Y D3 D3 Slide 36

37 D Latch When CLK =, latch is transparent D flows through to Q like a buffer When CLK =, the latch is opaque Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch CLK CLK D Latch Q D Q Slide 37

38 D Latch Design Multiplexer chooses D or old Q D CLK Q Q D CLK CLK CLK Q Q CLK Slide 38

39 D Latch Operation Q Q D Q D Q CLK = CLK = CLK D Q Slide 39

40 D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop CLK CLK D D Flop Q Q Slide 4

41 D Flip-flop Design Built from master and slave D latches CLK D CLK QM CLK Q CLK CLK CLK CLK CLK D Latch QM Latch Q CLK CLK Slide 4

42 D Flip-flop Operation D QM Q CLK = D QM Q CLK = CLK D Q Slide 42

43 Race Condition Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition CLK CLK CLK2 CLK2 D Flop Q Flop Q2 Q Q2 Slide 43

44 Nonoverlapping Clocks Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead φ 2 φ D QM Q φ 2 φ 2 φ φ φ 2 φ φ φ 2 Slide 44

45 Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology V DD and GND should abut (standard height) Adjacent gates should satisfy design rules nmos at bottom and pmos at top All gates include well and substrate contacts Slide 45

46 Example: Inverter Slide 46

47 Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal V DD rail at top Metal GND rail at bottom 32 λ by 4 λ Slide 47

48 Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers Slide 48

49 Wiring Tracks A wiring track is the space required for a wire 4 λ width, 4 λ spacing from neighbor = 8 λ pitch Transistors also consume one wiring track Slide 49

50 Well spacing Wells must surround transistors by 6 λ Implies 2 λ between opposite transistor flavors Leaves room for one wire track Slide 5

51 Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in λ Slide 5

52 Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ( A+ B+ C) id Slide 52

53 Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ( A+ B+ C) id Slide 53

54 Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ( A+ B+ C) id Slide 54