System on Chip Design. Michael Nydegger

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1 Short Questions, 26. February 2015 What is meant by the term n-well process? What does this mean for the n-type MOSFETs in your design? What is the meaning of the threshold voltage (practically)? What are the three operating regions of a MOSFET? How does the MOSFET behave in each region? Why do we use a p-type MOSFET instead of a resistive load device in static CMOS gates? Rev..1

2 Short Questions, 5. March 2015 What is the purpose of the Y-chart (figure below)? What are the three design views? What is meant by the term "system gap"? What is it s historical cause? System-on-Chip -Chart o 5 component What libraries is a Transaction-Level Model (TLM) used for? On M. Jacomet ystem (MoC, which NoC) abstraction Behavioral level in the Structural Y-chart is it located? rocessor (std, custom) LU s logic (RFs, (standard, mem) cells) SoC Introduction Gap What kind of tools drastically changed the design Y-Chart flow of Processor Level embedded systems in the early 1980 s? System Level 3 design views behavioral (functionality) structural (netlist) physical (layout) 4 abstraction layers system processor logic circuit system processor logic circuit Flow System Models System Platform Tools Conclusion System on Chip transistor Rev..2

3 Short Questions, 5. March 2015 What is the purpose of the Y-chart (figure below)? What are the three design views? What is meant by the term "system gap"? What is it s historical cause? System-on-Chip -Chart o 5 component What libraries is a Transaction-Level Model (TLM) used for? On M. Jacomet ystem (MoC, which NoC) abstraction level in the Y-chart is it located? rocessor (std, custom) LU s logic (RFs, (standard, mem) cells) SoC Introduction Gap What kind of tools drastically changed the design Y-Chart flow of Processor Level embedded systems in the early 1980 s? System Level 3 design views behavioral (functionality) structural (netlist) physical (layout) Behavioral 4 abstraction layers system processor logic circuit system processor logic circuit Structural Flow System Models System Platform Tools Conclusion System on Chip transistor Physical Rev..2

4 Short Questions, 12. March 2015 How do we measure propagation delays of symmetric CMOS gates? What are the problems in measuring delays of skewed gates? Which input of a multi-input gate is typically the fastest (location of the input transistor relative to output) and why? What is the relation between the dynamic power consumption and the frequency? How about the supply voltage? What happens to an ideal step at the end of a long wire? Rev..3

5 Short Questions, 26. March 2015 What is the motivation for operator merging in hardware synthesis? What are the similarities of variables you would preferably merge? How many transistors are required to build a 2-input AND gate? Which Euler path(s) are common for the drawn p- and n-mos networks? pmos nmos 1. A D E C B 2. C B A D E 3. E C B A D 4. A C E B D A B D E C D A B E C Rev..4

6 Short Questions, 9. April 2015 What is meant by the term "multicycling" and how does it affect the maximum clock speed of your datapath? What is the disadvantage of control pipelining? Explain the difference between ASAP/ALAP scheduling and RC scheduling? Why do we use both n- and p-type MOSFETs in transmission gates (TGs)? What happens to a logic high at the input of a TG which only consists of an n-type MOSFET? Why are large chains of TGs often avoided? Rev..5

7 Short Questions, 16. April 2015 How can we detect an overflow in a 2 s complement addition? What is the idea behind the introduction of a carry propagate and generate signal? How does a carry-select adder work? A carry save adder (CSA) must be complemented by a carry propagate adder (CPA) because of? Rev..6

8 Short Questions, 23. April 2015 How is the delay of a Wallace tree adder related to the number of summands? When would you use bit-serial adders? How do you build the partial products in a simple hardware multiplier? What s the idea behind higher radix multiplications? A barrel shifter can do...? Rev..7

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