Chapter 8 Differential and Multistage Amplifiers. EE 3120 Microelectronics II

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1 1 Chapter 8 Differential and Multistage Amplifiers

2 Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4. Ch 10: Feedback 5. Ch 11: Output Stages

3 Active-Loaded Differential Pair 3 Two Stage Op Amp (MOSFET)

4 Learning Objectives 4 1) MOS and the bipolar differential amplifiers: how they reject common-mode noise or interference and amplify differential signals 2) The analysis and design of MOS and BJT differential amplifiers: utilizing passive resistive loads, currentsource loads, and cascodes 3) The structure, analysis, and design of amplifiers composed of two or more stages in cascade

5 5 Differential Amplifier with Active Load

6 Differential Amplifier 6 Differential Input and Differential Output Decreases noise Decreases common-mode gain Increases CMRR Increases differential gain by a factor of 2 (6 db)

7 Frequency Response of Differential Amplifier (9.8) Higher Cut-off Frequency affected by C gd of Q S (part of C ss ) 7 Can be part of the current mirror

8 Frequency Response of Differential Amplifier (9.8) 8 CMRR reduces due to C ss Current mirror introduces an additional zero at f z Tradeoff between the need to reduce the dc voltage (to save power), Vov across Q S (low Vov requires large W/L to maintain bias current I which increases C ss ) and the need to keep the CMRR reasonably high at higher frequencies

9 8.5.1 Differential to Single-ended Conversion Differential Input and Single-ended Output To connect to off-chip load 9

10 A A A d cm cm 2g Active-Loaded MOS Differential Pair 1 gm( ro 2 ro 4) gmro 2 CMRR gmro 2 ro 4 2 gm3rss...(8.147) ro (8.146) 2R 1 g r CMRR g r g R...( R m3 SS SS m3 o3...(8.146') ) Ideal case: no DC output current Small signal current 2i at the output m o m SS 10

11 8.5.2 Active-Loaded MOS Differential Pair Higher the output resistance of the current mirror, higher the CMRR CMRR 11 g r r 2g R...(8.147) m o4 m3 o2 SS Output resistance of active-loaded MOS diff pair R O r r...(8.138) 4 o2 o Low gain, high input resistance compared to BJT diff pair with active load

12 A A d cm g CMRR m Bipolar Differential Pair with Active Load ( r o2 ro 4 R 3 EE r o4 1 3g 2 ) (8.165) m R EE g m r o..(8.167)...(8.158) 12

13 8.5.5 Bipolar Differential Pair with Active Load Higher the output resistance of the current mirror, higher the CMRR CMRR 1 3 EE..(8.167) 2 g R m 13 Output resistance of active-loaded BJT diff pair R O r r...(8.157) 4 o2 o High gain (large g m ), low input resistance (=2r π ) compared to MOS diff pair with active load

14 14 Multistage Amplifiers

15 8.6.1 A Two-Stage CMOS Op Amp PMOS Input Stage 15 A A A 1 2 o g g 1 m1 A A m6 2 ( r o2 ( r o6 r o4 r o7 )...(8.174) )...(8.175)

16 8.6.1 A Two-Stage CMOS Op Amp NMOS Input Stage 16

17 PNP Input Stage A Biploar Op Amp (p12.63) 17

18 List of Problems Diff Pair with Active Load p8.86: MOS diff pair with active load p8.87 (simulation only): MOS diff pair with active load p8.97: BJT diff pair with active load 18 Multistage Amplifiers: p8.112 (simulation only): Bipolar op-amp expl8.5(simulation only): CMOS op-amp Frequency Response of Diff Pair expl 9.14 (read only) and ex 9.29 (read only)

19 Summary 19 The differential-pair (diff pair) or differential-amplifier configuration is most widely used building block in analog IC designs. The input stage of every op-amp is a differential amplifier. There are two reasons for preferring differential to single-ended amplifiers: 1) differential amplifiers are insensitive to interference and 2) they do not need bypass and coupling capacitors For a MOS (or Bipolar) pair biased by a current source I, each device operates at a drain (collector, assuming a = 1) current of I/2 and a corresponding overdrive voltage V OV (no equivalent in bipolar). Each device has g m =1/V OV (ai/2v T for bipolar).

20 Summary With the two input terminals connected to a suitable dc voltage V CM, the bias current I of a perfectly symmetrical differential pair divides equally between the two transistors of the pair, resulting in zero voltage difference between the two drains (collectors). To steer the current completely to one side of the pair, a difference input voltage v id of at least 2 1/2 V OV is needed. 20 Superimposing a differential input signal v id on the dc commonmode input voltage V CM such that v I1 = V CM + v id /2 and v I2 = V CM v id /2 causes a virtual signal ground to appear on the common-source (common-emitter) connection.

21 Summary The analysis of a differential amplifier to determine differential gain, differential input resistance, frequency response of differential gain, and so on is facilitated by employing the differential half-circuit which is a common-source (commonemitter) transistor biased at I/2. 21 An input common-mode signal v icm gives rise to drain (collector) voltage signals that are ideally equal and given by v icm (R D /2R SS )[- v icm (R C /2R EE ) for the bipolar pair], where R SS (R EE ) is the output resistance of the current source that supplies the bias current I.

22 Summary 22 While the input differential resistance R id of the MOS pair is infinite, that for the bipolar pair is only 2r p but can be increased to 2( +1)(r e +R e ) by including resistances R e in the two emitters. The latter action, however, lowers A d. Mismatches between the two sides of a differential pair result in a differential dc output voltage (V o ) even when the two input terminals are tied together and connected to a dc voltage V CM. This signifies the presence of an input offset voltage V OS = V O /A d. In a MOS pair, there are three main sources for V OS. Two exist for the bipolar pair.

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