# DESIGN CHALLENGES OF TECHNOLOGY SCALING

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 DESIGN CHALLENGES OF TECHNOLOGY SCALING IS PROCESS TECHNOLOGY MEETING THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SUCCESSIVE TECHNOLOGY GENERATIONS HELPS IDENTIFY POTENTIAL LIMITERS OF SCALING, PERFORMANCE, AND INTEGRATION. Shekhar Borkar Intel Corporation /99/\$ IEEE Scaling advanced CMOS technology to the next generation improves performance, increases transistor density, and reduces power consumption. Technology scaling typically has three main goals: ) reduce gate delay by 30%, resulting in an increase in operating frequency of about 43%; 2) double transistor density; and 3) reduce energy per transition by about 65%, saving 50% of power (at a 43% increase in frequency). These are not ad hoc goals; rather, they follow scaling theory. This article looks closely at past trends in technology scaling and how well microprocessor technology and products have met these goals. It also projects the challenges that lie ahead if these trends continue. This analysis uses data from various Intel microprocessors; however, this study is equally applicable to other types of logic designs. Scaling theory Scaling a technology reduces gate delay by 30% and the lateral and vertical dimensions by 30%. Therefore, the area and fringing capacitance, and consequently the total capacitance, decrease by 30% to 0.7: Delay = 0.7, frequency.43 Width = W = 0.7, length = L = 0.7, t ox = 0.7 (t ox : oxide thickness) Area capacitance = C A = ( )/0.7= 0.7 Fringing capacitance = C F L C F = 0.7 Total capacitance C = 0.7 Since the dimensions decrease by 30%, the die area decreases by 50%, and capacitance per unit of area increases by 43%: Die area = X Y = = C Area 07. = = Frequency-scaling trends (performance) To evaluate how well past technologies have met the performance goal, we plot product (introduction) frequencies over time, as shown in Figure. Assuming that a technology generation spans two to three years, the data show that microprocessor frequency has doubled every generation not just increased by 43%. Several factors may account for this. Consider the data plotted on the right-hand y-axis in Figure. The average number of gate delays in a clock period is decreasing because the new microarchitectures use shorter 23

2 TECHNOLOGY SCALING 24 MHz,000, IEEE MICRO 993 II 995 Year Figure. Processor frequency doubles each generation. Transistor size (m) 0 Total transistor Average transistor Figure 2. Scaling of transistor size. Logic transistors/mm 2 (logarithmic scale) II II Process technology (microns) i860 II Process technology (microns) Figure 3. Effect of scaling on logic transistor density. Doubling trend Avg. no. of gate delays per clock period pipelines for static gates, and advanced circuit techniques reduce critical path delays even further. This could be one reason that frequency is doubling every technology generation. One might suspect that this frequency increase comes at the expense of overdesign or oversizing of transistors. Figure 2 shows how transistor size scales across technologies in different Intel microprocessors. The dotted lines show transistor size scaling down 30% per generation according to scaling theory. Notice that the total transistor size, which is the sum of all transistor widths, decreases by about 30%. The lower graph shows average transistor sizes (in arbitrary units), which also decrease by about 30%, ruling out any suspicion about oversizing and overdesign. We can conclude that the twofold frequency improvement each technology generation is primarily due to two factors: The reduced number of gates employed in a clock period makes the design more pipelined. Advanced circuit techniques reduce the average gate delay beyond 30% per generation. Transistor density Transistor density is the number of logic transistors in a unit of area. Transistor density should double every technology generation, since according to scaling theory, area decreases by 50%. Memory density has been scaling as expected, and therefore this study focuses on logic transistor density. Figure 3 plots the logic transistor density of several microprocessors, showing their compaction across different technologies. The dotted line shows the expected density-doubling trend. Notice that when a processor design is ported to the next process technology, it meets the density goal; however, a new processor microarchitecture implemented in the same technology shows a drop in density. This may be due to the complexity of the new microarchitectures, as well as to the limited resources available to accomplish a more complex design. Interconnection-scaling trends To meet technology goals, the interconnection system must scale accordingly. In general, as interconnection width and thickness

3 (a) ILD4 ILD3 ILD2 ILD M ILD0 Field oxide Gate oxide (b) M M M 0.0 (c) (d) Figure 4. Interconnection scaling: interconnection stacking (a); relative minimum width (b); relative minimum spacing (c); relative minimum pitch (d). No. of nets (logarithmic scale) 0,000,000 0,000 Length (microns) Figure 5. Interconnection distribution. decrease, resistance increases, and as interconnections become denser, capacitance increases. Although chip size should decrease by 30% in each successive technology, new designs add more transistors to further exploit integration. As a result, the average die size of a chip tends to increase over time. To account for increased parasitics (resistance and capacitance), integration, and complexity, manufacturers add more interconnection layers. The thinner, tighter layers are used for local interconnections, and the new thicker and sparser layers are used for global interconnections and power distribution. Figure 4 shows interconnectionscaling trends on a relative scale. Notice that interconnections seem to be scaling normally. Does advancement in a microarchitecture make the interconnection system more complex? If so, this could explain why new microarchitectures decrease in density. Figure 5 shows interconnection distribution extracted from II (MMX) II JULY AUGUST

4 TECHNOLOGY SCALING 26 Maximum power (W) 0 IEEE MICRO II Figure 6. Maximum thermal power dissipation. Active capacitance density (nf/mm 2 ) MMX Figure 7. Active capacitance density. (MMX) several microprocessor chips employing different microarchitectures. On the y-axis (log scale), the number of interconnections is plotted against the length of the interconnections on the x-axis. The graph shows that interconnection distribution does not change significantly with advances in microarchitecture. Hence, complexity can be ruled out as the reason for the drop in density, and interconnection distribution seems to follow the trend.? 43% trend Power A chip s maximum power consumption depends on its technology as well as its implementation. According to scaling theory, a design ported to the next-generation technology should operate at 43% higher frequency. If the supply voltage remains constant (constant voltage scaling), the power should remain the same. On the other hand, if the supply voltage scales down by 30% (constant electric field scaling), the power should decrease by 50%: V DD = (constant voltage scaling) Power = C V 2 f = 0.7 (/0.7) = V DD = 0.7 (constant electric field scaling) Power = C V 2 f = (/0.7) = 0.5 Figure 6 plots the maximum thermal power dissipation of several microprocessors in successive technologies. The technologies used constant voltage scaling until reaching 0.8 microns and used constant electric field scaling thereafter. Therefore, power increased dramatically up to 0.8 microns, when the increase slowed. Notice that microprocessors ported to next-generation technologies with constant voltage scaling do not show a decrease in power; the power remains constant. On the other hand, microprocessors ported to technologies using constant electric field scaling decrease in power. This is consistent with scaling theory. The power dissipation of a chip depends not only on its technology, but also on its implementation that is, on size, circuit style, microarchitecture, operation frequency, and so on. Hence, to better understand power trends, it is necessary to normalize by introducing the notion of active capacitance, a fictitious equivalent capacitance responsible for power dissipation. We can further normalize the active capacitance to the chip area, in a metric called the active capacitance density capacitance per unit of area responsible for power dissipation. Active = capacitance V Active capacitance = density 2 DD Power frequency Active capacitance Area Figure 7 plots the active capacitance density of several microprocessors in different technologies. From scaling theory, we expect active capacitance density to increase by 43% per

5 technology generation. The figure shows that the increase is on the order of 30% to 35%, not 43%, due to lower density. That is, in practice the microprocessors do not achieve a twofold improvement of logic transistor density between technologies, resulting in a lower active capacitance density. Die size trends Manufacturers have not only taken advantage of increased transistor density, but have also increased chip (die) size to further the level of integration. Microprocessor die size tends to grow about 25% per technology generation. Loosely speaking, this satisfies Moore s law. Projections So far, we have seen trends in several aspects of microprocessor technologies and characteristics. Let s assume that these trends continue that is, frequency doubles, supply voltage scales down 30%, active capacitance grows 30% to 35%, and die size grows 25%. Now we can speculate on power dissipation and supply currents. Figure 8 plots the computed power dissipation of future microprocessor chips if the trends continue. If supply voltage scales down, power dissipation will increase from 0 W in 999 to about 2,000 W in 20; otherwise, it could reach approximately,000 W! So far, this analysis considers only active power and neglects leakage power. Leakage has not been highly significant in the past, but it will be significant in the future. Figure 9 shows supply current projections. Supply current will grow from 0 A to about 3,000 A if supply voltage scales down; otherwise, it will become even higher. To bring power dissipation within reasonable range, we will have to restrict die size. With die size restricted to about 5 mm (a small die), power will stay around 0 W, and supply current will grow to about 300 A. A larger die, about 22 mm, will consume about 200 W of power with a supply current of about 500 A. These are reasonable targets that we can realize in practice. Energy-delay trade-offs Reducing supply voltage, frequency, and/or die size will reduce power. All of these reductions reduce chip performance. That is, one Power (W),000, Figure 8. Power dissipation projections. I cc (A),000,000 0 Year Figure 9. Supply current projections. has to trade off performance to reduce power. Therefore, we must ask whether the primary technology goal (30% delay reduction) makes sense. Why not set a goal that includes delay as well as power? A good metric for this purpose would be the energy-delay product. We can set goals to achieve a lower energy-delay product and make technology decisions as discussed in Gonzalez et al. 2 The choices are as follows: V DD = (constant voltage scaling) Energy = C V 2 = 0.7 = 0.7, delay = 0.7 Energy delay = = 0.5 V DD = 0.7 (constant electric field scaling) Energy = C V 2 = = 0.7 3, delay = 0.7 Energy delay = = 0.25 Year JULY AUGUST

6 TECHNOLOGY SCALING 28 l off (na/micron),000,000 0 Figure. Projected I off. Clock IEEE MICRO Temperature ( C) Clock A B C B C Clock D domino gate Figure. Domino circuit. Q Static gate D2 domino gate 0.-micron 0.3-micron 0.8-micron micron Q2 Clearly, constant electric field scaling (supply voltage scaling) gives the lower energydelay product (ignoring leakage energy) and hence is preferable. However, it requires scaling threshold voltage (V T ) as well, which increases the subthreshold leakage current, thus increasing the chip s leakage power. Subthreshold leakage Now we attempt to estimate the subthreshold leakage power of future chips, starting with the 0.25-micron technology described in Bohr et al., 3 and projecting subthreshold leakage currents for 0.8-, 0.3-, and 0.-micron technologies. Assume that 0.25-micron technology has a V T of 450 mv, and I off is around na per micron at 30 C. Also assume that subthreshold slopes are 80 and 0 mv per decade at 30 C and 0 C respectively. Assume that V T decreases by 5% per generation, and I off increases by 5 times each generation. Since I off increases exponentially with temperature, it is important to consider leakage currents and leakage power as a function of temperature. Figure shows projected I off (as a function of temperature) for the four different technologies. Next we use these projected I off values to estimate the active leakage power of a 5-mm die and compare the active leakage power with the active power. The total transistor width on the die increases around 50% each technology generation; hence, the total leakage current increases about 7.5 times. This results in the chip s leakage power increasing about 5 times each generation. Since active power remains constant (according to scaling theory), leakage power will become a significant portion of total power. Notice that it is possible to substantially reduce leakage power, and hence overall power, by reducing the die temperature. Therefore, better cooling techniques will be more critical in advanced deep-submicron technologies to control both active leakage power and total power. Impact of scaling on circuits Supply voltage scaling increases subthreshold leakage currents, increases leakage power, and poses numerous challenges in the design of special circuits. Domino circuits (Figure ), for example, are widely used to achieve high performance. A domino gate typically reduces delay 30% compared with a static gate, but it consumes 50% more power. A domino circuit also takes less space because the logic is implemented with N transistors, and most of the complementary P stack is absent. As the threshold voltage decreases, the noise margin decreases. To compensate, the size of the keeper P transistor must increase, in turn increasing the contention current and consequently reducing the gate s performance. Overall, the domino s advantage over static logic will continue to decrease. This effect is not restricted to domino logic alone; supply voltage scaling will affect most special circuits, such as sense amplifiers and programmable logic arrays. Soft errors Soft errors (single-event upsets) are caused by alpha particles in the chip material and by cosmic rays from space. Since capacitance and

7 voltages will decrease in future technologies, a smaller charge (Q = C V) will be needed to flip a bit in memory. Therefore, the soft error rate will increase. Attempting to reduce the soft error rate by increasing capacitance on the node will result in reduced performance. Typically, we protect data in memory with parity or error-correcting codes, but there is no mechanism to protect latches and flip-flops that store state in random logic. The increased soft error rate will have a detrimental effect on logic latches, a problem that needs more investigation. Power density Power density is the power dissipated by the chip per unit of area, in W/cm 2. Figure 2 plots the power density of microprocessor chips in different technology generations. Chips in 0.6-micron technology have surpassed the power density of a kitchen hot plate s heating coil, and clearly the trend is increasing. Controlling die temperature and keeping it low are essential for better performance and lower leakage. Controlling power density will be even more crucial for leakage control in deep-submicron technologies. Trends in performance, density, and power follow scaling theory. If these trends continue, power delivery and dissipation will be the primary limiters of performance and integration. To overcome these limiters, we must constrain die size growth and continue to scale supply voltage. We will have to scale threshold voltage to meet performance demands, thus increasing subthreshold leakage current, limiting functionality of special circuits, increasing leakage power, and increasing soft error susceptibility. These are among the major challenges that circuit designers will face in future technologies. MICRO Acknowledgments I thank my colleagues Vivek De, K. Soumyanath, Ali Keshavarzi, Ian Young, and several others for providing insight into topics discussed in this article. I also thank Bill Holt, Ricardo Suarez, Fred Pollack, and Richard Wirt for their continued support and encouragement. W/cm Hot plate Figure 2. Chip power density References. Intel Corp., 2. R. Gonzalez, B. Gordon, and M. Horowitz, Supply and Threshold Voltage Scaling for Low-Power CMOS, IEEE J. Solid-State Circuits, Vol. 32, No. 8, Aug. 997, pp M. Bohr et al., Proc. Int l Electron Devices Meeting, IEEE Electron Device Society, 996, pp Shekhar Borkar is the director of Intel s Circuit Research Laboratory, where he leads research on low-power circuits and high-speed signaling. He is also an adjunct faculty member at the Oregon Graduate Institute, teaching digital CMOS VLSI design. Borkar received a master s degree in physics from the University of Bombay and an MSEE from the University of Notre Dame. Send questions and comments to Shekhar Borkar, 5200 NE Elam Young Parkway, EY2-07, Hillsboro, OR, 9724; intel.com. JULY AUGUST

### Low Power AMD Athlon 64 and AMD Opteron Processors

Low Power AMD Athlon 64 and AMD Opteron Processors Hot Chips 2004 Presenter: Marius Evers Block Diagram of AMD Athlon 64 and AMD Opteron Based on AMD s 8 th generation architecture AMD Athlon 64 and AMD

### Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department

### INTERNATIONAL JOURNAL OF COMPUTER ENGINEERING & TECHNOLOGY (IJCET)

INTERNATIONAL JOURNAL OF COMPUTER ENGINEERING & TECHNOLOGY (IJCET) International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 6367(Print), ISSN 0976 6367(Print) ISSN 0976 6375(Online)

### Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,

### Digital Design for Low Power Systems

Digital Design for Low Power Systems Shekhar Borkar Intel Corp. Outline Low Power Outlook & Challenges Circuit solutions for leakage avoidance, control, & tolerance Microarchitecture for Low Power System

### A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology

International Journal of Computer Sciences and Engineering Open Access Research Paper Volume-4, Issue-1 E-ISSN: 2347-2693 A Novel Low Power Fault Tolerant Full Adder for Deep Submicron Technology Zahra

### International Conference on Science, Technology, Engineering & Management [ICON-STEM 15]

An Enhanced Technique for Leakage Reduction in 8:1 Domino Multiplexer S. Lakshmi Narayanan*, R. Jaya Nandhini, Dr. ReebaKorah Department of ECE, Anna University, Chennai,Tamil Nadu, India. *Corresponding

### Alpha CPU and Clock Design Evolution

Alpha CPU and Clock Design Evolution This lecture uses two papers that discuss the evolution of the Alpha CPU and clocking strategy over three CPU generations Gronowski, Paul E., et.al., High Performance

### NAME AND SURNAME. TIME: 1 hour 30 minutes 1/6

E.T.S.E.T.B. MSc in ICT FINAL EXAM VLSI Digital Design Spring Course 2005-2006 June 6, 2006 Score publication date: June 19, 2006 Exam review request deadline: June 22, 2006 Academic consultancy: June

### Intel s Revolutionary 22 nm Transistor Technology

Intel s Revolutionary 22 nm Transistor Technology Mark Bohr Intel Senior Fellow Kaizad Mistry 22 nm Program Manager May, 2011 1 Key Messages Intel is introducing revolutionary Tri-Gate transistors on its

### International Journal of Electronics and Computer Science Engineering 1482

International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant

### Design and analysis of flip flops for low power clocking system

Design and analysis of flip flops for low power clocking system Gabariyala sabadini.c PG Scholar, VLSI design, Department of ECE,PSNA college of Engg and Tech, Dindigul,India. Jeya priyanka.p PG Scholar,

### TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN

TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN USING DIFFERENT FOUNDRIES Priyanka Sharma 1 and Rajesh Mehra 2 1 ME student, Department of E.C.E, NITTTR, Chandigarh, India 2 Associate Professor, Department

### ISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7

ISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7 13.7 A 40Gb/s Clock and Data Recovery Circuit in 0.18µm CMOS Technology Jri Lee, Behzad Razavi University of California, Los Angeles, CA

### Digital Integrated Circuit (IC) Layout and Design

Digital Integrated Circuit (IC) Layout and Design! EE 134 Winter 05 " Lecture Tu & Thurs. 9:40 11am ENGR2 142 " 2 Lab sections M 2:10pm 5pm ENGR2 128 F 11:10am 2pm ENGR2 128 " NO LAB THIS WEEK " FIRST

### Keywords: SAEN (sense enable signal), BB (bit- bar), BL (bit- line), SOC (system on chip)

Volume 4, Issue 5, May 2014 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Analytical Study

### These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption

Basic Properties of a Digital Design These help quantify the quality of a design from different perspectives: Cost Functionality Robustness Performance Energy consumption Which of these criteria is important

### 路 論 Chapter 15 System-Level Physical Design

Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS

### Hugh de Lacy - Technical Manager Alun Jones Technical Director Micross Components Ltd., Given at CMSE, Portsmouth 2008

Shrinking Silicon Feature Sizes Consequences for Reliability Hugh de Lacy - Technical Manager Alun Jones Technical Director Micross Components Ltd., www.micross.com Given at CMSE, Portsmouth 2008 1 The

### S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India

Power reduction on clock-tree using Energy recovery and clock gating technique S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India Abstract Power consumption of

### Silicon Memories. Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) The main goal is to be cheap

Silicon Memories Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Dense -- The smaller the bits, the less area you need, and the more bits you

### McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures

McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Sheng Li, Junh Ho Ahn, Richard Strong, Jay B. Brockman, Dean M Tullsen, Norman Jouppi MICRO 2009

### Sequential 4-bit Adder Design Report

UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela

### True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique

True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique Priyanka Sharma ME (ECE) Student NITTTR Chandigarh Rajesh Mehra Associate Professor Department of ECE NITTTR Chandigarh

### PERFORMANCE EVALUATION OF 4:1 MULTIPLEXER USING DIFFERENT DOMINO LOGIC STYLES

International Journal of Electronics and Communication Engineering and Technology (IJECET) Volume 7, Issue 4, July-August 2016, pp. 20 31, Article ID: IJECET_07_04_003 Available online at http://www.iaeme.com/ijecet/issues.asp?jtype=ijecet&vtype=7&itype=4

### LOW PROPAGATION DELAY DESIGN OF 3-BIT RIPPLE COUNTER ON 0.12 MICRON TECHNOLOGY

INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS ISSN 2320-7345 LOW PROPAGATION DELAY DESIGN OF 3-BIT RIPPLE COUNTER ON 0.12 MICRON TECHNOLOGY 1 Rachit Manchanda, 2 Rajesh Mehra

### 13. Memories. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016

13. Memories Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016 October 12, 2016 ECE Department, University of Texas at Austin Lecture

### Basics of Energy & Power Dissipation

Basics of Energy & Power Dissipation ecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary Basic Concepts Dynamic power Static power Time, Energy, Power Tradeoffs Activity model for power estimation

### Index i xi xv xxvi. Abstract List of Tables List of Figures Glossary. Page.No CHAPTER 1 INTRODUCTION

iv Abstract List of Tables List of Figures Glossary Index i xi xv xxvi CHAPTER 1 INTRODUCTION 1.1 Introduction 1.2 Formulation of the problem 1.3 Objectives 1.4 Methodology 1.5 Contribution of the Thesis

### Dynamic Combinational Circuits

Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) James Morizio 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

### GDI Technique : A Power-Efficient Method for Digital Circuits

GDI Technique : A Power-Efficient Method for Digital Circuits Kunal & Nidhi Kedia Department of Electronics & Telecommunication Engineering, Synergy Institute of Engineering & Technology, Dhenkanal, Odisha

### Semiconductor Memories

Chapter 8 Semiconductor Memories (based on Kang, Leblebici. CMOS Digital Integrated Circuits 8.1 General concepts Data storage capacity available on a single integrated circuit grows exponentially being

### A Survey on Sequential Elements for Low Power Clocking System

Journal of Computer Applications ISSN: 0974 1925, Volume-5, Issue EICA2012-3, February 10, 2012 A Survey on Sequential Elements for Low Power Clocking System Bhuvana S ECE Department, Avinashilingam University

### Expanding the Synopsys PrimeTime Solution with Power Analysis

Expanding the Synopsys PrimeTime Solution with Analysis Gordon Yip, Product Marketing Manager, Synopsys, Inc. June 2006 Introduction Design closure in today s advanced designs requires a delicate balance

### Module 6 : Semiconductor Memories Lecture 28 : Static Random Access Memory (SRAM)

Module 6 : Semiconductor Memories Lecture 28 : Static Random Access Memory (SRAM) Objectives In this lecture you will learn the following SRAM Basics CMOS SRAM Cell CMOS SRAM Cell Design READ Operation

### Class 18: Memories-DRAMs

Topics: 1. Introduction 2. Advantages and Disadvantages of DRAMs 3. Evolution of DRAMs 4. Evolution of DRAMs 5. Basics of DRAMs 6. Basics of DRAMs 7. Write Operation 8. SA-Normal Operation 9. SA-Read Operation

### E&CE 437. E&CE 437 Integrated VLSI Systems. January Lecture Transparencies. (Introduction) M. Sachdev

Integrated VLSI Systems January 2002 Lecture Transparencies (Introduction) M. Sachdev 1 of 10 Course Details Instructor: M. Sachdev, msachdec@ece.uwaterloo.ca TA: Bhaskar Chatterjee, bhaskar@vlsi.uwaterloo.ca

### Pass-Transistor Logic. Topics. NMOS-Only Logic. Pass-Transistor Logic. Resistance of Transmission Gate. Pass-Transistor Logic.

Topics Transmission Gate Pass-transistor Logic 3 March 2009 1 3 March 2009 2 NMOS-Only Logic Example: AND Gate 3 March 2009 3 3 March 2009 4 Resistance of Transmission Gate XOR 3 March 2009 5 3 March 2009

### LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING

LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING A thesis work submitted to the faculty of San Francisco State University In partial fulfillment of the requirements for

### 1.1 Silicon on Insulator a brief Introduction

Table of Contents Preface Acknowledgements Chapter 1: Overview 1.1 Silicon on Insulator a brief Introduction 1.2 Circuits and SOI 1.3 Technology and SOI Chapter 2: SOI Materials 2.1 Silicon on Heteroepitaxial

### Topics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology

Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Two-phase clocking. Testing of combinational (Chapter 4) and sequential (Chapter

### Lecture 8: Latch and Flip Flop Design

Lecture 8: Latch and Flip Flop Design Slides originally from: Vladimir Stojanovic & Vojin G. Oklobdzija Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in

### Lecture 10: Latch and Flip-Flop Design. Outline

Lecture 1: Latch and Flip-Flop esign Slides orginally from: Vladimir Stojanovic Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in latches and flip-flops

### Power-Saving Techniques and Future Design of SPARC64 V/VI

Power-Saving Techniques and Future Design of SPARC64 V/VI V Aiichiro Inoue (Manuscript received May 31, 2007) The performance of high-end microprocessors has increased along with improvements in semiconductor

### ISSCC 2003 / SESSION 10 / HIGH SPEED BUILDING BLOCKS / PAPER 10.5

ISSCC 2003 / SESSION 10 / HIGH SPEED BUILDING BLOCKS / PAPER 10.5 10.5 Broadband ESD Protection Circuits in CMOS Technology Sherif Galal, Behzad Razavi Electrical Engineering Department, University of

### MOSFET DIFFERENTIAL AMPLIFIER (TWO-WEEK LAB)

page 1 of 7 MOSFET DIFFERENTIAL AMPLIFIER (TWO-WEEK LAB) BACKGROUND The MOSFET is by far the most widely used transistor in both digital and analog circuits, and it is the backbone of modern electronics.

### CMOS Power Consumption

CMOS Power Consumption Lecture 13 18-322 Fall 2003 Textbook: [Sections 5.5 5.6 6.2 (p. 257-263) 11.7.1 ] Overview Low-power design Motivation Sources of power dissipation in CMOS Power modeling Optimization

### Power Reduction Techniques in the SoC Clock Network. Clock Power

Power Reduction Techniques in the SoC Network Low Power Design for SoCs ASIC Tutorial SoC.1 Power Why clock power is important/large» Generally the signal with the highest frequency» Typically drives a

### Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems

Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH

### Imaging parallel interface RAM

Page 1 of 6 ( 4 of 32 ) United States Patent Application 20070024713 Kind Code A1 Baer; Richard L. ; et al. February 1, 2007 Imaging parallel interface RAM Abstract Imaging Parallel Interface Random Access

### Design and Simulation of 2 Bit Comparator Using SET Based Logic Circuits

Design and Simulation of 2 Bit Comparator Using SET Based Logic Circuits Mahima U. 1 Rajanna K. M. 2 Vijaykumar R. H. 3 Department of ECE, Dr. AIT Department of ECE, Dr.AIT Department of ECE, Dr AIT Abstract

### Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1

ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05

### Digital Logic Design

Digital Logic Design: An Embedded Systems Approach Using VHDL Chapter 1 Introduction and Methodology Portions of this work are from the book, Digital Logic Design: An Embedded Systems Approach Using VHDL,

### II. PROPOSED FLIP FLOP DESIGN

A Review on High Performance Low Power Conditional Discharge Flip Flop Sonam Parihar 1, Rachana Arya 2 1 P.G student, Bipin Tripathi Kumaon Institute of Technology, Dwarahat, Almora, Uttarakhand 2 Assistant

### An integrated DC-DC step-up charge pump and step-down converter in 130 nm technology

An integrated DC-DC step-up charge pump and step-down converter in 130 nm technology M. Bochenek a,b, W. Dabrowski b, F. Faccio a, J. Kaplon a a CERN, 1211 Geneva 23, Switzerland b Faculty of Physics and

### Digital Design Chapter 1 Introduction and Methodology 17 February 2010

Digital Chapter Introduction and Methodology 7 February 200 Digital : An Embedded Systems Approach Using Chapter Introduction and Methodology Digital Digital: circuits that use two voltage levels to represent

### NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential

### Architectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng

Architectural Level Power Consumption of Network Presenter: YUAN Zheng Why Architectural Low Power Design? High-speed and large volume communication among different parts on a chip Problem: Power consumption

### Layout Design and Simulation of CMOS Multiplexer

23 Layout and Simulation of CMOS Multiplexer Priti Gupta Electronics & Communication department National Institute of Teacher s Training and Research Chandigarh Rajesh Mehra Electronics & Communication

### Analysis (III) Low Power Design. Kai Huang

Analysis (III) Low Power Design Kai Huang Chinese new year: 1.3 billion urban exodus 1/28/2014 Kai.Huang@tum 2 The interactive map, which is updated hourly The thicker, brighter lines are the busiest routes.

### New Encoding Method for Low Power Sequential Access ROMs

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.13, NO.5, OCTOBER, 2013 http://dx.doi.org/10.5573/jsts.2013.13.5.443 New Encoding Method for Low Power Sequential Access ROMs Seong-Ik Cho, Ki-Sang

### Innovative improvement of fundamental metrics including power dissipation and efficiency of the ALU system

Innovative improvement of fundamental metrics including power dissipation and efficiency of the ALU system Joseph LaBauve Department of Electrical and Computer Engineering University of Central Florida

### 數 位 積 體 電 路 Digital Integrated Circuits

IEE5049 - Spring 2012 數 位 積 體 電 路 Digital Integrated Circuits Course Overview Professor Wei Hwang 黃 威 教 授 Department of Electronics Engineering National Chiao Tung University hwang@mail.nctu.edu.tw Wei

### Implementation Of High-k/Metal Gates In High-Volume Manufacturing

White Paper Implementation Of High-k/Metal Gates In High-Volume Manufacturing INTRODUCTION There have been significant breakthroughs in IC technology in the past decade. The upper interconnect layers of

### Leakage Power Analysis and Comparison of Deep Submicron Logic Gates *

Leakage Power Analysis and Comparison of Deep Submicron Logic Gates * Geoff Merrett and Bashir M. Al-Hashimi ESD Group, School of Electronics and Computer Science, University of Southampton, UK bmah@ecs.soton.ac.uk

### Arithmetic Computations of GALOIS Field In Multi-Valued Logic

Arithmetic Computations of GALOIS Field In Multi-Valued Logic Ankita. N. Sakhare & M. L. Keote Dept of Electronics and Telecommunication, Y.C.C.E, Wanadongri, Nagpur, India E-mail : sakhare.ankita@gmail.com,

### A 10,000 Frames/s 0.18 µm CMOS Digital Pixel Sensor with Pixel-Level Memory

Presented at the 2001 International Solid State Circuits Conference February 5, 2001 A 10,000 Frames/s 0.1 µm CMOS Digital Pixel Sensor with Pixel-Level Memory Stuart Kleinfelder, SukHwan Lim, Xinqiao

### Design of Energy Efficient Low Power Full Adder using Supply Voltage Gating

Design of Energy Efficient Low Power Full Adder using Supply Voltage Gating S.Nandhini 1, T.G.Dhaarani 2, P.Kokila 3, P.Premkumar 4 Assistant Professor, Dept. of ECE, Nandha Engineering College, Erode,

### Low Power and Reliable SRAM Memory Cell and Array Design

Springer Series in Advanced Microelectronics 31 Low Power and Reliable SRAM Memory Cell and Array Design Bearbeitet von Koichiro Ishibashi, Kenichi Osada 1. Auflage 2011. Buch. XI, 143 S. Hardcover ISBN

### DESIGN OF LOW POWER SRAM USING NEGATIVE BIAS TEMPERATURE INSTABILITY TECHNIQUE

DESIGN OF LOW POWER SRAM USING NEGATIVE BIAS TEMPERATURE INSTABILITY TECHNIQUE 1 SWATHI TANGELLA, 2 PREMA KUMAR MEDAPATI 1 M.Tech Student, Department of ECE, Shri Vishnu Engineering College for Women 2

### Introduction to CMOS VLSI Design

Introduction to CMOS VLSI esign Slides adapted from: N. Weste,. Harris, CMOS VLSI esign, Addison-Wesley, 3/e, 24 Introduction Integrated Circuits: many transistors on one chip Very Large Scale Integration

### Low Power and Low Frequency CMOS Ring Oscillator Design

Available online www.ejaet.com European Journal of Advances in Engineering and Technology, 2015, 2(7): 82-87 Research Article ISSN: 2394-658X Low Power and Low Frequency CMOS Ring Oscillator Design Venigalla

### HIGH FREQUENCY LOW VOLTAGE PRESCALER

International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN 2249-684X Vol. 3, Issue 1, Mar 2013, 105-112 TJPRC Pvt. Ltd. HIGH FREQUENCY LOW

### VLSI Design Verification and Testing

VLSI Design Verification and Testing Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text Michael L. Bushnell and Vishwani D. Agrawal, Essentials of Electronic Testing, for Digital,

### Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design

Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design Department of Electrical and Computer Engineering Overview The VLSI Design program is part of two tracks in the department:

### Embedded Systems. 9. Low Power Design

Embedded Systems 9. Low Power Design Lothar Thiele 9-1 Contents of Course 1. Embedded Systems Introduction 2. Software Introduction 7. System Components 10. Models 3. Real-Time Models 4. Periodic/Aperiodic

### Lecture 7: Clocking of VLSI Systems

Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 Two-Phase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10 - Clocking Note: The analysis

### Ultra Low Power Logic Gates

Website: www.ijetae.com (ISSN 225-2459, ISO 91:8 Certified Journal, Volume 3, Issue 7, July 213) Abstract In this wk, implementation of all the basic logic gates is presented using 18nm CMOS technology

### DRG-Cache: A Data Retention Gated-Ground Cache for Low Power 1

DRG-Cache: A Data Retention Gated-Ground Cache for Low Power 1 ABSTRACT In this paper we propose a novel integrated circuit and architectural level techniue to reduce leakage power consumption in high

### Photonic Networks for Data Centres and High Performance Computing

Photonic Networks for Data Centres and High Performance Computing Philip Watts Department of Electronic Engineering, UCL Yury Audzevich, Nick Barrow-Williams, Robert Mullins, Simon Moore, Andrew Moore

### Sample Final Exam FinalDay, FinalMonth, FinalYear ELEC4708: Advanced Digital Electronics Department of Electronics, Carleton University

0 0 Sample Final Exam FinalDay, FinalMonth, FinalYear ELEC4708: Advanced Digital Electronics Department of Electronics, Carleton University Instructor: Maitham Shams Exam Duration: 3 hour Booklets: None

### Multidisciplinary Research

ISSN (Online) : 2455-3662 SJIF Impact Factor :3.395 (Morocco) EPRA International Journal of Multidisciplinary Research Volume: 2 Issue: 7 July 2016 Published By : EPRA Journals CC License EPRA International

### Advanced VLSI Design CMOS Processing Technology

Isolation of transistors, i.e., their source and drains, from other transistors is needed to reduce electrical interactions between them. For technologies

### CMOS Sample-and-Hold Circuits

CMOS Sample-and-Hold Circuits ECE 1352 Reading Assignment By: Joyce Cheuk Wai Wong November 12, 2001 Department of Electrical and Computer Engineering University of Toronto 1. Introduction Sample-and-hold

### Introduction to VLSI Programming. TU/e course 2IN30. Prof.dr.ir. Kees van Berkel Dr. Johan Lukkien [Dr.ir. Ad Peeters, Philips Nat.

Introduction to VLSI Programming TU/e course 2IN30 Prof.dr.ir. Kees van Berkel Dr. Johan Lukkien [Dr.ir. Ad Peeters, Philips Nat.Lab] Introduction to VLSI Programming Goals Create silicon (CMOS) awareness

### Electrostatic Discharge (ESD)

Electrostatic Discharge (ESD) ELEC 353 Electronics II Instructor: Prof. C. Saavedra What is ESD? A sudden current flow between two objects that are at different potentials ESD currents are large and of

### Core Power Delivery Network Analysis of Core and Coreless Substrates in a Multilayer Organic Buildup Package

Core Power Delivery Network Analysis of Core and Coreless Substrates in a Multilayer Organic Buildup Package Ozgur Misman, Mike DeVita, Nozad Karim, Amkor Technology, AZ, USA 1900 S. Price Rd, Chandler,

### Low leakage and high speed BCD adder using clock gating technique

Low leakage and high speed BCD adder using clock gating technique Mr. Suri shiva 1 Mr K.R.Anudeep Laxmikanth 2 Mr. Naveen Kumar.Ch 3 Abstract The growing market of mobile, battery powered electronic systems

### On-Chip Interconnect: The Past, Present, and Future

On-Chip Interconnect: The Past, Present, and Future Professor Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester URL: http://www.ece.rochester.edu/~friedman Future

### II. IMPLICIT-TYPE P-FF DESIGN WITH PULSE CONTROL SCHEME A.

Power Efficient Counter Design Using Conditional Pulse Enhancement Flip-Flop 1 R.Nithyalakshmi, 2 P.Sivasankar Rajamani 1 PG/VLSI Design, K.S.R College of Engineering, Thiruchengode 2 Asst. Professor,

### Chapter 1 Introduction to The Semiconductor Industry 2005 VLSI TECH. 1

Chapter 1 Introduction to The Semiconductor Industry 1 The Semiconductor Industry INFRASTRUCTURE Industry Standards (SIA, SEMI, NIST, etc.) Production Tools Utilities Materials & Chemicals Metrology Tools

### Probabilistic CMOS (PCMOS) Logic for Nanoscale Circuit Design

1 Probabilistic CMOS (PCMOS) Logic for Nanoscale Circuit Design Krishna V. Palem 1, 4, Pinar Korkmaz 2, Kiat-Seng Yeo 3, 4, and Zhi-Hui Kong 3, 4 1 Department of Computer Science, Electrical and Computer

### EEC 116 Lecture #6: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #6: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 extended, same due date as Lab 4 HW4 issued today Amirtharajah/Parkhurst,

### A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem

A Novel Low Power, High Speed 4 Transistor CMOS Full Adder Cell with 5% Improvement in Threshold Loss Problem T. Vigneswaran, B. Mukundhan, and P. Subbarami Reddy Abstract Full adders are important components

### EECS 240 Topic 7: Current Sources

EECS 240 Analog Integrated Circuits Topic 7: Current Sources Bernhard E. Boser,Ali M. Niknejad and S.Gambini Department of Electrical Engineering and Computer Sciences Bias Current Sources Applications

### Signal integrity in deep-sub-micron integrated circuits

Signal integrity in deep-sub-micron integrated circuits Alessandro Bogliolo abogliolo@ing.unife.it Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization

### A 1-GSPS CMOS Flash A/D Converter for System-on-Chip Applications

A -GSPS CMOS Flash A/D Converter for System-on-Chip Applications Jincheol Yoo, Kyusun Choi, and Ali Tangel Department of Computer Science & Department of Computer & Engineering Communications Engineering

### CHAPTER 14 CMOS DIGITAL LOGIC CIRCUITS

CHAPTER 4 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 4. Digital Logic Inverters 4. The CMOS Inverter 4.3 Dynamic Operation of the CMOS Inverter 4.4 CMOS Logic-Gate Circuits 4.5 Implications of Technology