Introduction to VLSI Programming. TU/e course 2IN30. Prof.dr.ir. Kees van Berkel Dr. Johan Lukkien [Dr.ir. Ad Peeters, Philips Nat.
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1 Introduction to VLSI Programming TU/e course 2IN30 Prof.dr.ir. Kees van Berkel Dr. Johan Lukkien [Dr.ir. Ad Peeters, Philips Nat.Lab]
2 Introduction to VLSI Programming Goals Create silicon (CMOS) awareness Understanding the metrics for Time (speed, performance) Energy (power consumption) Area (cost) Learn to design at VLSI-programming level Based on metrics Tangram silicon compiler is used as a vehicle Philips Research, Kees van Berkel,
3 Time table 2005 date class lab subject Aug hours intro; VLSI Sep hours handshake circuits Sep hours handshake circuits assignment Sep hours Tangram Sep hours demo, fifos, registers Oct. 4 no lecture Oct hours design cases; deadline assignment Oct hours DLX introduction Oct hours low-cost DLX Nov hours high-speed DLX Nov. 8 spare Nov. 29 deadline final report Philips Research, Kees van Berkel,
4 Course grading Your course grading is based on: the quality of your Tangram programs [30%]; your final report on the design and evaluation of these programs (guidelines will follow) [30%]; a concluding discussion with you on the programs, the report and the lecture notes [20%]; your results on an intermediate assignment [20%]. Philips Research, Kees van Berkel,
![[30%]; a concluding discussion with you on the programs, the report and the lecture notes](/docs-images/54/9924530/images/page_4.jpg "[20%]; your results on an intermediate assignment [20%].")
5 Lecture 1: outline ICs, Moore s Law, ITRS roadmap VLSI design and silicon compilation Tangram Handshake Technology VLSI circuits: basics, metrics, scaling Abstractions: Transistors Production rules Gates Philips Research, Kees van Berkel,
6 A Tangram pager IC Philips Research, Kees van Berkel,
7 A Tangram smartcard IC Philips Research, Kees van Berkel,
8 A mostly analog IC Philips Research, Kees van Berkel,
9 Integrated circuit 2004 typical state-of-the-art example GSM, DVD player Pentium IV area mm 2 2 cm 2 feature sie nm 90 nm supply voltage 1.2 volt 0.9 volt power consumption watt 100 watt supply current 1-10 ampere 100 ampere clock frequency MH 4 GH costs/transistor < millicent < millicent Philips Research, Kees van Berkel,
10 Typical IC in the year mm 2 32-b cpu 1Mb RAM Philips Research, Kees van Berkel,
11 Vertical cut through circuit Philips Research, Kees van Berkel,
12 Moore s Law Philips Research, Kees van Berkel,
13 Moore s Law Status 1970: 1 kbit RAM 4-bit µprocessor (2,300 transistors) Gorden Moore (Intel): the number of transistors per IC will double each year Moore [1975]: doubling every 1.5 year Philips Research, Kees van Berkel,
![transistors per IC will double each year Moore [1975]:](/docs-images/54/9924530/images/page_13.jpg "doubling every 1.")
14 Rule of two [Hu, 1993] Every 2 generations of IC technology (6 years) device feature sie 0.5 x chip sie 2 x clock frequency 2 x number of i/o pins 2 x DRAM capacity 16 x logic-gate density 4 x Philips Research, Kees van Berkel,
15 ITRS roadmap International Technology Roadmap for Semiconductors Collaborative effort of semicon industry Outlines R&D needs with 15 year horion Some 839 international experts Drive is to reduce cost per function so as enable further proliferation of computers, electronic communication and consumer electronics Philips Research, Kees van Berkel,
16 Some predictions from ITRS roadmap TU/e year feature sie [nm] DRAM [bit/chip] 64M 1 G 16 G transistors/cm 2 [M] clock freq. [GH] (1 CD ROM 6 Gbit sie human genome) Philips Research, Kees van Berkel,
![transistors/cm 2 [M] 3.7 18 84 clock freq. [GH] 0.7 1.6 2.](/docs-images/54/9924530/images/page_16.jpg "5 (1 CD ROM 6 Gbit sie human genome) Philips Research, Kees van")
17 Complexity and abstraction design productivity log (units/my) ITRS multi core + software core register gate transistor Philips Research, Kees van Berkel,
18 VLSI programming of asynchronous circuits compiler expander Tangram program Handshake circuit feedback simulator behavior, area, time, energy, test coverage Asynchronous circuit (netlist of gates) Philips Research, Kees van Berkel,
19 Tangram handshake technology High-level design method for asynchronous circuits based on handshaking Enables exploitation of the potential of asynchronous circuits without bothering about the circuit details Quoted by Prof. S.B. Furber as by far the most advanced asynchronous tool set available today Philips Research, Kees van Berkel,
20 Tangram handshake technology Design technology for clockless digital ICs Local handshake instead of global clock Handshake between active and passive partner Communication is by means of alternating request (from active to passive) and acknowledge (from passive to active) signals Active Passive Philips Research, Kees van Berkel,
21 Handshake circuits Master Task 1 Sequencer Task 2 Philips Research, Kees van Berkel,
22 Handshake circuits for low power Master Task 1 Sequencer Task 2 Philips Research, Kees van Berkel,
23 Low power Clocked 80c51 Tangram 80c51 Philips Research, Kees van Berkel,
24 Low current peaks Clocked 80c51 Tangram 80c51 Philips Research, Kees van Berkel,
25 Low electromagnetic emission Clocked 80c51 Tangram 80c51 Philips Research, Kees van Berkel,
26 Time for a break Philips Research, Kees van Berkel,
27 Some common acronyms IC: LSI: VLSI: ULSI: Integrated Circuit [1960s] Large Scale Integration [1970s] Very Large Scale Integration [1980s] Ultra Large Scale Integration [1990s] (Proposed and rejected) Transistor: Tran(sfer) (re)sistor Transfers current across a resistor Philips Research, Kees van Berkel,
28 Transistors CMOS is the dominant IC technology today (Complementary Metal Oxide Semiconductor) Two types of transistors are used PMOS and NMOS Dimensions of transistors are scaled by 2 in every new generation 0.5µ -0.35µ -0.25µ -0.18µ -0.12µ -90n -70n - This halves their area and makes them faster Philips Research, Kees van Berkel,
29 PMOS transistors Good in conducting 1 s (Power, Vdd) Poor in conducting 0 s (Ground, Vss) If V(g)=Vdd then not conducting Small leakage current only If V(g)=Vss then conducting If V(s)=Vdd then V(d):=Vdd If V(d)=Vss then V(s):=Vss+Vth gate source circle denotes inversion of control signal drain Philips Research, Kees van Berkel,
30 NMOS transistors Good in conducting 0 s (Ground, Vss) Poor in conducting 1 s (Power, Vdd) If V(g)=Vss then not conducting Small leakage current only If V(g)=Vdd then conducting If V(s)=Vdd then V(d):=Vdd-Vth If V(d)=Vss then V(s):=Vss gate source drain Philips Research, Kees van Berkel,
31 CMOS circuits Pull-up stack consisting of only P-mosts Pull-down stack consisting of only N-mosts Only inverting gates can thus be formed Vdd V + P N Pull-up Pull-down Vss Philips Research, Kees van Berkel,
32 VLSI basics Vdd (power) V + Charge Q C wire gat e Vss (ground) Philips Research, Kees van Berkel,
33 Transitions on a wire input a output Vdd (power) gate delay gate delay input a output time Vss (ground) Philips Research, Kees van Berkel,
34 VLSI basics elementary event: transition on a wire; charge Q = CV [Coulomb] moves from battery to wire (up transition), or from wire to battery (down transition) up + down transition requires energy E = QV = CV 2 [Joule] that is, ½CV 2 for a single transition Philips Research, Kees van Berkel,
35 VLSI metrics dimensionless quantities (0.12 µm CMOS): A area gate equivalent (8 µm 2, or 120,000 geq/mm 2 ) T time gate delay (0.2 nanosecond) E energy transition (0.5 picojoule) Philips Research, Kees van Berkel,
36 Energy and power Power P = f E [watt] f = frequency Example: a clock with frequency f, driving N gates consumes: P = 2 N f transitions/second with N = 10,000 gates and f = 500 MH: P = transitions/second = 5 W Philips Research, Kees van Berkel,
37 Back to transistors and gates CMOS gates are built from P-mosts and N-mosts These form inverting gates Their function can be specified using guarded commands In this context these are also known as production rules Philips Research, Kees van Berkel,
38 Gates and production rules A gate with inputs a, b, and output Behavior (function) of a gate is specified by pair of so-called production rules: F, G is a shorthand for := true is a shorthand for := false F and G are so-called guards (boolean expressions on the inputs of the gate) Philips Research, Kees van Berkel,
39 Gates and production rules Inverter with input a and output a, a a specifies the P-most (pull-up) a specifies the N-most (pull-down) Vdd a a Vss Philips Research, Kees van Berkel,
40 Gates and production rules F, G Guards must be mutually exclusive, i.e. F G must hold at any time This is to formalie the restriction to prevent short-circuit behavior must hold at any time does not necessarily require that F G or G F It may also impose a restriction on the environment of the gate Philips Research, Kees van Berkel,
41 Gates and production rules A gate is combinational if F G is a tautology and it is sequential otherwise. Guards must be stable: once a guard is true it must remain true until completion of transition. Execution of a production rule is an atomic action. Philips Research, Kees van Berkel,
42 Boolean functions and transistors Transistors can be put in series Conducting only if all conducting This implements an AND function Transistors can be put in parallel Conducting if either is conducting This implements an OR function Networks can build AND/OR functions Philips Research, Kees van Berkel,
43 NAND gate = (a b) Inverting function, hence single CMOS stage a b Two P-mosts in parallel a b Two N-mosts in series Vss a b a b Vdd a b Philips Research, Kees van Berkel,
44 AND gate Vdd = a b a b a b Non-inverting function, hence two CMOS stages First stage: NAND-gate a b y a b y Second stage: Inverter y y a b a Vss a b b y Philips Research, Kees van Berkel,
45 Combinational CMOS gates Guards of production rules are complementary This is reflected in the transistor stacks Exercise Draw transistor diagrams of Z = (A (B C )) Z = (A B) What is their delay in terms of CMOS inversions? What is their cost (area) in # transistors? Philips Research, Kees van Berkel,
46 Gates: examples inverter a a a AND gate a b a b a b majority majority(a,b,c) gate majority(a,b,c) a b c M data latch d e latch d e d e Philips Research, Kees van Berkel,
47 Gates: generalied C-elements Muller-C a b element a b a b C Asymmetric a b C-element b a b + C set-reset s latch r negating r set-reset latch s s r s r + C - + C - Philips Research, Kees van Berkel,
48 Realiation of a Majority gate: pull-up paths pull-down paths (a b) (b c) (c a) ( a b) ( b c) ( c a) Philips Research, Kees van Berkel,
49 Realiation of sequential gates Transform F, G into a combinational gate with feedback, by weakening the guards: F ( G ), G ( F ) and by using that (F G) holds invariantly: F ( G ), (F ( G )) Hence, any sequential gate can be realied by combinational gate = F ( G ). a b feedback combinational gate fork Philips Research, Kees van Berkel,
50 Realiation of sequential gates F G F ( G ) G (F ) (alternative) state holding state holding stable instable instable stable forbidden forbidden 1 0 Philips Research, Kees van Berkel,
51 Realiation of a Muller-C element Production rules: a b, a b = F ( G ) = a b ( ( a b ) ) = majority(a,b,) a b b b a a vdd a b vs s Philips Research, Kees van Berkel,
52 Realiation of Muller-C elements a b b a b a a b a b a b vdd vs s a b b c c vdd a vs s a b c a b c Philips Research, Kees van Berkel,
53 Wires and forks wire a a a fork a y a a y a a y Asymmetric a y y fork a y y isochronic a fork a a a = < y Philips Research, Kees van Berkel,
54 Next week: lecture 2 Outline: Handshake signaling Handshake behaviors; program notation Handshake components and their realiation as networks of gates Handshake circuits Philips Research, Kees van Berkel,
55
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